void
bx_cpu_c::AND_EdId(BxInstruction_t *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id;
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 & op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_AND32);
}
void
bx_cpu_c::XOR_EdGd(BxInstruction_t *i)
{
/* for 32 bit operand size mode */
Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn);
/* op1_32 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = op1_32 ^ op2_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
}
/* Opcode: VEX.66.0F.38 2C (VEX.W=0) */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMASKMOVPS_MpsHpsVps(bxInstruction_c *i)
{
BxPackedAvxRegister mask = BX_READ_AVX_REG(i->vvv()), op = BX_READ_AVX_REG(i->nnn());
unsigned len = i->getVL();
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
#if BX_SUPPORT_X86_64
if (i->as64L()) {
for (unsigned n=0; n < (4*len); n++) {
if (mask.avx32u(n) & 0x80000000) {
if (! IsCanonical(get_laddr64(i->seg(), eaddr + 4*n)))
exception(int_number(i->seg()), 0);
}
}
}
#endif
// see you can successfully write all the elements first
for (int n=4*len-1; n >= 0; n--) {
if (mask.avx32u(n) & 0x80000000)
read_RMW_virtual_dword(i->seg(), (eaddr + 4*n) & i->asize_mask());
}
for (unsigned n=0; n < (4*len); n++) {
if (mask.avx32u(n) & 0x80000000)
write_virtual_dword(i->seg(), (eaddr + 4*n) & i->asize_mask(), op.avx32u(n));
}
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::NOT_EdM(bxInstruction_c *i)
{
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op1_32 = ~op1_32;
write_RMW_virtual_dword(op1_32);
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::OR_EdIdM(bxInstruction_c *i)
{
Bit32u op1_32;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op1_32 |= i->Id();
write_RMW_virtual_dword(op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
void BX_CPU_C::NOT_Ed(bxInstruction_c *i)
{
Bit32u op1_32, result_32;
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = ~op1_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = ~op1_32;
write_RMW_virtual_dword(result_32);
}
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::XOR_EdGdM(bxInstruction_c *i)
{
Bit32u op1_32, op2_32;
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
op2_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 ^= op2_32;
write_RMW_virtual_dword(op1_32);
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
BX_NEXT_INSTR(i);
}
void BX_CPU_C::XOR_EdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id();
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = op1_32 ^ op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = op1_32 ^ op2_32;
write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
}
void BX_CPU_C::XCHG_EdGd(bxInstruction_c *i)
{
Bit32u op2_32, op1_32;
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
write_RMW_virtual_dword(op2_32);
}
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
}
void BX_CPU_C::AND_EdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id();
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
result_32 = op1_32 & op2_32;
#endif
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
#if defined(BX_HostAsm_And32)
Bit32u flags32;
asmAnd32(result_32, op1_32, op2_32, flags32);
setEFlagsOSZAPC(flags32);
#else
result_32 = op1_32 & op2_32;
#endif
write_RMW_virtual_dword(result_32);
}
#if !defined(BX_HostAsm_And32)
SET_FLAGS_OSZAPC_RESULT_32(result_32, BX_INSTR_LOGIC32);
#endif
}
void
bx_cpu_c::NOT_Ed(BxInstruction_t *i)
{
Bit32u op1_32, result_32;
/* op1 is a register or memory reference */
if (i->mod == 0xc0) {
op1_32 = BX_READ_32BIT_REG(i->rm);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg, i->rm_addr, &op1_32);
}
result_32 = ~op1_32;
/* now write result back to destination */
if (i->mod == 0xc0) {
BX_WRITE_32BIT_REG(i->rm, result_32);
}
else {
write_RMW_virtual_dword(result_32);
}
}
void BX_CPP_AttrRegparmN(1) BX_CPU_C::ENTER32_IwIb(bxInstruction_c *i)
{
Bit16u imm16 = i->Iw();
Bit8u level = i->Ib2();
level &= 0x1F;
BX_CPU_THIS_PTR speculative_rsp = 1;
BX_CPU_THIS_PTR prev_rsp = RSP;
push_32(EBP);
Bit32u frame_ptr32 = ESP;
if (BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b) {
Bit32u ebp = EBP; // Use temp copy for case of exception.
if (level > 0) {
/* do level-1 times */
while (--level) {
ebp -= 4;
Bit32u temp32 = read_virtual_dword(BX_SEG_REG_SS, ebp);
push_32(temp32);
}
/* push(frame pointer) */
push_32(frame_ptr32);
}
ESP -= imm16;
// ENTER finishes with memory write check on the final stack pointer
// the memory is touched but no write actually occurs
// emulate it by doing RMW read access from SS:ESP
read_RMW_virtual_dword(BX_SEG_REG_SS, ESP);
}
else {
Bit16u bp = BP;
if (level > 0) {
/* do level-1 times */
while (--level) {
bp -= 4;
Bit32u temp32 = read_virtual_dword(BX_SEG_REG_SS, bp);
push_32(temp32);
}
/* push(frame pointer) */
push_32(frame_ptr32);
}
SP -= imm16;
// ENTER finishes with memory write check on the final stack pointer
// the memory is touched but no write actually occurs
// emulate it by doing RMW read access from SS:SP
read_RMW_virtual_dword(BX_SEG_REG_SS, SP);
}
EBP = frame_ptr32;
BX_CPU_THIS_PTR speculative_rsp = 0;
}
