void unload_guest_pcore(struct proc *p, int guest_pcoreid)
{
struct guest_pcore *gpc;
struct per_cpu_info *pcpui = &per_cpu_info[core_id()];
gpc = lookup_guest_pcore(p, guest_pcoreid);
assert(gpc);
spin_lock(&p->vmm.lock);
assert(gpc->cpu != -1);
vmx_unload_guest_pcore(gpc);
gpc->cpu = -1;
/* Save guest's xcr0 and restore Akaros's default. */
gpc->xcr0 = rxcr0();
lxcr0(__proc_global_info.x86_default_xcr0);
/* We manage these MSRs manually. */
gpc->msr_kern_gs_base = read_kern_gsbase();
gpc->msr_star = read_msr(MSR_STAR);
gpc->msr_lstar = read_msr(MSR_LSTAR);
gpc->msr_sfmask = read_msr(MSR_SFMASK);
write_kern_gsbase((uint64_t)pcpui);
if (gpc->msr_star != AKAROS_MSR_STAR)
write_msr(MSR_STAR, AKAROS_MSR_STAR);
if (gpc->msr_lstar != AKAROS_MSR_LSTAR)
write_msr(MSR_LSTAR, AKAROS_MSR_LSTAR);
if (gpc->msr_sfmask, AKAROS_MSR_SFMASK)
write_msr(MSR_SFMASK, AKAROS_MSR_SFMASK);
/* As soon as we unlock, this gpc can be started on another core */
spin_unlock(&p->vmm.lock);
pcpui->guest_pcoreid = -1;
}
// Extract each core RRPL Data elapsed data
int32_t core_data_elapsed ( int32_t core , struct CoreData * core_data ) {
long long result;
if ( core_data[core].core_id != core ) { exit ( 0 ); }
result=read_msr(core_data[core].msr_fd,MSR_PKG_ENERGY_STATUS);
core_data[core].package_after=(double)result*core_data[core].energy_units;
result=read_msr(core_data[core].msr_fd,MSR_PP0_ENERGY_STATUS);
core_data[core].pp0_after=(double)result*core_data[core].energy_units;
/* not available on SandyBridge-EP */
if ((cpu_model==CPU_SANDYBRIDGE) || (cpu_model==CPU_IVYBRIDGE) ||
(cpu_model==CPU_HASWELL) || (cpu_model==CPU_HASWELL_EP) ) {
result=read_msr(core_data[core].msr_fd,MSR_PP1_ENERGY_STATUS);
core_data[core].pp1_after=(double)result*core_data[core].energy_units;
}
if ((cpu_model==CPU_SANDYBRIDGE_EP) || (cpu_model==CPU_IVYBRIDGE_EP) ||
(cpu_model==CPU_HASWELL) || (cpu_model==CPU_HASWELL_EP) ) {
result=read_msr(core_data[core].msr_fd,MSR_DRAM_ENERGY_STATUS);
core_data[core].dram_after=(double)result*core_data[core].energy_units;
}
}
/* Enable prefetch on core2 */
static int enable_prefetch_core2(int core) {
int fd;
uint64_t result;
int begin,end,c;
printf("Enable all prefetch\n");
if (core==-1) {
begin=0;
end=1024;
}
else {
begin=core;
end=core;
}
for(c=begin;c<=end;c++) {
fd=open_msr(c);
if (fd<0) break;
/* Read original results */
result=read_msr(fd,CORE2_PREFETCH_MSR);
printf("\tCore %d old : L2HW=%c L2ADJ=%c DCU=%c DCUIP=%c\n",
c,
result&(1ULL<<9)?'N':'Y',
result&(1ULL<<19)?'N':'Y',
result&(1ULL<<37)?'N':'Y',
result&(1ULL<<39)?'N':'Y'
);
/* Enable all */
result &= ~((1ULL<<9)|(1ULL<<19)|(1ULL<<37)|(1ULL<<39));
result=write_msr(fd,CORE2_PREFETCH_MSR,result);
/* Verify change */
result=read_msr(fd,CORE2_PREFETCH_MSR);
printf("\tCore %d new : L2HW=%c L2ADJ=%c DCU=%c DCUIP=%c\n",
c,
result&(1ULL<<9)?'N':'Y',
result&(1ULL<<19)?'N':'Y',
result&(1ULL<<37)?'N':'Y',
result&(1ULL<<39)?'N':'Y'
);
close(fd);
}
return 0;
}
/* Enable prefetch on nehalem and newer */
static int enable_prefetch_nhm(int core) {
int fd;
int result;
int begin,end,c;
printf("Enable all prefetch\n");
if (core==-1) {
begin=0;
end=1024;
}
else {
begin=core;
end=core;
}
for(c=begin;c<=end;c++) {
fd=open_msr(c);
if (fd<0) break;
/* Read original results */
result=read_msr(fd,NHM_PREFETCH_MSR);
printf("\tCore %d old : L2HW=%c L2ADJ=%c DCU=%c DCUIP=%c\n",
c,
result&0x1?'N':'Y',
result&0x2?'N':'Y',
result&0x4?'N':'Y',
result&0x8?'N':'Y'
);
/* Enable all */
result=write_msr(fd,NHM_PREFETCH_MSR,0x0);
/* Verify change */
result=read_msr(fd,NHM_PREFETCH_MSR);
printf("\tCore %d new : L2HW=%c L2ADJ=%c DCU=%c DCUIP=%c\n",
c,
result&0x1?'N':'Y',
result&0x2?'N':'Y',
result&0x4?'N':'Y',
result&0x8?'N':'Y'
);
close(fd);
}
return 0;
}
void
get_raw_power_info( int package, int domain, uint64_t *pval ){
switch(domain){
case PKG_DOMAIN: read_msr( package, MSR_PKG_POWER_INFO, pval );
break;
#ifdef ARCH_062D
case DRAM_DOMAIN: read_msr( package, MSR_DRAM_POWER_INFO, pval );
break;
#endif
default: assert(0); // Not avail for PP0/PP1 domains.
break;
}
}
void
get_raw_policy( int package, int domain, uint64_t *ppolicy ){
switch( domain ){
case PP0_DOMAIN: read_msr( package, MSR_PP0_POLICY, ppolicy );
break;
#ifdef ARCH_062A
case PP1_DOMAIN: read_msr( package, MSR_PP1_POLICY, ppolicy );
break;
#endif
default: assert(0);
break;
}
}
void rapl_init(struct PowerState * pstate){
uint64_t result = read_msr(MSR_RAPL_POWER_UNIT, pstate->msr_fh);
pstate->power_units = pow(0.5,(double)(result&0xf));
pstate->energy_units = pow(0.5,(double)((result>>8)&0x1f));
pstate->time_units = pow(0.5,(double)((result>>16)&0xf));
pstate->pkg_pwr = 0;
pstate->pp0_pwr = 0;
uint64_t initial_value = read_msr(MSR_PKG_ENERGY_STATUS, pstate->msr_fh);
do {
pstate->pkg_reg_value = read_msr(MSR_PKG_ENERGY_STATUS, pstate->msr_fh);
pstate->pp0_reg_value = read_msr(MSR_PP0_ENERGY_STATUS, pstate->msr_fh);
} while (pstate->pkg_reg_value == initial_value); // ensure a fresh reading
}
static int mperf_measure_stats(unsigned int cpu)
{
unsigned long long val;
int ret;
ret = read_msr(cpu, MSR_APERF, &val);
aperf_current_count[cpu] = val;
ret |= read_msr(cpu, MSR_MPERF, &val);
mperf_current_count[cpu] = val;
is_valid[cpu] = !ret;
return 0;
}
static int mperf_init_stats(unsigned int cpu)
{
unsigned long long val;
int ret;
ret = read_msr(cpu, MSR_APERF, &val);
aperf_previous_count[cpu] = val;
ret |= read_msr(cpu, MSR_MPERF, &val);
mperf_previous_count[cpu] = val;
is_valid[cpu] = !ret;
return 0;
}
/*
* get_aperf_mperf()
*
* Returns the current aperf/mperf MSR values of cpu
*/
static int get_aperf_mperf(unsigned int cpu, uint64_t *aperf, uint64_t *mperf)
{
int retval;
retval = read_msr(cpu, MSR_IA32_APERF, (unsigned long long*)aperf);
if (retval < 0)
return retval;
retval = read_msr(cpu, MSR_IA32_MPERF, (unsigned long long*)mperf);
if (retval < 0)
return retval;
return 0;
}
void rapl_finalize(struct PowerState * pstate){
// TODO disable signal
uint64_t case_reads = 3;
uint64_t test_reads = 3;
const uint64_t pkg_init = pstate->pkg_reg_value;
const uint64_t pp0_init = pstate->pp0_reg_value;
const uint64_t pkg_pre = read_msr(MSR_PKG_ENERGY_STATUS, pstate->msr_fh);
const uint64_t pp0_pre = read_msr(MSR_PP0_ENERGY_STATUS, pstate->msr_fh);
while(read_msr(MSR_PKG_ENERGY_STATUS, pstate->msr_fh) == pkg_pre) {
++case_reads;
}
const uint64_t pkg_post = read_msr(MSR_PKG_ENERGY_STATUS, pstate->msr_fh);
const uint64_t pp0_post = read_msr(MSR_PP0_ENERGY_STATUS, pstate->msr_fh);
while(read_msr(MSR_PKG_ENERGY_STATUS, pstate->msr_fh) == pkg_post) {
++test_reads;
}
const uint64_t pkg_exit = read_msr(MSR_PKG_ENERGY_STATUS, pstate->msr_fh);
const uint64_t pp0_exit = read_msr(MSR_PP0_ENERGY_STATUS, pstate->msr_fh);
double ratio = ((double) case_reads) / ((double) test_reads);
// Should be max of what it is, post - (exit - post) * case_reads / test_reads)
pstate->pkg_reg_value = fmax(pkg_pre, (uint64_t) pkg_post - (pkg_exit - pkg_post)
* ratio);
pstate->pp0_reg_value = fmax(pp0_pre, (uint64_t) pp0_post - (pp0_exit - pp0_post)
* ratio);
pstate->pkg_pwr += (pstate->pkg_reg_value - pkg_init) * pstate->energy_units;
pstate->pp0_pwr += (pstate->pp0_reg_value - pp0_init) * pstate->energy_units;
}
int main(void) {
int fd;
long long result;
double power_units,energy_units,time_units;
double package_before,package_after;
double pp0_before,pp0_after;
double pp1_before=0.0,pp1_after;
double dram_before=0.0,dram_after;
double thermal_spec_power,minimum_power,maximum_power,time_window;
int cpu_model;
double power_target = 500;
printf("Starting set each package power to %fW\n",power_target);
fd=open_msr(0);
/* Calculate the units used */
result=read_msr(fd,MSR_RAPL_POWER_UNIT);
power_units=pow(0.5,(double)(result&0xf));
// printf("Power units = %.3fW\n",power_units);
// printf("\n");
energy_units=pow(0.5,(double)((result>>8)&0x1f));
// printf("Energy units = %.8fJ\n",energy_units);
// printf("\n");
time_units=pow(0.5,(double)((result>>16)&0xf));
// printf("Time units = %.8fs, %.8fKs\n",time_units, time_units*1000.0);
// printf("\n");
set_power_limit(fd, power_target, power_units);
fd=open_msr(8);
/* Calculate the units used */
result=read_msr(fd,MSR_RAPL_POWER_UNIT);
power_units=pow(0.5,(double)(result&0xf));
energy_units=pow(0.5,(double)((result>>8)&0x1f));
time_units=pow(0.5,(double)((result>>16)&0xf));
set_power_limit(fd, power_target, power_units);
return 1;
}
/* This function reads the VMX-specific MSRs
* to determine whether EPT is supported.
* See section 24.6.2 and Appenix A.3.3 of the Intel manual.
*
* Hint: the TA solution uses the read_msr() helper function.
*
* Hint: As specified in the appendix, the values in the tables
* are actually offset by 32 bits.
*
* Hint: This needs to check two MSR bits---first verifying
* that secondary VMX controls are enabled, and then that
* EPT is available.
*/
static inline bool vmx_check_ept() {
uint64_t vmx_procbased_clts = read_msr(IA32_VMX_PROCBASED_CTLS);
if(BIT(vmx_procbased_clts>>32,31))
{
//cprintf("return true in vmx_check_ept");
uint64_t vmx_procbased_clts2 = read_msr(IA32_VMX_PROCBASED_CTLS2);
if(BIT(vmx_procbased_clts2>>32,1)){
return true;
}
else
{
return false;
}
}
static int hsw_ext_get_count(enum intel_hsw_ext_id id, unsigned long long *val,
unsigned int cpu)
{
int msr;
switch (id) {
case PC8:
msr = MSR_PKG_C8_RESIDENCY;
break;
case PC9:
msr = MSR_PKG_C9_RESIDENCY;
break;
case PC10:
msr = MSR_PKG_C10_RESIDENCY;
break;
case TSC:
msr = MSR_TSC;
break;
default:
return -1;
};
if (read_msr(cpu, msr, val))
return -1;
return 0;
}
static int snb_get_count(enum intel_snb_id id, unsigned long long *val,
unsigned int cpu)
{
int msr;
switch (id) {
case C7:
msr = MSR_CORE_C7_RESIDENCY;
break;
case PC2:
msr = MSR_PKG_C2_RESIDENCY;
break;
case PC7:
msr = MSR_PKG_C7_RESIDENCY;
break;
case TSC:
msr = MSR_TSC;
break;
default:
return -1;
};
if (read_msr(cpu, msr, val))
return -1;
return 0;
}
void dump_p6_MSRs (struct cpudata *cpu)
{
unsigned long long val = 0;
if (!user_is_root)
return;
printf("P6 family MSRs:\n");
if (read_msr (cpu->number, 0x2a, &val) == 1) {
printf("Low power mode is ");
if ((val & (1<<26)) == 0)
printf("dis");
else
printf("en");
printf("abled\n");
}
/*
if (read_msr (cpu->number, 0x410, &val) == 1) {
}
*/
printf("\n");
}
static void perfmon_do_cores_status(void *opaque)
{
struct perfmon_status_env *env = (struct perfmon_status_env *) opaque;
struct perfmon_cpu_context *cctx = PERCPU_VARPTR(counters_env);
int coreno = core_id();
counter_t ccno = env->pa->cores_counters[coreno];
spin_lock_irqsave(&cctx->lock);
if (perfmon_is_fixed_event(&env->pa->ev))
env->pef->cores_values[coreno] =
read_msr(MSR_CORE_PERF_FIXED_CTR0 + ccno);
else
env->pef->cores_values[coreno] =
read_msr(MSR_IA32_PERFCTR0 + ccno);
spin_unlock_irqsave(&cctx->lock);
}
int cpufreq_has_boost_support(unsigned int cpu, int *support, int *active,
int *states)
{
struct cpupower_cpu_info cpu_info;
int ret;
unsigned long long val;
*support = *active = *states = 0;
ret = get_cpu_info(&cpu_info);
if (ret)
return ret;
if (cpupower_cpu_info.caps & CPUPOWER_CAP_AMD_CBP) {
*support = 1;
/* AMD Family 0x17 does not utilize PCI D18F4 like prior
* families and has no fixed discrete boost states but
* has Hardware determined variable increments instead.
*/
if (cpu_info.family == 0x17 || cpu_info.family == 0x18) {
if (!read_msr(cpu, MSR_AMD_HWCR, &val)) {
if (!(val & CPUPOWER_AMD_CPBDIS))
*active = 1;
}
} else {
ret = amd_pci_get_num_boost_states(active, states);
if (ret)
return ret;
}
} else if (cpupower_cpu_info.caps & CPUPOWER_CAP_INTEL_IDA)
*support = *active = 1;
return 0;
}
int cthd_msr::set_clock_mod_duty_cycle_per_cpu(int cpu, int state) {
unsigned long long val;
int ret;
// First bit is reserved
state = state << 1;
ret = read_msr(cpu, MSR_IA32_THERM_CONTROL, &val);
if (ret < 0)
return THD_ERROR;
if (!state) {
val &= ~MSR_IA32_CLK_MOD_ENABLE;
} else {
val |= MSR_IA32_CLK_MOD_ENABLE;
}
val &= ~MSR_IA32_CLK_MOD_DUTY_CYCLE_MASK;
val |= (state & MSR_IA32_CLK_MOD_DUTY_CYCLE_MASK);
ret = write_msr(cpu, MSR_IA32_THERM_CONTROL, val);
if (ret < 0) {
thd_log_warn("set_clock_mod_duty_cycle current set failed to write\n");
return THD_ERROR;
}
return THD_SUCCESS;
}
int cthd_msr::disable_turbo() {
int cpu_count = get_no_cpus();
unsigned long long val;
int ret;
for (int i = 0; i < cpu_count; ++i) {
/*
This method is recommended only for BIOS
ret = read_msr(i, MSR_IA32_MISC_ENABLE, &val);
if (ret < 0)
return THD_ERROR;
val |= MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
ret = write_msr(i, MSR_IA32_MISC_ENABLE, val);
if (ret < 0)
return THD_ERROR;
*/
ret = read_msr(i, MSR_IA32_PERF_CTL, &val);
if (ret < 0)
return THD_ERROR;
val |= TURBO_DISENGAGE_BIT;
ret = write_msr(i, MSR_IA32_PERF_CTL, val);
if (ret < 0)
return THD_ERROR;
}
thd_log_info("Turbo disabled \n");
return THD_SUCCESS;
}
void apic(void)
{
unsigned long apic_base;
apic_base = read_msr(APIC_BASE_MSR);
print("APIC base: %lx\n", apic_base);
}
void
get_raw_perf_status( int package, int domain, uint64_t *pstatus ){
switch(domain){
#ifdef PKG_PERF_STATUS_AVAILABLE
case PKG_DOMAIN: read_msr(package, MSR_PKG_PERF_STATUS, pstatus);
break;
#endif
#ifdef ARCH_062D
case DRAM_DOMAIN: read_msr(package, MSR_DRAM_PERF_STATUS, pstatus);
break;
#endif
default: assert(0);
break;
}
}
static int nhm_get_count(enum intel_nhm_id id, unsigned long long *val,
unsigned int cpu)
{
int msr;
switch (id) {
case C3:
msr = MSR_CORE_C3_RESIDENCY;
break;
case C6:
msr = MSR_CORE_C6_RESIDENCY;
break;
case PC3:
msr = MSR_PKG_C3_RESIDENCY;
break;
case PC6:
msr = MSR_PKG_C6_RESIDENCY;
break;
case TSC:
msr = MSR_TSC;
break;
default:
return -1;
};
if (read_msr(cpu, msr, val))
return -1;
return 0;
}
void
disable_turbo(int cpu){
uint64_t val;
read_msr( cpu, MSR_MISC_ENABLE, &val );
// Set bit 38 to 1.
val |= ((uint64_t)1) << 38;
write_msr( cpu, MSR_MISC_ENABLE, val );
}
void
enable_turbo(int cpu){
uint64_t val;
read_msr( cpu, MSR_MISC_ENABLE, &val );
// Set bit 38 to 0.
val &= ((uint64_t)-1) ^ ((uint64_t)1) << 38;
write_msr( cpu, MSR_MISC_ENABLE, val );
}
energy_counters_init_res energy_counters_init(energy_counters_state* state){
#if defined(__linux__)
u_int64_t result;
memset(state, 0, sizeof(energy_counters_state));
state->cpu_model=detect_cpu();
if(state->cpu_model<0){
return UNSUPPORTED_CPU_TYPE;
}
FILE *f;
int n=0;
char command[512];
f = popen("cat /proc/cpuinfo | grep 'physical id' | sort -u | wc -l", "r");
if (!f || fscanf(f, "%d", &n) == EOF) { pclose(f); return NUMBER_OF_SOCKETS_NOT_FOUND;}
pclose(f);
state->num_sockets=n;
state->sockets=(socket_state*)malloc(sizeof(socket_state)*state->num_sockets);
memset(state->sockets, 0, sizeof(socket_state)*state->num_sockets);
unsigned int i;
for(i=0; i<state->num_sockets;i++){
sprintf(command, "cat /proc/cpuinfo | egrep 'processor|physical id' | tr -d '\t' "
"| tr -d ' ' | paste -d'|' - - | grep 'physicalid:%d' "
"| cut -d '|' -f 1 | cut -d ':' -f 2 | head -1", i);
f = popen(command,"r");
if (!f || fscanf(f, "%d", &n) == EOF) { pclose(f); return PROCESSOR_PER_SOCKET_NOT_FOUND;}
pclose(f);
state->sockets[i].core=n;
state->sockets[i].fd=open_msr(n);
if(state->sockets[i].fd<0){
return IMPOSSIBLE_TO_OPEN_MSR_FILE;
}
/* Calculate the units used */
result=read_msr(state->sockets[i].fd,MSR_RAPL_POWER_UNIT);
state->sockets[i].power_per_unit=pow(0.5,(double)(result&0xf));
state->sockets[i].energy_per_unit=pow(0.5,(double)((result>>8)&0x1f));
state->sockets[i].time_per_unit=pow(0.5,(double)((result>>16)&0xf));
result=read_msr(state->sockets[i].fd,MSR_PKG_POWER_INFO);
state->sockets[i].thermal_spec_power=state->sockets[i].power_per_unit*(double)(result&0x7fff);
}
return OK;
#else
return OS_NOT_SUPPORTED;
#endif
}
static void perfmon_enable_event(int event, bool enable)
{
uint64_t gctrl = read_msr(MSR_CORE_PERF_GLOBAL_CTRL);
if (enable)
write_msr(MSR_CORE_PERF_GLOBAL_CTRL, gctrl | (1 << event));
else
write_msr(MSR_CORE_PERF_GLOBAL_CTRL, gctrl & ~(1 << event));
}
void rapl_refresh(struct PowerState * pstate){
uint64_t pkg_reg_init = pstate->pkg_reg_value;
uint64_t pp0_reg_init = pstate->pp0_reg_value;
uint64_t pkg_reg_curr = read_msr(MSR_PKG_ENERGY_STATUS, pstate->msr_fh);
uint64_t pp0_reg_curr = read_msr(MSR_PP0_ENERGY_STATUS, pstate->msr_fh);
if ( pkg_reg_init > pkg_reg_curr || pp0_reg_init > pp0_reg_curr) {
fprintf(stderr, "Wrap around detected!\n"
"\tpkg_init:\t%ld\n"
"\tpkg_curr:\t%ld\n"
"\tpp0_init:\t%ld\n"
"\tpp0_curr:\t%ld\n",
pkg_reg_init, pkg_reg_curr, pp0_reg_init, pp0_reg_curr);
}
pstate->pkg_reg_value = pkg_reg_curr;
pstate->pp0_reg_value = pp0_reg_curr;
pstate->pkg_pwr += (pkg_reg_curr - pkg_reg_init) * pstate->energy_units;
pstate->pp0_pwr += (pp0_reg_curr - pp0_reg_init) * pstate->energy_units;
}
void perfmon_interrupt(struct hw_trapframe *hw_tf, void *data)
{
int i;
struct perfmon_cpu_context *cctx = PERCPU_VARPTR(counters_env);
uint64_t gctrl, status;
spin_lock_irqsave(&cctx->lock);
/* We need to save the global control status, because we need to disable
* counters in order to be able to reset their values.
* We will restore the global control status on exit.
*/
status = read_msr(MSR_CORE_PERF_GLOBAL_STATUS);
gctrl = read_msr(MSR_CORE_PERF_GLOBAL_CTRL);
write_msr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
for (i = 0; i < (int) cpu_caps.counters_x_proc; i++) {
if (status & ((uint64_t) 1 << i)) {
if (cctx->counters[i].event) {
profiler_add_hw_sample(
hw_tf, perfmon_make_sample_event(cctx->counters + i));
write_msr(MSR_IA32_PERFCTR0 + i,
-(int64_t) cctx->counters[i].trigger_count);
}
}
}
for (i = 0; i < (int) cpu_caps.fix_counters_x_proc; i++) {
if (status & ((uint64_t) 1 << (32 + i))) {
if (cctx->fixed_counters[i].event) {
profiler_add_hw_sample(
hw_tf, perfmon_make_sample_event(cctx->fixed_counters + i));
write_msr(MSR_CORE_PERF_FIXED_CTR0 + i,
-(int64_t) cctx->fixed_counters[i].trigger_count);
}
}
}
write_msr(MSR_CORE_PERF_GLOBAL_OVF_CTRL, status);
write_msr(MSR_CORE_PERF_GLOBAL_CTRL, gctrl);
spin_unlock_irqsave(&cctx->lock);
/* We need to re-arm the IRQ as the PFM IRQ gets masked on trigger.
* Note that KVM and real HW seems to be doing two different things WRT
* re-arming the IRQ. KVM re-arms does not mask the IRQ, while real HW does.
*/
perfmon_arm_irq();
}
void
dump_rapl(){
int package;
uint64_t val;
for( package=0; package<NUM_PACKAGES; package++){
read_msr( package, MSR_PKG_ENERGY_STATUS, &val );
fprintf(stdout, "%20lu ", val);
}
fprintf(stdout, "MSR_PKG_ENERGY_STATUS\n");
for( package=0; package<NUM_PACKAGES; package++){
read_msr( package, MSR_PP0_ENERGY_STATUS, &val );
fprintf(stdout, "%20lu ", val);
}
fprintf(stdout, "MSR_PP0_ENERGY_STATUS\n");
#ifdef ARCH_062D
for( package=0; package<NUM_PACKAGES; package++){
read_msr( package, MSR_DRAM_ENERGY_STATUS, &val );
fprintf(stdout, "%20lu ", val);
}
fprintf(stdout, "MSR_DRAM_ENERGY_STATUS\n");
#endif
for( package=0; package<NUM_PACKAGES; package++){
read_msr( package, MSR_PKG_POWER_INFO, &val );
fprintf(stdout, "0x%018lx ", val);
}
fprintf(stdout, "MSR_PKG_POWER_INFO\n");
for( package=0; package<NUM_PACKAGES; package++){
read_msr( package, MSR_PKG_POWER_INFO, &val );
fprintf(stdout, "0x%018lx ", val);
}
fprintf(stdout, "MSR_DRAM_POWER_INFO\n");
for( package=0; package<NUM_PACKAGES; package++){
read_msr( package, MSR_PKG_POWER_LIMIT, &val );
fprintf(stdout, "0x%018lx ", val);
}
fprintf(stdout, "MSR_PKG_POWER_LIMIT\n");
for( package=0; package<NUM_PACKAGES; package++){
read_msr( package, MSR_PP0_POWER_LIMIT, &val );
fprintf(stdout, "0x%018lx ", val);
}
fprintf(stdout, "MSR_PP0_POWER_LIMIT\n");
#ifdef ARCH_062D
for( package=0; package<NUM_PACKAGES; package++){
read_msr( package, MSR_DRAM_POWER_LIMIT, &val );
fprintf(stdout, "0x%018lx ", val);
}
fprintf(stdout, "MSR_DRAM_POWER_LIMIT\n");
#endif
}
