void tee_mmu_set_map(struct tee_mmu_mapping *map)
{
if (map == NULL)
tee_mmu_switch(read_ttbr1(), 0);
else
tee_mmu_switch(map->ttbr0, map->ctxid);
core_tlb_maintenance(TLBINV_UNIFIEDTLB, 0);
}
default:
return "";
}
}
static __maybe_unused void print_detailed_abort(
struct abort_info *ai __maybe_unused,
const char *ctx __maybe_unused)
{
EMSG_RAW("\n");
EMSG_RAW("%s %s-abort at address 0x%" PRIxVA "%s\n",
ctx, abort_type_to_str(ai->abort_type), ai->va,
fault_to_str(ai->abort_type, ai->fault_descr));
#ifdef ARM32
EMSG_RAW(" fsr 0x%08x ttbr0 0x%08x ttbr1 0x%08x cidr 0x%X\n",
ai->fault_descr, read_ttbr0(), read_ttbr1(),
read_contextidr());
EMSG_RAW(" cpu #%zu cpsr 0x%08x\n",
get_core_pos(), ai->regs->spsr);
EMSG_RAW(" r0 0x%08x r4 0x%08x r8 0x%08x r12 0x%08x\n",
ai->regs->r0, ai->regs->r4, ai->regs->r8, ai->regs->ip);
EMSG_RAW(" r1 0x%08x r5 0x%08x r9 0x%08x sp 0x%08x\n",
ai->regs->r1, ai->regs->r5, ai->regs->r9,
read_mode_sp(ai->regs->spsr & CPSR_MODE_MASK));
EMSG_RAW(" r2 0x%08x r6 0x%08x r10 0x%08x lr 0x%08x\n",
ai->regs->r2, ai->regs->r6, ai->regs->r10,
read_mode_lr(ai->regs->spsr & CPSR_MODE_MASK));
EMSG_RAW(" r3 0x%08x r7 0x%08x r11 0x%08x pc 0x%08x\n",
ai->regs->r3, ai->regs->r7, ai->regs->r11, ai->pc);
#endif /*ARM32*/
#ifdef ARM64