int gpio_AckoutFreqSel(unsigned long Freq)
{
unsigned long tmpRead = 0;
unsigned long tmpClkV = -1;
switch(Freq) {
case 54:
tmpClkV = 0x0;
break;
case 27:
tmpClkV = 0x1;
break;
case 24:
tmpClkV = 0x2;
break;
default:
tmpClkV = -1;
break;
}
if(-1 != tmpClkV) {
tmpRead = reg_read32(PERI_CRG_REG(11));
tmpRead &= 0xFFF3FFFF;
tmpRead |= (tmpClkV << 18);
reg_write32(PERI_CRG_REG(11), tmpRead);
reg_write32(IO_CONFIG_REG(0), 1); //VI_ADC_CLK
return 0;
}
return -1;
}
void tz_set_module_apc(unsigned int module, E_MASK_DOM domain_num , APC_ATTR permission_control)
{
volatile unsigned int* base = 0;
unsigned int clr_bit = 0x3 << ((module % MOD_NO_IN_1_DEVAPC) * 2);
unsigned int set_bit = permission_control << ((module % MOD_NO_IN_1_DEVAPC) * 2);
if(domain_num == E_DOMAIN_0)
{
base = (unsigned int*) ((unsigned int)DEVAPC0_D0_APC_0 + (module/16) *4);
}
else if(domain_num == E_DOMAIN_1)
{
base = (unsigned int*) ((unsigned int)DEVAPC0_D1_APC_0 + (module/16) *4);
}
else if(domain_num == E_DOMAIN_2)
{
base = (unsigned int*) ((unsigned int)DEVAPC0_D2_APC_0 + (module/16) *4);
}
else if(domain_num == E_DOMAIN_3)
{
base = (unsigned int*) ((unsigned int)DEVAPC0_D3_APC_0 + (module/16) *4);
}
#ifdef DBG_PRELOADER
MSG(DOM, "(B)tz_set_module_apc is (0x%x) 0x%x\n", base, reg_read32(base));
#endif
reg_write32(base, reg_read32(base) & ~clr_bit);
reg_write32(base, reg_read32(base) | set_bit);
#ifdef DBG_PRELOADER
MSG(DOM, "(E)tz_set_module_apc is (0x%x) 0x%x\n", base, reg_read32(base));
#endif
}
static void tnetw1130_write0l(tnetw1130_t *s, hwaddr addr,
uint32_t value)
{
if (addr < TNETW1130_MEM0_SIZE) {
reg_write32(s->mem0, addr, value);
}
if (addr == TNETW1130_SLV_MEM_ADDR) {
s->fw_addr = value;
if (value >= TNETW1130_FW_SIZE) {
UNEXPECTED();
}
} else if (addr == TNETW1130_SLV_MEM_DATA) {
reg_write32(s->fw, s->fw_addr, value);
} else if (addr == TNETW1130_SLV_MEM_CTL) {
if (value == 0) {
TRACE(TNETW, logout("basic mode\n"));
} else if (value == 1) {
TRACE(TNETW, logout("autoincrement mode\n"));
MISSING();
} else {
UNEXPECTED();
}
} else if (addr == TNETW1130_SLV_END_CTL) {
}
TRACE(TNETW, logout("addr %s = 0x%08x\n", tnetw1130_regname(addr), value));
}
int32
cx23882_int(void *data)
{
cx23882_device *device = data;
uint32 mstat;
uint32 wmstat;
mstat = reg_read32(REG_PCI_INT_MSTAT);
if (!mstat)
return B_UNHANDLED_INTERRUPT;
if (mstat & (PCI_INT_STAT_HST_INT | PCI_INT_STAT_VIP_INT | PCI_INT_STAT_AUD_INT | PCI_INT_STAT_VID_INT)) {
// serious error, these bits should not be set
dprintf("cx23882_int error: msk 0x%08" B_PRIx32 ", stat 0x%08" B_PRIx32
", mstat 0x%08" B_PRIx32 "\n", reg_read32(REG_PCI_INT_MSK),
reg_read32(REG_PCI_INT_STAT), mstat);
reg_write32(REG_PCI_INT_MSK, 0);
return B_HANDLED_INTERRUPT;
}
wmstat = mstat & ~(PCI_INT_STAT_HST_INT | PCI_INT_STAT_VIP_INT | PCI_INT_STAT_TS_INT | PCI_INT_STAT_AUD_INT | PCI_INT_STAT_VID_INT);
if (wmstat)
reg_write32(REG_PCI_INT_STAT, wmstat);
if (wmstat)
dprintf("cx23882_int got 0x%08" B_PRIx32 "\n", wmstat);
if (mstat & PCI_INT_STAT_TS_INT) {
cx23882_mpegts_int(device);
return B_INVOKE_SCHEDULER;
} else {
return B_HANDLED_INTERRUPT;
}
}
void gpio_Platform_VerFix(int Ver)
{
if(Ver == GPIO_PROBE_VER1) {
reg_write32(IO_CONFIG_REG(1), 3); //VIU0_MODE_LSB, GPIO_MODE, fephy_dbg_out[0~7], VIU0_MODE_MSB
reg_write32(IO_CONFIG_REG(2), 3); //VIU1_MODE_LSB, GPIO_MODE, fephy_dbg_out[8~15], VIU1_MODE_MSB
}
gpio_AckoutFreqSel(27); //27MHz Output for All Support Platforms;
}
status_t
cx23882_stop_capture(cx23882_device *device)
{
TRACE("cx23882_stop_capture\n");
// stop RISC processor and DMA
reg_write32(REG_TS_DMA_CNTRL, reg_read32(REG_TS_DMA_CNTRL) & ~(TS_DMA_CNTRL_TS_FIFO_EN | TS_DMA_CNTRL_TS_RISC_EN));
reg_write32(REG_DEV_CNTRL2, reg_read32(REG_DEV_CNTRL2) & ~DEV_CNTRL2_RUN_RISC);
return B_OK;
}
status_t
cx23882_init(cx23882_device *device)
{
// assumes that cx23882_reset() has already been called
status_t err;
if ((err = cx23882_buffers_alloc(device)) < B_OK) {
dprintf("cx23882: Error, buffer alloc failed\n");
return err;
}
device->capture_size = DMA_BUFFER_SIZE;
cx23882_via_sis_fixup(device);
// Set FIFO thresholds, should be 0 < x <= 7
reg_write32(REG_PDMA_STHRSH, PDMA_ISBTHRSH_6 | PDMA_PCITHRSH_6);
reg_write32(REG_PDMA_DTHRSH, PDMA_ISBTHRSH_6 | PDMA_PCITHRSH_6);
// init risc programm
cx23882_risc_ram_setup(device);
// init sram
cx23882_sram_setup(device);
// Reset counter to 0
reg_write32(REG_TS_GP_CNT_CNTRL, 0x3);
// Line length for RISC DMA
reg_write32(REG_TS_LNGTH, BYTES_PER_LINE);
// Set serial interface mode
reg_write32(REG_TS_GEN_CONTROL, reg_read32(REG_TS_GEN_CONTROL) | TS_GEN_CONTROL_IPB_SMODE);
// Setup hardware MPEG2 fec interface
reg_write32(REG_HW_SOP_CONTROL, (MPEG2_SYNC_BYTE << 16) | (MPEG2_PACKET_SIZE << 4) | SYNC_PACKET_COUNT);
// Setup TSSTOP status, active low, rising and falling edge, single bit width
reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) | 0x18000);
reg_write32(REG_TS_SOP_STATUS, reg_read32(REG_TS_SOP_STATUS) & ~0x06000);
// Enable interrupts for MPEG TS and all errors
reg_write32(REG_PCI_INT_MSK, reg_read32(REG_PCI_INT_MSK) | PCI_INT_STAT_TS_INT | 0x00fc00);
reg_write32(REG_TS_INT_MSK, reg_read32(REG_TS_INT_MSK) | TS_INT_STAT_TS_RISC1 | TS_INT_STAT_TS_RISC2 | 0x1f1100);
TRACE("cx23882_init done\n");
return B_OK;
}
static void tnetw1130_write1l(tnetw1130_t *s, hwaddr addr,
uint32_t value)
{
assert(addr < TNETW1130_MEM1_SIZE);
reg_write32(s->mem1, addr, value);
TRACE(TNETW, logout("addr %s = 0x%08x\n", tnetw1130_regname1(addr), value));
}
static void tnetw1130_write1l(pci_tnetw1130_t * d, target_phys_addr_t addr,
uint32_t value)
{
tnetw1130_t *s = &d->tnetw1130;
assert(addr < TNETW1130_MEM1_SIZE);
reg_write32(s->mem1, addr, value);
TRACE(TNETW, logout("addr %s = 0x%08x\n", tnetw1130_regname1(addr), value));
}
static void
cx23882_via_sis_fixup(cx23882_device *device)
{
uint16 host_vendor;
uint32 dev_cntrl1;
host_vendor = gPci->read_pci_config(0, 0, 0, PCI_vendor_id, 2);
dev_cntrl1 = reg_read32(REG_F2_DEV_CNTRL1);
if (host_vendor == PCI_VENDOR_VIA || host_vendor == PCI_VENDOR_SIS) {
dprintf("cx23882: enabling VIA/SIS compatibility mode\n");
reg_write32(REG_F2_DEV_CNTRL1, dev_cntrl1 | F2_DEV_CNTRL1_EN_VSFX);
} else {
dprintf("cx23882: disabling VIA/SIS compatibility mode\n");
reg_write32(REG_F2_DEV_CNTRL1, dev_cntrl1 & ~F2_DEV_CNTRL1_EN_VSFX);
}
}
void device_APC_dom_setup(void)
{
MSG(DOM, "\nDevice APC domain init setup:\n\n");
reg_write32(DEVAPC0_APC_CON, 0x0);
#ifdef DBG_PRELOADER
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_APC_CON));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
#endif
#if defined(MACH_TYPE_MT6735)
/*Set modem0 master to DOMAIN1*/
reg_set_field(DEVAPC0_MAS_DOM_1 , MD1_DOMAIN, DOMAIN_1);
/*Set connsys master to DOMAIN2*/
reg_set_field(DEVAPC0_MAS_DOM_1 , CONN2AP, DOMAIN_2);
/*Set modem1 master to DOMAIN5*/
reg_set_field(DEVAPC0_MAS_DOM_2 , MD3_DOMAIN, DOMAIN_5);
/*Set gpu master to DOMAIN6*/
reg_set_field(DEVAPC0_MAS_DOM_2 , GPU, DOMAIN_6);
#elif defined(MACH_TYPE_MT6735M)
// Notice: Compare to Denali-2: (1)Denali-2 does not have Master "MD3" (2)Denali-2 does not have Domain 4, 5, 6, 7.
/*Set modem0 master to DOMAIN1*/
reg_set_field(DEVAPC0_MAS_DOM_0 , MD1_DOMAIN, DOMAIN_1);
/*Set connsys master to DOMAIN2*/
reg_set_field(DEVAPC0_MAS_DOM_0 , CONN2AP, DOMAIN_2);
/*Set gpu master to DOMAIN3*/
reg_set_field(DEVAPC0_MAS_DOM_1 , GPU, DOMAIN_3);
#elif defined(MACH_TYPE_MT6753)
/*Set modem0 master to DOMAIN1*/
reg_set_field(DEVAPC0_MAS_DOM_1 , MD1_DOMAIN, DOMAIN_1);
/*Set connsys master to DOMAIN2*/
reg_set_field(DEVAPC0_MAS_DOM_1 , CONN2AP, DOMAIN_2);
/*Set modem1 master to DOMAIN5*/
reg_set_field(DEVAPC0_MAS_DOM_2 , MD3_DOMAIN, DOMAIN_5);
/*Set gpu master to DOMAIN6*/
reg_set_field(DEVAPC0_MAS_DOM_2 , GPU, DOMAIN_6);
#else
#error "Wrong MACH type"
#endif
#ifdef DBG_PRELOADER
MSG(DOM, "Device APC domain after setup:\n");
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
#endif
}
static inline void
cx23882_mpegts_int(cx23882_device *device)
{
uint32 mstat = reg_read32(REG_TS_INT_MSTAT);
reg_write32(REG_TS_INT_STAT, mstat);
// dprintf("cx23882_mpegts_int got 0x%08lx\n", mstat);
if (mstat & TS_INT_STAT_OPC_ERR) {
dprintf("cx23882_mpegts_int RISC opcode error\n");
reg_write32(REG_PCI_INT_MSK, 0);
return;
}
if ((mstat & (TS_INT_STAT_TS_RISC1 | TS_INT_STAT_TS_RISC2)) == (TS_INT_STAT_TS_RISC1 | TS_INT_STAT_TS_RISC2)) {
dprintf("cx23882_mpegts_int both buffers ready\n");
mstat = TS_INT_STAT_TS_RISC1;
}
if (mstat & TS_INT_STAT_TS_RISC1) {
int32 count;
// dprintf("cx23882_mpegts_int buffer 1 at %Ld\n", system_time());
device->capture_data = device->dma_buf1_virt;
device->capture_end_time = system_time();
get_sem_count(device->capture_sem, &count);
if (count <= 0)
release_sem_etc(device->capture_sem, 1, B_DO_NOT_RESCHEDULE);
}
if (mstat & TS_INT_STAT_TS_RISC2) {
int32 count;
// dprintf("cx23882_mpegts_int buffer 2 at %Ld\n", system_time());
device->capture_data = device->dma_buf2_virt;
device->capture_end_time = system_time();
get_sem_count(device->capture_sem, &count);
if (count <= 0)
release_sem_etc(device->capture_sem, 1, B_DO_NOT_RESCHEDULE);
}
}
void device_APC_dom_setup(void)
{
MSG(DOM, "\nDevice APC domain init setup:\n\n");
reg_write32(DEVAPC0_APC_CON, 0x0);
#ifdef DBG_PRELOADER
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
#endif
/*Set modem master to DOMAIN1(MD0),DOMAIN5(MD1)*/
reg_set_field(DEVAPC0_MAS_DOM_0 , MD1_AHB_0, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD1_AXI_1, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD1_AXI_2, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD2_AHB_0, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD2_AXI_1, DOMAIN_1);
reg_set_field(DEVAPC0_MAS_DOM_1 , MD2_AXI_2, DOMAIN_1);
/*Set connsys master to DOMAIN2*/
reg_set_field(DEVAPC0_MAS_DOM_1 , CONNSYS, DOMAIN_2);
/*Set MD32 to DOMAIN3*/
reg_set_field(DEVAPC0_MAS_DOM_0 , MD32 , DOMAIN_3);
/*Set MFG to DOMAIN6*/
reg_set_field(DEVAPC0_MAS_DOM_1 , MFG , DOMAIN_6);
#ifdef DBG_PRELOADER
MSG(DOM, "Device APC domain after setup:\n");
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_0));
MSG(DOM, "Domain Setup (0x%x)\n", reg_read32(DEVAPC0_MAS_DOM_1));
#endif
}
static void gpio_mode_conf(void)
{
reg_write32(IO_CONFIG_REG(0), 0); //VIU0_CLK, GPIO0_0, VOU0_CLK
reg_write32(IO_CONFIG_REG(1), 1); //VIU0_VS, GPIO0_1, UART2_TXD
reg_write32(IO_CONFIG_REG(2), 3); //VIU0_HS, GPIO0_2, VOU1_CLK, VIU0_CLKA
reg_write32(IO_CONFIG_REG(3), 0); //VIU0_DAT15, GPIO0_3, VOU0_DATA7
reg_write32(IO_CONFIG_REG(4), 0); //VIU0_DAT14, GPIO0_4, VOU0_DATA6
reg_write32(IO_CONFIG_REG(5), 0); //VIU0_DAT13, GPIO0_5, VOU0_DATA5
reg_write32(IO_CONFIG_REG(6), 0); //VIU0_DAT12, GPIO0_6, VOU0_DATA4
reg_write32(IO_CONFIG_REG(7), 0); //VIU0_DAT11, GPIO0_7, VOU0_DATA3
reg_write32(IO_CONFIG_REG(8), 0); //VIU0_DAT10, GPIO1_0, VOU0_DATA2
reg_write32(IO_CONFIG_REG(9), 0); //VIU0_DAT9, GPIO1_1, VOU0_DATA1
reg_write32(IO_CONFIG_REG(10), 0); //VIU0_DAT8, GPIO1_2, VOU0_DATA0
reg_write32(IO_CONFIG_REG(11), 0); //VIU0_DAT7, GPIO1_3, VOU1_DATA7
reg_write32(IO_CONFIG_REG(12), 0); //VIU0_DAT6, GPIO1_4, VOU1_DATA6
reg_write32(IO_CONFIG_REG(13), 0); //VIU0_DAT5, GPIO1_5, VOU1_DATA5
reg_write32(IO_CONFIG_REG(14), 0); //VIU0_DAT4, GPIO1_6, VOU1_DATA4
reg_write32(IO_CONFIG_REG(15), 0); //VIU0_DAT3, GPIO1_7, VOU1_DATA3
reg_write32(IO_CONFIG_REG(16), 0); //VIU0_DAT2, GPIO2_0, VOU1_DATA2
reg_write32(IO_CONFIG_REG(17), 0); //VIU0_DAT1, GPIO2_1, VOU1_DATA1
reg_write32(IO_CONFIG_REG(18), 0); //VIU0_DAT0, GPIO2_2, VOU1_DATA0
reg_write32(IO_CONFIG_REG(19), 0); //VIU1_CLK, GPIO2_3, VOU2_CLK, VIU4_CLK
reg_write32(IO_CONFIG_REG(20), 0); //VIU1_VS, GPIO2_4, UART2_RXD
reg_write32(IO_CONFIG_REG(21), 0); //VIU1_HS, GPIO2_5, VOU3_CLK, VIU1_CLKA
reg_write32(IO_CONFIG_REG(22), 0); //VIU1_DAT15, GPIO2_6, VOU2_DATA7, VIU4_DAT15
reg_write32(IO_CONFIG_REG(23), 0); //VIU1_DAT14, GPIO2_7, VOU2_DATA6, VIU4_DAT14
reg_write32(IO_CONFIG_REG(24), 0); //VIU1_DAT13, GPIO3_0, VOU2_DATA5, VIU4_DAT13
reg_write32(IO_CONFIG_REG(25), 0); //VIU1_DAT12, GPIO3_1, VOU2_DATA4, VIU4_DAT12
reg_write32(IO_CONFIG_REG(26), 0); //VIU1_DAT11, GPIO3_2, VOU2_DATA3, VIU4_DAT11
reg_write32(IO_CONFIG_REG(27), 0); //VIU1_DAT10, GPIO3_3, VOU2_DATA2, VIU4_DAT10
reg_write32(IO_CONFIG_REG(28), 0); //VIU1_DAT9, GPIO3_4, VOU2_DATA1, VIU4_DAT9
reg_write32(IO_CONFIG_REG(29), 0); //VIU1_DAT8, GPIO3_5, VOU2_DATA0, VIU4_DAT8
reg_write32(IO_CONFIG_REG(30), 0); //VIU1_DAT7, GPIO3_6, VOU3_DATA7, VIU4_DAT7
reg_write32(IO_CONFIG_REG(31), 0); //VIU1_DAT6, GPIO3_7, VOU3_DATA6, VIU4_DAT6
reg_write32(IO_CONFIG_REG(32), 0); //VIU1_DAT5, GPIO4_0, VOU3_DATA5, VIU4_DAT5
reg_write32(IO_CONFIG_REG(33), 0); //VIU1_DAT4, GPIO4_1, VOU3_DATA4, VIU4_DAT4
reg_write32(IO_CONFIG_REG(34), 0); //VIU1_DAT3, GPIO4_2, VOU3_DATA3, VIU4_DAT3
reg_write32(IO_CONFIG_REG(35), 0); //VIU1_DAT2, GPIO4_3, VOU3_DATA2, VIU4_DAT2
reg_write32(IO_CONFIG_REG(36), 0); //VIU1_DAT1, GPIO4_4, VOU3_DATA1, VIU4_DAT1
reg_write32(IO_CONFIG_REG(37), 0); //VIU1_DAT0, GPIO4_5, VOU3_DATA0, VIU4_DAT0
reg_write32(IO_CONFIG_REG(38), 0); //VIU2_CLK, GPIO4_6, VOU4_CLK
reg_write32(IO_CONFIG_REG(39), 2); //VIU2_VS, GPIO4_7, UART3_TXD
reg_write32(IO_CONFIG_REG(40), 3); //VIU2_HS, GPIO5_0, VOU5_CLK, VIU2_CLKA
reg_write32(IO_CONFIG_REG(41), 0); //VIU2_DAT15, GPIO5_1, VOU4_DATA7
reg_write32(IO_CONFIG_REG(42), 0); //VIU2_DAT14, GPIO5_2, VOU4_DATA6
reg_write32(IO_CONFIG_REG(43), 0); //VIU2_DAT13, GPIO5_3, VOU4_DATA5
reg_write32(IO_CONFIG_REG(44), 0); //VIU2_DAT12, GPIO5_4, VOU4_DATA4
reg_write32(IO_CONFIG_REG(45), 0); //VIU2_DAT11, GPIO5_5, VOU4_DATA3
reg_write32(IO_CONFIG_REG(46), 0); //VIU2_DAT10, GPIO5_6, VOU4_DATA2
reg_write32(IO_CONFIG_REG(47), 0); //VIU2_DAT9, GPIO5_7, VOU4_DATA1
reg_write32(IO_CONFIG_REG(48), 0); //VIU2_DAT8, GPIO6_0, VOU4_DATA0
reg_write32(IO_CONFIG_REG(49), 0); //VIU2_DAT7, GPIO6_1, VOU5_DATA7
reg_write32(IO_CONFIG_REG(50), 0); //VIU2_DAT6, GPIO6_2, VOU5_DATA6
reg_write32(IO_CONFIG_REG(51), 0); //VIU2_DAT5, GPIO6_3, VOU5_DATA5
reg_write32(IO_CONFIG_REG(52), 0); //VIU2_DAT4, GPIO6_4, VOU5_DATA4
reg_write32(IO_CONFIG_REG(53), 0); //VIU2_DAT3, GPIO6_5, VOU5_DATA3
reg_write32(IO_CONFIG_REG(54), 0); //VIU2_DAT2, GPIO6_6, VOU5_DATA2
reg_write32(IO_CONFIG_REG(55), 0); //VIU2_DAT1, GPIO6_7, VOU5_DATA1
reg_write32(IO_CONFIG_REG(56), 0); //VIU2_DAT0, GPIO7_0, VOU5_DATA0
reg_write32(IO_CONFIG_REG(57), 1); //GPIO7_1, VGA_HS
reg_write32(IO_CONFIG_REG(58), 1); //GPIO7_2, VGA_VS
reg_write32(IO_CONFIG_REG(59), 4); //VIU3_CLK, GPIO7_3, VOU6_CLK, VOU1120_CLK, SDIO_CCLK_OUT
reg_write32(IO_CONFIG_REG(60), 2); //VIU3_VS, GPIO7_4, UART3_RXD, VOU1120_VS, SDIO_CARD_POWER_EN
reg_write32(IO_CONFIG_REG(61), 1); //VIU3_HS, GPIO7_5, VOU7_CLK, VOU1120_HS, VIU3_CLKA
reg_write32(IO_CONFIG_REG(62), 1); //VIU3_DAT15, GPIO7_6, VOU6_DATA7, VOU1120_DATA15, SDIO_CARD_DETECT
reg_write32(IO_CONFIG_REG(63), 1); //VIU3_DAT14, GPIO7_7, VOU6_DATA6, VOU1120_DATA14, SDIO_CWPR
reg_write32(IO_CONFIG_REG(64), 1); //VIU3_DAT13, GPIO8_0, VOU6_DATA5, VOU1120_DATA13, SDIO_CCMD
reg_write32(IO_CONFIG_REG(65), 1); //VIU3_DAT12, GPIO8_1, VOU6_DATA4, VOU1120_DATA12, SDIO_CDATA0
reg_write32(IO_CONFIG_REG(66), 1); //VIU3_DAT11, GPIO8_2, VOU6_DATA3, VOU1120_DATA11, SDIO_CDATA1
reg_write32(IO_CONFIG_REG(67), 1); //VIU3_DAT10, GPIO8_3, VOU6_DATA2, VOU1120_DATA10, SDIO_CDATA2
reg_write32(IO_CONFIG_REG(68), 1); //VIU3_DAT9, GPIO8_4, VOU6_DATA1, VOU1120_DATA9, SDIO_CDATA3
reg_write32(IO_CONFIG_REG(69), 1); //VIU3_DAT8, GPIO8_5, VOU6_DATA0, VOU1120_DATA8
reg_write32(IO_CONFIG_REG(70), 1); //VIU3_DAT7, GPIO8_6, VOU7_DATA7, VOU1120_DATA7
reg_write32(IO_CONFIG_REG(71), 1); //VIU3_DAT6, GPIO8_7, VOU7_DATA6, VOU1120_DATA6
reg_write32(IO_CONFIG_REG(72), 1); //VIU3_DAT5, GPIO9_0, VOU7_DATA5, VOU1120_DATA5
reg_write32(IO_CONFIG_REG(73), 1); //VIU3_DAT4, GPIO9_1, VOU7_DATA4, VOU1120_DATA4
reg_write32(IO_CONFIG_REG(74), 1); //VIU3_DAT3, GPIO9_2, VOU7_DATA3, VOU1120_DATA3
reg_write32(IO_CONFIG_REG(75), 1); //VIU3_DAT2, GPIO9_3, VOU7_DATA2, VOU1120_DATA2
reg_write32(IO_CONFIG_REG(76), 1); //VIU3_DAT1, GPIO9_4, VOU7_DATA1, VOU1120_DATA1
reg_write32(IO_CONFIG_REG(77), 1); //VIU3_DAT0, GPIO9_5, VOU7_DATA0, VOU1120_DATA0
reg_write32(IO_CONFIG_REG(78), 0); //GPIO9_6, SIO0_RCLK
reg_write32(IO_CONFIG_REG(79), 0); //GPIO9_7, SIO0_RFS
reg_write32(IO_CONFIG_REG(80), 0); //GPIO10_0, SIO0_DIN
reg_write32(IO_CONFIG_REG(81), 0); //GPIO10_1, SIO1_RCLK
reg_write32(IO_CONFIG_REG(82), 0); //GPIO10_2, SIO1_RFS
reg_write32(IO_CONFIG_REG(83), 0); //GPIO10_3, SIO1_DIN
reg_write32(IO_CONFIG_REG(84), 0); //GPIO10_4, SIO2_RCLK
reg_write32(IO_CONFIG_REG(85), 0); //GPIO10_5, SIO2_RFS
reg_write32(IO_CONFIG_REG(86), 0); //GPIO10_6, SIO2_DIN
reg_write32(IO_CONFIG_REG(87), 1); //GPIO10_7, SIO3_RCLK
reg_write32(IO_CONFIG_REG(88), 1); //GPIO11_0, SIO3_RFS
reg_write32(IO_CONFIG_REG(89), 1); //GPIO11_1, SIO3_DIN
reg_write32(IO_CONFIG_REG(90), 1); //GPIO11_2, SIO4_XCLK
reg_write32(IO_CONFIG_REG(91), 1); //GPIO11_3, SIO4_XFS
reg_write32(IO_CONFIG_REG(92), 1); //GPIO11_4, SIO4_RCLK
reg_write32(IO_CONFIG_REG(93), 1); //GPIO11_5, SIO4_RFS
reg_write32(IO_CONFIG_REG(94), 1); //GPIO11_6, SIO4_DOUT
reg_write32(IO_CONFIG_REG(95), 1); //GPIO11_7, SIO4_DIN
reg_write32(IO_CONFIG_REG(96), 0); //GPIO12_0, SPI_SCLK
reg_write32(IO_CONFIG_REG(97), 0); //GPIO12_1, SPI_SDO
reg_write32(IO_CONFIG_REG(98), 0); //GPIO12_2, SPI_SDI
reg_write32(IO_CONFIG_REG(99), 0); //GPIO12_3, SPI_CSN0
reg_write32(IO_CONFIG_REG(100), 0); //SPI_CSN6, NF_ECC_TYPE1
reg_write32(IO_CONFIG_REG(101), 0); //SPI_CSN7, NF_ECC_TYPE2, CLK_TEST_OUT0, CLK_TEST_OUT1, CLK_TEST_OUT2, CLK_TEST_OUT3
reg_write32(IO_CONFIG_REG(102), 0); //GPIO12_4, I2C_SDA
reg_write32(IO_CONFIG_REG(103), 0); //GPIO12_5, I2C_SCL
reg_write32(IO_CONFIG_REG(104), 0); //GPIO12_6, UART1_RTSN
reg_write32(IO_CONFIG_REG(105), 1); //GPIO12_7, UART1_RXD
reg_write32(IO_CONFIG_REG(106), 1); //GPIO13_0, UART1_TXD
reg_write32(IO_CONFIG_REG(107), 0); //GPIO13_1, UART1_CTSN
reg_write32(IO_CONFIG_REG(108), 0); //RGMII0_TXCK, GPIO13_2
reg_write32(IO_CONFIG_REG(109), 1); //GPIO13_3, RGMII0_CRS, RGMII0_RXER
reg_write32(IO_CONFIG_REG(110), 1); //GPIO13_4, RGMII0_COL, RGMII0_TXER
reg_write32(IO_CONFIG_REG(111), 1); //GPIO13_5, RGMII1_RXDV
reg_write32(IO_CONFIG_REG(112), 1); //GPIO13_6, RGMII1_RXD3
reg_write32(IO_CONFIG_REG(113), 1); //GPIO13_7, RGMII1_RXD2
reg_write32(IO_CONFIG_REG(114), 1); //GPIO14_0, RGMII1_RXD1
reg_write32(IO_CONFIG_REG(115), 1); //GPIO14_1, RGMII1_RXD0
reg_write32(IO_CONFIG_REG(116), 1); //GPIO14_2, RGMII1_RXCK
reg_write32(IO_CONFIG_REG(117), 1); //GPIO14_3, RGMII1_TXEN
reg_write32(IO_CONFIG_REG(118), 1); //GPIO14_4, RGMII1_TXD3
reg_write32(IO_CONFIG_REG(119), 1); //GPIO14_5, RGMII1_TXD2
reg_write32(IO_CONFIG_REG(120), 1); //GPIO14_6, RGMII1_TXD1
reg_write32(IO_CONFIG_REG(121), 1); //PLL_TEST_OUT0, RGMII1_TXD0, PLL_TEST_OUT1, PLL_TEST_OUT2, PLL_TEST_OUT3
reg_write32(IO_CONFIG_REG(122), 1); //GPIO15_0, RGMII1_TXCK
reg_write32(IO_CONFIG_REG(123), 1); //GPIO15_1, RGMII1_TXCKOUT
reg_write32(IO_CONFIG_REG(124), 1); //GPIO15_2, RGMII1_CRS, RGMII1_RXER
reg_write32(IO_CONFIG_REG(125), 1); //GPIO15_3, RGMII1_COL, RGMII1_TXER
reg_write32(IO_CONFIG_REG(126), 0); //IR_IN, GPIO15_4
reg_write32(IO_CONFIG_REG(127), 1); //NF_DQ0, GPIO15_5
reg_write32(IO_CONFIG_REG(128), 1); //NF_DQ1, GPIO15_6
reg_write32(IO_CONFIG_REG(129), 1); //NF_DQ2, GPIO15_7
reg_write32(IO_CONFIG_REG(130), 1); //NF_DQ3, GPIO16_0
reg_write32(IO_CONFIG_REG(131), 1); //NF_DQ4, GPIO16_1
reg_write32(IO_CONFIG_REG(132), 1); //NF_DQ5, GPIO16_2
reg_write32(IO_CONFIG_REG(133), 1); //NF_DQ6, GPIO16_3
reg_write32(IO_CONFIG_REG(134), 1); //NF_DQ7, GPIO16_4
reg_write32(IO_CONFIG_REG(135), 1); //NF_RDY0, GPIO16_5
reg_write32(IO_CONFIG_REG(136), 1); //NF_RDY1, GPIO16_6
reg_write32(IO_CONFIG_REG(137), 0); //SFC_DIO, GPIO16_7
reg_write32(IO_CONFIG_REG(138), 0); //SFC_WP_IO2, GPIO17_0
reg_write32(IO_CONFIG_REG(139), 0); //SFC_D0I, GPIO17_1
reg_write32(IO_CONFIG_REG(140), 0); //SFC_HOLD_IO3, GPIO17_2
reg_write32(IO_CONFIG_REG(141), 0); //GPIO17_3, USB0_OVRCUR
reg_write32(IO_CONFIG_REG(142), 0); //GPIO17_4, USB0_PWREN
reg_write32(IO_CONFIG_REG(143), 0); //GPIO17_5, USB1_OVRCUR
reg_write32(IO_CONFIG_REG(144), 0); //GPIO17_6, USB1_PWREN
reg_write32(IO_CONFIG_REG(145), 1); //GPIO17_7, HDMI_HOTPLUG
reg_write32(IO_CONFIG_REG(146), 1); //GPIO18_0, HDMI_CEC
reg_write32(IO_CONFIG_REG(147), 1); //GPIO18_1, HDMI_SDA
reg_write32(IO_CONFIG_REG(148), 1); //GPIO18_2, HDMI_SCL
reg_write32(IO_CONFIG_REG(149), 1); //GPIO18_3, SATA_LED_N0
reg_write32(IO_CONFIG_REG(150), 1); //GPIO18_4, SATA_LED_N1
}
static void gpio_mode_conf(void)
{
reg_write32(IO_CONFIG_REG(0), 0); //GPIO8_5, VI_ADC_CLK, CLK_TEST_OUT0, CLK_TEST_OUT1, CLK_TEST_OUT2, CLK_TEST_OUT3, RTC_TEST_CLK
reg_write32(IO_CONFIG_REG(1), 0); //VIU0_MODE_LSB, GPIO_MODE, fephy_dbg_out[0~7], VIU0_MODE_MSB
reg_write32(IO_CONFIG_REG(2), 0); //VIU1_MODE_LSB, GPIO_MODE, fephy_dbg_out[8~15], VIU1_MODE_MSB
reg_write32(IO_CONFIG_REG(3), 1); //GPIO2_0, VGA_HS
reg_write32(IO_CONFIG_REG(4), 1); //GPIO1_5, VGA_VS
reg_write32(IO_CONFIG_REG(5), 2); //AIO_MCLK, GPIO7_0, BOOT_SEL
reg_write32(IO_CONFIG_REG(6), 0); //AIO_BLCK_TX, GPIO7_1
reg_write32(IO_CONFIG_REG(7), 0); //AIO_WS_TX, GPIO7_2
reg_write32(IO_CONFIG_REG(8), 0); //AIO_SD_TX, GPIO7_3, JTAG_SEL
reg_write32(IO_CONFIG_REG(9), 0); //AIO_BLCK_RX, GPIO7_4
reg_write32(IO_CONFIG_REG(10), 0); //AIO_WS_RX, GPIO7_5
reg_write32(IO_CONFIG_REG(11), 0); //AIO_SD_RX, GPIO7_6
reg_write32(IO_CONFIG_REG(12), 0); //GPIO8_0, SPI_SCLK
reg_write32(IO_CONFIG_REG(13), 4); //PLL_TEST_OUT0, SPI_SDO, PLL_TEST_OUT1, PLL_TEST_OUT2, GPIO8_1
reg_write32(IO_CONFIG_REG(14), 0); //GPIO8_2, SPI_SDI
reg_write32(IO_CONFIG_REG(15), 0); //GPIO8_3, SPI_CSN0
reg_write32(IO_CONFIG_REG(16), 0); //GPIO8_4, SPI_CSN1, PWM_SVB
reg_write32(IO_CONFIG_REG(17), 0); //GPIO1_6, I2C_SDA
reg_write32(IO_CONFIG_REG(18), 0); //GPIO1_7, I2C_SCL
reg_write32(IO_CONFIG_REG(19), 0); //GPIO5_0, UART1_RTSN
reg_write32(IO_CONFIG_REG(20), 1); //GPIO5_1, UART1_RXD
reg_write32(IO_CONFIG_REG(21), 0); //GPIO5_2, UART1_CTSN, PWM_SVB
reg_write32(IO_CONFIG_REG(22), 1); //GPIO5_3, UART1_TXD
reg_write32(IO_CONFIG_REG(23), 1); //GPIO5_4, UART2_RXD
reg_write32(IO_CONFIG_REG(24), 1); //GPIO5_5, UART2_TXD
reg_write32(IO_CONFIG_REG(25), 1); //GPIO7_7, IR_IN
reg_write32(IO_CONFIG_REG(26), 0); //GPIO6_0, USB0_OVRCUR
reg_write32(IO_CONFIG_REG(27), 0); //GPIO6_1, USB0_PWREN
reg_write32(IO_CONFIG_REG(28), 0); //GPIO6_2, USB1_OVRCUR
reg_write32(IO_CONFIG_REG(29), 0); //GPIO6_3, USB1_PWREN
reg_write32(IO_CONFIG_REG(30), 1); //GPIO6_4, HDMI_HOTPLUG
reg_write32(IO_CONFIG_REG(31), 1); //GPIO6_5, HDMI_CEC
reg_write32(IO_CONFIG_REG(32), 1); //GPIO6_6, HDMI_SDA
reg_write32(IO_CONFIG_REG(33), 1); //GPIO6_7, HDMI_SCL
reg_write32(IO_CONFIG_REG(34), 0); //GPIO2_1, SATA_LED_N0
reg_write32(IO_CONFIG_REG(35), 0); //GPIO2_2, SATA_LED_N1
reg_write32(IO_CONFIG_REG(36), 1); //GPIO5_6, ETH_LED1
reg_write32(IO_CONFIG_REG(37), 1); //GPIO5_7, ETH_LED0
reg_write32(IO_CONFIG_REG(38), 0); //GPIO0_0, RMII_CLK
reg_write32(IO_CONFIG_REG(39), 0); //GPIO0_1, RMII_TX_EN
reg_write32(IO_CONFIG_REG(40), 0); //GPIO0_2, RMII_TXD0
reg_write32(IO_CONFIG_REG(41), 0); //GPIO0_3, RMII_TXD1
reg_write32(IO_CONFIG_REG(42), 0); //GPIO0_4, RMII_CRS_DV
reg_write32(IO_CONFIG_REG(43), 0); //GPIO0_5, RMII_RXD0
reg_write32(IO_CONFIG_REG(44), 0); //GPIO0_6, RMII_RXD1
reg_write32(IO_CONFIG_REG(45), 0); //GPIO0_7, RMII_RX_ER
reg_write32(IO_CONFIG_REG(46), 1); //GPIO1_0, UART3_TXD
reg_write32(IO_CONFIG_REG(47), 1); //GPIO1_1, UART3_RXD
reg_write32(IO_CONFIG_REG(48), 0); //GPIO1_2, TEMPER_DQ
reg_write32(IO_CONFIG_REG(49), 0); //GPIO1_3, MDCK
reg_write32(IO_CONFIG_REG(50), 0); //GPIO1_4, MDIO
gpio_Platform_VerFix(gpio_Platform_VerProbe());
}
void
cx23882_reset(cx23882_device *device)
{
// software reset (XXX Test)
reg_write32(0x38c06c, 1);
snooze(200000);
// disable RISC controller
reg_write32(REG_DEV_CNTRL2, 0);
// disable TS interface DMA
reg_write32(REG_TS_DMA_CNTRL, 0x0);
// disable VIP interface up- & downstram DMA
reg_write32(REG_VIP_STREAM_EN, 0x0);
// disable host interface up- & downstram DMA
reg_write32(REG_HST_STREAM_EN, 0x0);
// stop all interrupts
reg_write32(REG_PCI_INT_MSK, 0x0);
reg_write32(REG_VID_INT_MSK, 0x0);
reg_write32(REG_AUD_INT_MSK, 0x0);
reg_write32(REG_TS_INT_MSK, 0x0);
reg_write32(REG_VIP_INT_MSK, 0x0);
reg_write32(REG_HST_INT_MSK, 0x0);
reg_write32(REG_DMA_RISC_INT_MSK, 0x0);
// clear all pending interrupts
reg_write32(REG_PCI_INT_STAT, 0xffffffff);
reg_write32(REG_VID_INT_STAT, 0xffffffff);
reg_write32(REG_AUD_INT_STAT, 0xffffffff);
reg_write32(REG_TS_INT_STAT, 0xffffffff);
reg_write32(REG_VIP_INT_STAT, 0xffffffff);
reg_write32(REG_HST_INT_STAT, 0xffffffff);
reg_write32(REG_DMA_RISC_INT_MSK, 0xffffffff);
}
static void
cx23882_sram_setup(cx23882_device *device)
{
dprintf("cx23882_sram_setup enter\n");
// setup CDT entries for both FIFOs
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CDT, SRAM_START_ADDRESS + SRAM_BASE_FIFO_0);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CDT + 16, SRAM_START_ADDRESS + SRAM_BASE_FIFO_1);
// setup CDMS
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x00, SRAM_START_ADDRESS + SRAM_BASE_RISC_PROG);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x04, SRAM_START_ADDRESS + SRAM_BASE_CDT);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x08, (2 * 16) / 8); // FIFO count = 2
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x0c, SRAM_START_ADDRESS + SRAM_BASE_RISC_QUEUE);
reg_write32(SRAM_START_ADDRESS + SRAM_BASE_CMDS_TS + 0x10, 0x80000000 | (0x100 / 4));
// setup DMA registers
reg_write32(REG_DMA28_PTR1, SRAM_START_ADDRESS + SRAM_BASE_FIFO_0);
reg_write32(REG_DMA28_PTR2, SRAM_START_ADDRESS + SRAM_BASE_CDT);
reg_write32(REG_DMA28_CNT1, BYTES_PER_LINE / 8);
reg_write32(REG_DMA28_CNT2, (2 * 16) / 8); // FIFO count = 2
dprintf("cx23882_sram_setup leave\n");
}
