void gt64xxx_device::device_reset()
{
pci_device::device_reset();
// Configuration register defaults
m_reg[GREG_CPU_CONFIG] = m_be ? 0 : (1<<12);
m_reg[GREG_RAS_1_0_LO] = 0x0;
m_reg[GREG_RAS_1_0_HI] = 0x7;
m_reg[GREG_RAS_3_2_LO] = 0x8;
m_reg[GREG_RAS_3_2_HI] = 0xf;
m_reg[GREG_CS_2_0_LO] = 0xe0;
m_reg[GREG_CS_2_0_HI] = 0x70;
m_reg[GREG_CS_3_BOOT_LO] = 0xf8;
m_reg[GREG_CS_3_BOOT_HI] = 0x7f;
m_reg[GREG_PCI_IO_LO] = 0x80;
m_reg[GREG_PCI_IO_HI] = 0xf;
m_reg[GREG_PCI_MEM0_LO] = 0x90;
m_reg[GREG_PCI_MEM0_HI] = 0x1f;
m_reg[GREG_INTERNAL_SPACE] = 0xa0;
m_reg[GREG_PCI_MEM1_LO] = 0x790;
m_reg[GREG_PCI_MEM1_HI] = 0x1f;
m_reg[GREG_RAS0_LO] = 0x0;
m_reg[GREG_RAS0_HI] = 0x7;
m_reg[GREG_RAS1_LO] = 0x8;
m_reg[GREG_RAS1_HI] = 0xf;
m_reg[GREG_RAS2_LO] = 0x10;
m_reg[GREG_RAS2_HI] = 0x17;
m_reg[GREG_RAS3_LO] = 0x18;
m_reg[GREG_RAS3_HI] = 0x1f;
m_reg[GREG_CS0_LO] = 0xc0;
m_reg[GREG_CS0_HI] = 0xc7;
m_reg[GREG_CS1_LO] = 0xc8;
m_reg[GREG_CS1_HI] = 0xcf;
m_reg[GREG_CS2_LO] = 0xd0;
m_reg[GREG_CS2_HI] = 0xdf;
m_reg[GREG_CS3_LO] = 0xf0;
m_reg[GREG_CS3_HI] = 0xfb;
m_reg[GREG_CSBOOT_LO] = 0xfc;
m_reg[GREG_CSBOOT_HI] = 0xff;
m_reg[GREG_PCI_COMMAND] = m_be ? 0 : 1;
map_cpu_space();
regenerate_config_mapping();
m_pci_stall_state = 0;
m_retry_count = 0;
m_pci_cpu_stalled = 0;
m_cpu_stalled_offset = 0;
m_cpu_stalled_data = 0;
m_cpu_stalled_mem_mask = 0;
m_dma_active = 0;
m_dma_timer->adjust(attotime::never);
m_last_dma = 0;
m_prev_addr = 0;
}
void pci_bridge_device::device_reset()
{
pci_device::device_reset();
bridge_control = 0x0000;
primary_bus = 0x00;
secondary_bus = 0x00;
subordinate_bus = 0x00;
regenerate_config_mapping();
}
void gt64xxx_device::device_reset()
{
pci_device::device_reset();
// Configuration register defaults
m_reg[GREG_CPU_CONFIG] = m_be ? 0 : (1<<12);
m_reg[GREG_RAS_1_0_LO] = 0x0;
m_reg[GREG_RAS_1_0_HI] = 0x7;
m_reg[GREG_RAS_3_2_LO] = 0x8;
m_reg[GREG_RAS_3_2_HI] = 0xf;
m_reg[GREG_CS_2_0_LO] = 0xe0;
m_reg[GREG_CS_2_0_HI] = 0x70;
m_reg[GREG_CS_3_BOOT_LO] = 0xf8;
m_reg[GREG_CS_3_BOOT_HI] = 0x7f;
m_reg[GREG_PCI_IO_LO] = 0x80;
m_reg[GREG_PCI_IO_HI] = 0xf;
m_reg[GREG_PCI_MEM0_LO] = 0x90;
m_reg[GREG_PCI_MEM0_HI] = 0x1f;
m_reg[GREG_INTERNAL_SPACE] = 0xa0;
m_reg[GREG_PCI_MEM1_LO] = 0x790;
m_reg[GREG_PCI_MEM1_HI] = 0x1f;
m_reg[GREG_RAS0_LO] = 0x0;
m_reg[GREG_RAS0_HI] = 0x7;
m_reg[GREG_RAS1_LO] = 0x8;
m_reg[GREG_RAS1_HI] = 0xf;
m_reg[GREG_RAS2_LO] = 0x10;
m_reg[GREG_RAS2_HI] = 0x17;
m_reg[GREG_RAS3_LO] = 0x18;
m_reg[GREG_RAS3_HI] = 0x1f;
m_reg[GREG_CS0_LO] = 0xc0;
m_reg[GREG_CS0_HI] = 0xc7;
m_reg[GREG_CS1_LO] = 0xc8;
m_reg[GREG_CS1_HI] = 0xcf;
m_reg[GREG_CS2_LO] = 0xd0;
m_reg[GREG_CS2_HI] = 0xdf;
m_reg[GREG_CS3_LO] = 0xf0;
m_reg[GREG_CS3_HI] = 0xfb;
m_reg[GREG_CSBOOT_LO] = 0xfc;
m_reg[GREG_CSBOOT_HI] = 0xff;
m_reg[GREG_PCI_COMMAND] = m_be ? 0 : 1;
map_cpu_space();
regenerate_config_mapping();
}
