/** \brief init and register r6 spi bus.
*
* \param SPI: R6 SPI, e.g: SPI1,SPI2,SPI3.
* \param spi_bus_name: spi bus name, e.g: "spi1"
* \return
*
*/
rt_err_t tina_spi_bus_register(SPI_T *spi, const char *spi_bus_name)
{
int i;
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
RT_ASSERT(spi_bus_name != RT_NULL);
for (i = 0; i < ARR_LEN(spis); i++)
{
if (spi == spis[i].spi)
{
bus_software_reset_disalbe(spis[i].spi_gate);
bus_gate_clk_enalbe(spis[i].spi_gate);
spis[i].spi_bus->parent.user_data = (void *)&spis[i];
DEBUG_PRINTF("bus addr: %08X\n", (rt_uint32_t)spis[i].spi_bus);
DEBUG_PRINTF("user_data: %08X\n", (rt_uint32_t)spis[i].spi_bus->parent.user_data);
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
rt_spi_bus_register(spis[i].spi_bus, spi_bus_name, &tina_spi_ops);
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
return RT_EOK;
}
}
DEBUG_PRINTF("%s -> %d\n", __FUNCTION__, __LINE__);
return RT_ERROR;
}
void rt_hw_spi3_init(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
SPI_InitTypeDef SPI_InitStruct;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
GPIO_PinAFConfig(GPIOB,GPIO_PinSource3,GPIO_AF_SPI3);
GPIO_PinAFConfig(GPIOB,GPIO_PinSource4,GPIO_AF_SPI3);
GPIO_PinAFConfig(GPIOB,GPIO_PinSource5,GPIO_AF_SPI3);
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_Init(GPIOB, &GPIO_InitStruct);
SPI_InitStruct.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStruct.SPI_Mode = SPI_Mode_Master;
SPI_InitStruct.SPI_DataSize = SPI_DataSize_8b;
SPI_InitStruct.SPI_CPOL = SPI_CPOL_High;
SPI_InitStruct.SPI_CPHA = SPI_CPHA_2Edge;
SPI_InitStruct.SPI_NSS = SPI_NSS_Soft;
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16;
SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStruct.SPI_CRCPolynomial = 7;
SPI_Init(SPI3, &SPI_InitStruct);
SPI_Cmd(SPI3, ENABLE);
rt_spi_bus_register(&spi3_bus,"spi3",(struct rt_spi_ops *)&spi3_ops);
}
/** \brief init and register lpc spi bus.
*
* \param SPI: lpc SPI, e.g: LPC_SSP0,LPC_SSP1,LPC_SSP2.
* \param lpc_spi: lpc spi bus struct.
* \param spi_bus_name: spi bus name, e.g: "spi1"
* \return
*
*/
rt_err_t lpc_spi_register(LPC_SSP_TypeDef *SPI,
struct lpc_spi_bus *lpc_spi,
const char *spi_bus_name)
{
if (SPI == LPC_SSP0)
{
lpc_spi->SPI = LPC_SSP0;
/*enable SSP0 power/clock*/
LPC_SC->PCONP |= (0x01 << 21);
}
else if (SPI == LPC_SSP1)
{
lpc_spi->SPI = LPC_SSP1;
/*enable SSP1 power/clock*/
LPC_SC->PCONP |= (0x01 << 10);
}
else if (SPI == LPC_SSP2)
{
lpc_spi->SPI = LPC_SSP2;
/*enable SSP2 power/clock*/
LPC_SC->PCONP |= (0x01 << 20);
}
else
{
return RT_ENOSYS;
}
return rt_spi_bus_register(&lpc_spi->parent, spi_bus_name, &lpc_spi_ops);
}
int wm_hw_spi_bus_init(void)
{
rt_int16_t gpio_pin;
gpio_pin = wm_get_pin(WM_SPI_CK_PIN);
if (gpio_pin >= 0)
{
wm_spi_ck_config((enum tls_io_name)gpio_pin);
}
gpio_pin = wm_get_pin(WM_SPI_DI_PIN);
if (gpio_pin >= 0)
{
wm_spi_di_config((enum tls_io_name)gpio_pin);
}
gpio_pin = wm_get_pin(WM_SPI_DO_PIN);
if (gpio_pin >= 0)
{
wm_spi_do_config((enum tls_io_name)gpio_pin);
}
wm_spi_bus.parent.user_data = &spi;
rt_spi_bus_register(&wm_spi_bus, "spi0", &wm_spi_ops);
return RT_EOK;
}
/** \brief init and register stm32 spi bus.
*
* \param SPI: STM32 SPI, e.g: SPI1,SPI2,SPI3.
* \param stm32_spi: stm32 spi bus struct.
* \param spi_bus_name: spi bus name, e.g: "spi1"
* \return
*
*/
rt_err_t stm32_spi_register(SPI_TypeDef * SPI,
struct stm32_spi_bus * stm32_spi,
const char * spi_bus_name)
{
if(SPI == SPI1)
{
stm32_spi->SPI = SPI1;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
}
else if(SPI == SPI2)
{
stm32_spi->SPI = SPI2;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
}
else if(SPI == SPI3)
{
stm32_spi->SPI = SPI3;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
}
else
{
return RT_ENOSYS;
}
return rt_spi_bus_register(&stm32_spi->parent, spi_bus_name, &stm32_spi_ops);
}
/** \brief init and register stm32 spi bus.
*
* \param SPI: STM32 SPI, e.g: SPI1,SPI2,SPI3.
* \param stm32_spi: stm32 spi bus struct.
* \param spi_bus_name: spi bus name, e.g: "spi1"
* \return
*
*/
rt_err_t stm32_spi_register(SPI_TypeDef * SPI,
struct stm32_spi_bus * stm32_spi,
const char * spi_bus_name)
{
if(SPI == SPI1)
{
#ifdef SPI_USE_DMA
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA2, ENABLE);
/* DMA2_Stream0 DMA_Channel_3 : SPI1_RX */
/* DMA2_Stream2 DMA_Channel_3 : SPI1_RX */
stm32_spi->DMA_Stream_RX = DMA2_Stream0;
stm32_spi->DMA_Channel_RX = DMA_Channel_3;
stm32_spi->DMA_Channel_RX_FLAG_TC = DMA_FLAG_TCIF0;
/* DMA2_Stream3 DMA_Channel_3 : SPI1_TX */
/* DMA2_Stream5 DMA_Channel_3 : SPI1_TX */
stm32_spi->DMA_Stream_TX = DMA2_Stream3;
stm32_spi->DMA_Channel_TX = DMA_Channel_3;
stm32_spi->DMA_Channel_TX_FLAG_TC = DMA_FLAG_TCIF3;
#endif
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
}
else if(SPI == SPI2)
{
stm32_spi->SPI = SPI2;
#ifdef SPI_USE_DMA
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
/* DMA1_Stream3 DMA_Channel_0 : SPI2_RX */
stm32_spi->DMA_Stream_RX = DMA1_Stream3;
stm32_spi->DMA_Channel_RX = DMA_Channel_0;
stm32_spi->DMA_Channel_RX_FLAG_TC = DMA_FLAG_TCIF3;
/* DMA1_Stream4 DMA_Channel_0 : SPI2_TX */
stm32_spi->DMA_Stream_TX = DMA1_Stream4;
stm32_spi->DMA_Channel_TX = DMA_Channel_0;
stm32_spi->DMA_Channel_TX_FLAG_TC = DMA_FLAG_TCIF4;
#endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
}
else if(SPI == SPI3)
{
#ifdef SPI_USE_DMA
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
/* DMA1_Stream2 DMA_Channel_0 : SPI3_RX */
stm32_spi->DMA_Stream_RX = DMA1_Stream2;
stm32_spi->DMA_Channel_RX = DMA_Channel_0;
stm32_spi->DMA_Channel_RX_FLAG_TC = DMA_FLAG_TCIF2;
/* DMA1_Stream5 DMA_Channel_0 : SPI3_TX */
stm32_spi->DMA_Stream_TX = DMA1_Stream5;
stm32_spi->DMA_Channel_TX = DMA_Channel_0;
stm32_spi->DMA_Channel_TX_FLAG_TC = DMA_FLAG_TCIF5;
#endif
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
}
else
{
return RT_ENOSYS;
}
return rt_spi_bus_register(&stm32_spi->parent, spi_bus_name, &stm32_spi_ops);
}
/** \brief init and register stm32 spi bus.
*
* \param SPI: STM32 SPI, e.g: SPI1,SPI2,SPI3.
* \param stm32_spi: stm32 spi bus struct.
* \param spi_bus_name: spi bus name, e.g: "spi1"
* \return
*
*/
rt_err_t stm32_spi_register(SPI_TypeDef * SPI,
struct stm32_spi_bus * stm32_spi,
const char * spi_bus_name)
{
if(SPI == SPI1)
{
stm32_spi->SPI = SPI1;
#ifdef SPI_USE_DMA
// rt_kprintf("DMA \r\n");
stm32_spi->DMA_Channel_RX = DMA1_Channel2;
stm32_spi->DMA_Channel_TX = DMA1_Channel3;
stm32_spi->DMA_Channel_RX_FLAG_TC = DMA1_FLAG_TC2;
stm32_spi->DMA_Channel_RX_FLAG_TE = DMA1_FLAG_TE2;
stm32_spi->DMA_Channel_TX_FLAG_TC = DMA1_FLAG_TC3;
stm32_spi->DMA_Channel_TX_FLAG_TE = DMA1_FLAG_TE3;
#endif /* #ifdef SPI_USE_DMA */
//rt_spi_bus_register(&stm32_spi->parent, "spi1", &stm32_spi_ops);
}
else if(SPI == SPI2)
{
stm32_spi->SPI = SPI2;
#ifdef SPI_USE_DMA
stm32_spi->DMA_Channel_RX = DMA1_Channel4;
stm32_spi->DMA_Channel_TX = DMA1_Channel5;
stm32_spi->DMA_Channel_RX_FLAG_TC = DMA1_FLAG_TC4;
stm32_spi->DMA_Channel_RX_FLAG_TE = DMA1_FLAG_TE4;
stm32_spi->DMA_Channel_TX_FLAG_TC = DMA1_FLAG_TC5;
stm32_spi->DMA_Channel_TX_FLAG_TE = DMA1_FLAG_TE5;
#endif /* #ifdef SPI_USE_DMA */
//rt_spi_bus_register(&stm32_spi->parent, "spi2", &stm32_spi_ops);
}
else if(SPI == SPI3)
{
stm32_spi->SPI = SPI3;
#ifdef SPI_USE_DMA
stm32_spi->DMA_Channel_RX = DMA2_Channel1;
stm32_spi->DMA_Channel_TX = DMA2_Channel2;
stm32_spi->DMA_Channel_RX_FLAG_TC = DMA2_FLAG_TC1;
stm32_spi->DMA_Channel_RX_FLAG_TE = DMA2_FLAG_TE1;
stm32_spi->DMA_Channel_TX_FLAG_TC = DMA2_FLAG_TC2;
stm32_spi->DMA_Channel_TX_FLAG_TE = DMA2_FLAG_TE2;
#endif /* #ifdef SPI_USE_DMA */
//rt_spi_bus_register(&stm32_spi->parent, "spi3", &stm32_spi_ops);
}
else
{
return RT_ENOSYS;
}
return rt_spi_bus_register(&stm32_spi->parent, spi_bus_name, &stm32_spi_ops);
}
/** \brief init and register gd32 spi bus.
*
* \param SPI: gd32 SPI, e.g: SPI1,SPI2,SPI3.
* \param spi_bus_name: spi bus name, e.g: "spi1"
* \return
*
*/
rt_err_t gd32_spi_bus_register(uint32_t spi_periph,
//struct gd32_spi_bus * gd32_spi,
const char * spi_bus_name)
{
int i;
RT_ASSERT(spi_bus_name != RT_NULL);
for (i = 0; i < ARR_LEN(spis); i++)
{
if (spi_periph == spis[i].spi_periph)
{
rcu_periph_clock_enable(spis[i].spi_clk);
spis[i].spi_bus->parent.user_data = (void *)&spis[i];
rt_spi_bus_register(spis[i].spi_bus, spi_bus_name, &gd32_spi_ops);
return RT_EOK;
}
}
return RT_ERROR;
}
int stm32_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
{
struct rt_spi_bus *spi_bus;
struct stm32_spi *spi;
if (SPIx == SPI1)
{
spi_bus = &_spi_bus1;
spi = &_spi1;
}
else if (SPIx == SPI2)
{
spi_bus = &_spi_bus2;
spi = &_spi2;
}
else
{
return -1;
}
spi->Instance = SPIx;
spi_bus->parent.user_data = spi;
return rt_spi_bus_register(spi_bus, name, &stm_spi_ops);
}
void rt_hw_spi2_init(void)
{
GPIO_InitTypeDef GPIO_InitStruct;
SPI_InitTypeDef SPI_InitStruct;
RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
CS_Configuration();
GPIO_PinAFConfig(GPIOC,GPIO_PinSource2,GPIO_AF_SPI2);
GPIO_PinAFConfig(GPIOC,GPIO_PinSource3,GPIO_AF_SPI2);
GPIO_PinAFConfig(GPIOB,GPIO_PinSource13,GPIO_AF_SPI2);
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStruct.GPIO_Speed = GPIO_Speed_100MHz;
GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.GPIO_Pin = GPIO_Pin_13;
GPIO_Init(GPIOB, &GPIO_InitStruct);
SPI_InitStruct.SPI_Direction = SPI_Direction_2Lines_FullDuplex; // ?????
SPI_InitStruct.SPI_Mode = SPI_Mode_Master; // ???
SPI_InitStruct.SPI_DataSize = SPI_DataSize_8b; // ????8?
SPI_InitStruct.SPI_CPOL = SPI_CPOL_High; // ????,?????
SPI_InitStruct.SPI_CPHA = SPI_CPHA_2Edge;
SPI_InitStruct.SPI_NSS = SPI_NSS_Soft; // NSS???????
SPI_InitStruct.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_8; // 8??,9MHz
SPI_InitStruct.SPI_FirstBit = SPI_FirstBit_MSB; // ????
SPI_InitStruct.SPI_CRCPolynomial = 7;
SPI_Init(SPI2, &SPI_InitStruct);
SPI_Cmd(SPI2, ENABLE);
rt_spi_bus_register(&spi2_bus,"spi2",(struct rt_spi_ops *)&spi2_ops);
}
int rt_hw_spi_bus_init(uint32_t instance, const char *name)
{
kinetis_spi.ops = &kinetis_spi_ops;
return rt_spi_bus_register(&kinetis_spi, name, &kinetis_spi_ops);
}
static int rt_hw_spi_bus_init(void)
{
rt_err_t result;
for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++)
{
spi_bus_obj[i].config = &spi_config[i];
spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i];
spi_bus_obj[i].handle.Instance = spi_config[i].Instance;
if (spi_bus_obj[i].spi_dma_flag & SPI_USING_RX_DMA_FLAG)
{
/* Configure the DMA handler for Transmission process */
spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
#endif
spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
#endif
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
}
if (spi_bus_obj[i].spi_dma_flag & SPI_USING_TX_DMA_FLAG)
{
/* Configure the DMA handler for Transmission process */
spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
#endif
spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
#endif
{
rt_uint32_t tmpreg = 0x00U;
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0)
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
/* Delay after an RCC peripheral clock enabling */
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
#endif
UNUSED(tmpreg); /* To avoid compiler warnings */
}
}
result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &stm_spi_ops);
RT_ASSERT(result == RT_EOK);
LOG_D("%s bus init done", spi_config[i].bus_name);
}
return result;
}
void rt_stm32f10x_spi_init(void)
{
#ifdef USING_SPI1
/* SPI1 config */
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable SPI1 Periph clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA
| RCC_APB2Periph_AFIO | RCC_APB2Periph_SPI1,
ENABLE);
#ifdef SPI_USE_DMA
/* Enable the DMA1 Clock */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
#endif /* #ifdef SPI_USE_DMA */
/* Configure SPI1 pins: PA5-SCK, PA6-MISO and PA7-MOSI */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
} /* SPI1 config */
/* register SPI1 */
{
stm32_spi_bus_1.SPI = SPI1;
#ifdef SPI_USE_DMA
stm32_spi_bus_1.DMA_Channel_RX = DMA1_Channel2;
stm32_spi_bus_1.DMA_Channel_TX = DMA1_Channel3;
stm32_spi_bus_1.DMA_Channel_RX_FLAG_TC = DMA1_FLAG_TC2;
stm32_spi_bus_1.DMA_Channel_RX_FLAG_TE = DMA1_FLAG_TE2;
stm32_spi_bus_1.DMA_Channel_TX_FLAG_TC = DMA1_FLAG_TC3;
stm32_spi_bus_1.DMA_Channel_TX_FLAG_TE = DMA1_FLAG_TE3;
#endif /* #ifdef SPI_USE_DMA */
rt_spi_bus_register(&stm32_spi_bus_1.parent, "spi1", &stm32_spi_ops);
} /* register SPI1 */
#endif /* #ifdef USING_SPI1 */
#ifdef USING_SPI2
/* SPI config */
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable SPI2 Periph clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB,ENABLE);
/*!< Enable the SPI and GPIO clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
#ifdef SPI_USE_DMA
/* Enable the DMA1 Clock */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
#endif
/* Configure SPI2 pins: PB13-SCK, PB14-MISO and PB15-MOSI */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
/*!< SPI SCK pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; /* PB13 SPI2_SCK */
GPIO_Init(GPIOB, &GPIO_InitStructure);
/*!< SPI MISO pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14; /* PB14 SPI2_MISO */
GPIO_Init(GPIOB, &GPIO_InitStructure);
/*!< SPI MOSI pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; /* PB15 SPI2_MOSI */
GPIO_Init(GPIOB, &GPIO_InitStructure);
} /* SPI config */
/* register SPI */
{
stm32_spi_bus_2.SPI = SPI2;
#ifdef SPI_USE_DMA
stm32_spi_bus_2.DMA_Channel_RX = DMA1_Channel4;
stm32_spi_bus_2.DMA_Channel_TX = DMA1_Channel5;
stm32_spi_bus_2.DMA_Channel_RX_FLAG_TC = DMA1_FLAG_TC4;
stm32_spi_bus_2.DMA_Channel_RX_FLAG_TE = DMA1_FLAG_TE4;
stm32_spi_bus_2.DMA_Channel_TX_FLAG_TC = DMA1_FLAG_TC5;
stm32_spi_bus_2.DMA_Channel_TX_FLAG_TE = DMA1_FLAG_TE5;
#endif /* #ifdef SPI_USE_DMA */
rt_spi_bus_register(&stm32_spi_bus_2.parent, "spi2", &stm32_spi_ops);
}/* register SPI */
#endif /* #ifdef USING_SPI2 */
#ifdef USING_SPI3
/* SPI config */
{
GPIO_InitTypeDef GPIO_InitStructure;
/* Enable SPI2 Periph clock */
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB,ENABLE);
/*!< Enable the SPI and GPIO clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
#ifdef SPI_USE_DMA
/* Enable the DMA2 Clock */
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);
#endif
/* Configure SPI2 pins: PB13-SCK, PB14-MISO and PB15-MOSI */
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
/*!< SPI SCK pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13; /* PB13 SPI2_SCK */
GPIO_Init(GPIOB, &GPIO_InitStructure);
/*!< SPI MISO pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14; /* PB14 SPI2_MISO */
GPIO_Init(GPIOB, &GPIO_InitStructure);
/*!< SPI MOSI pin configuration */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; /* PB15 SPI2_MOSI */
GPIO_Init(GPIOB, &GPIO_InitStructure);
} /* SPI config */
/* register SPI */
{
stm32_spi_bus_3.SPI = SPI2;
#ifdef SPI_USE_DMA
stm32_spi_bus_3.DMA_Channel_RX = DMA2_Channel1;
stm32_spi_bus_3.DMA_Channel_TX = DMA2_Channel2;
stm32_spi_bus_3.DMA_Channel_RX_FLAG_TC = DMA2_FLAG_TC1;
stm32_spi_bus_3.DMA_Channel_RX_FLAG_TE = DMA2_FLAG_TE1;
stm32_spi_bus_3.DMA_Channel_TX_FLAG_TC = DMA2_FLAG_TC2;
stm32_spi_bus_3.DMA_Channel_TX_FLAG_TE = DMA2_FLAG_TE2;
#endif /* #ifdef SPI_USE_DMA */
rt_spi_bus_register(&stm32_spi_bus_3.parent, "spi3", &stm32_spi_ops);
}/* register SPI */
#endif /* #ifdef USING_SPI3 */
}
