static void mt7621_fe_reset(void) { u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL); rt_sysc_w32(val | MT7621_RESET_FE, SYSC_REG_RESET_CTRL); rt_sysc_w32(val, SYSC_REG_RESET_CTRL); }
static int mt7621_wdt_bootcause(void) { if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE) return WDIOF_CARDRESET; return 0; }
static int mt7620_i2s_dai_probe(struct snd_soc_dai *dai) { struct mt7620_i2s *i2s = snd_soc_dai_get_drvdata(dai); uint32_t data; mt7620_i2c_init_pcm_config(i2s); dai->playback_dma_data = &i2s->playback_dma_data; dai->capture_dma_data = &i2s->capture_dma_data; /* set share pins to i2s/gpio mode and i2c mode */ data = rt_sysc_r32(0x60); data &= 0xFFFFFFE2; data |= 0x00000018; rt_sysc_w32(data, 0x60); printk("Internal REFCLK with fractional division\n"); mt7620_i2s_write(i2s, I2S_REG_CFG0, I2S_REG_CFG0_DFT_THRES); mt7620_i2s_write(i2s, I2S_REG_CFG1, 0); mt7620_i2s_write(i2s, I2S_REG_INT_EN, 0); mt7620_i2s_write(i2s, I2S_REG_DIVINT, i2sMaster_inclk_int[7]); mt7620_i2s_write(i2s, I2S_REG_DIVCMP, i2sMaster_inclk_comp[7] | I2S_REG_CLK_EN); return 0; }
void rt305x_wdt_reset(void) { u32 t; /* enable WDT reset output on pin SRAM_CS_N */ t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); t |= RT305X_SYSCFG_SRAM_CS0_MODE_WDT << RT305X_SYSCFG_SRAM_CS0_MODE_SHIFT; rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG); }
static int ralink_deassert_device(struct reset_controller_dev *rcdev, unsigned long id) { u32 val; if (id < 8) return -1; val = rt_sysc_r32(SYSC_REG_RESET_CTRL); val &= ~BIT(id); rt_sysc_w32(val, SYSC_REG_RESET_CTRL); return 0; }
void __init ralink_clk_init(void) { unsigned long cpu_rate, sys_rate, wdt_rate, uart_rate; u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG); if (soc_is_rt305x() || soc_is_rt3350()) { t = (t >> RT305X_SYSCFG_CPUCLK_SHIFT) & RT305X_SYSCFG_CPUCLK_MASK; switch (t) { case RT305X_SYSCFG_CPUCLK_LOW: cpu_rate = 320000000; break; case RT305X_SYSCFG_CPUCLK_HIGH: cpu_rate = 384000000; break; } sys_rate = uart_rate = wdt_rate = cpu_rate / 3; } else if (soc_is_rt3352()) {