static BOOLEAN
CheckFwReadLastH2C(
IN PADAPTER Adapter,
IN u8 BoxNum
)
{
u8 valHMETFR;
BOOLEAN Result = _FALSE;
valHMETFR = rtw_read8(Adapter, REG_HMETFR);
//RT_TRACE(COMP_INIT,DBG_LOUD,("REG[%x] = %x\n", REG_HMETFR, valHMETFR));
// Do not seperate to 91C and 88C, we use the same setting. Suggested by SD4 Filen. 2009.12.03.
if(((valHMETFR>>BoxNum)&BIT0) == 0)
Result = _TRUE;
return Result;
}
void rtl8188e_sreset_linked_status_check(struct adapter *padapter)
{
u32 rx_dma_status = 0;
u8 fw_status=0;
rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
if (rx_dma_status!= 0x00){
DBG_88E("%s REG_RXDMA_STATUS:0x%08x\n",__func__,rx_dma_status);
rtw_write32(padapter,REG_RXDMA_STATUS,rx_dma_status);
}
fw_status = rtw_read8(padapter,REG_FMETHR);
if (fw_status != 0x00)
{
if (fw_status == 1)
DBG_88E("%s REG_FW_STATUS (0x%02x), Read_Efuse_Fail !! \n",__func__,fw_status);
else if (fw_status == 2)
DBG_88E("%s REG_FW_STATUS (0x%02x), Condition_No_Match !! \n",__func__,fw_status);
}
}
u1Byte
ODM_Read1Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R8(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
return rtw_read8(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
PADAPTER Adapter = pDM_Odm->Adapter;
return PlatformEFIORead1Byte(Adapter, RegAddr);
#endif
}
u8
ODM_Read1Byte(
PDM_ODM_T pDM_Odm,
u32 RegAddr
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
return RTL_R8(RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
struct rtw_adapter * Adapter = pDM_Odm->Adapter;
return rtw_read8(Adapter,RegAddr);
#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
struct rtw_adapter * Adapter = pDM_Odm->Adapter;
return PlatformEFIORead1Byte(Adapter, RegAddr);
#endif
}
static void dm_InitGPIOSetting(struct adapter *Adapter)
{
#ifdef CONFIG_BT_COEXIST
struct hal_data_8188e *hal_data = GET_HAL_DATA(Adapter);
#endif
u8 tmp1byte;
tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
#ifdef CONFIG_BT_COEXIST
/* UMB-B cut bug. We need to support the modification. */
if (IS_81xxC_VENDOR_UMC_B_CUT(hal_data->VersionID) &&
hal_data->bt_coexist.BT_Coexist)
tmp1byte |= BIT5;
#endif
rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
}
/* Turn on LED according to LedPin specified. */
void SwLedOn(struct adapter *padapter, struct LED_871x *pLed)
{
u8 LedCfg;
if (padapter->bSurpriseRemoved || padapter->bDriverStopped)
return;
LedCfg = rtw_read8(padapter, REG_LEDCFG2);
switch (pLed->LedPin) {
case LED_PIN_LED0:
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */
break;
case LED_PIN_LED1:
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); /* SW control led1 on. */
break;
default:
break;
}
pLed->bLedOn = true;
}
static BOOLEAN
CheckWriteH2C(
IN PADAPTER Adapter,
IN u8 BoxNum
)
{
u8 valHMETFR;
BOOLEAN Result = _FALSE;
valHMETFR = rtw_read8(Adapter, REG_HMETFR);
//DbgPrint("CheckWriteH2C(): Reg[0x%2x] = %x\n",REG_HMETFR, valHMETFR);
if(((valHMETFR>>BoxNum)&BIT0) == 1)
Result = _TRUE;
return Result;
}
static void disable_dm(struct adapter *padapter)
{
u8 v8;
/* 3 1. disable firmware dynamic mechanism */
/* disable Power Training, Rate Adaptive */
v8 = rtw_read8(padapter, REG_BCN_CTRL);
v8 &= ~EN_BCN_FUNCTION;
rtw_write8(padapter, REG_BCN_CTRL, v8);
/* 3 2. disable driver dynamic mechanism */
/* disable Dynamic Initial Gain */
/* disable High Power */
/* disable Power Tracking */
Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, false);
/* enable APK, LCK and IQK but disable power tracking */
Switch_DM_Func(padapter, DYNAMIC_RF_CALIBRATION, true);
}
static VOID
_PageWrite(
IN PADAPTER Adapter,
IN u32 page,
IN PVOID buffer,
IN u32 size
)
{
u8 value8;
u8 u8Page = (u8) (page & 0x07) ;
value8 = rtw_read8(Adapter, REG_MCUFWDL+2);
//printk("%s,REG_%02x(0x%02x),wvalue(0x%02x)\n",__FUNCTION__,(REG_MCUFWDL+2),value8,(value8 & 0xF8) |u8Page);
value8 = (value8 & 0xF8) |u8Page;
rtw_write8(Adapter, REG_MCUFWDL+2,value8);
_BlockWrite(Adapter,buffer,size);
}
void rtl8188e_sreset_linked_status_check(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct sreset_priv *psrtpriv = &pHalData->srestpriv;
u32 rx_dma_status = 0;
u8 fw_status=0;
rx_dma_status = rtw_read32(padapter,REG_RXDMA_STATUS);
if(rx_dma_status!= 0x00){
DBG_8192C("%s REG_RXDMA_STATUS:0x%08x \n",__FUNCTION__,rx_dma_status);
rtw_write32(padapter,REG_RXDMA_STATUS,rx_dma_status);
}
fw_status = rtw_read8(padapter,REG_FMETHR);
if(fw_status != 0x00)
{
if(fw_status == 1)
DBG_8192C("%s REG_FW_STATUS (0x%02x), Read_Efuse_Fail !! \n",__FUNCTION__,fw_status);
else if(fw_status == 2)
DBG_8192C("%s REG_FW_STATUS (0x%02x), Condition_No_Match !! \n",__FUNCTION__,fw_status);
}
#if 0
u32 regc50,regc58,reg824,reg800;
regc50 = rtw_read32(padapter,0xc50);
regc58 = rtw_read32(padapter,0xc58);
reg824 = rtw_read32(padapter,0x824);
reg800 = rtw_read32(padapter,0x800);
if( ((regc50&0xFFFFFF00)!= 0x69543400)||
((regc58&0xFFFFFF00)!= 0x69543400)||
(((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))||
( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000)))
{
DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__,
regc50, regc58, reg824, reg800);
rtw_hal_sreset_reset(padapter);
}
#endif
if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
rtw_hal_sreset_reset(padapter);
return;
}
}
void rtw_hal_check_rxfifo_full(struct adapter *adapter)
{
struct dvobj_priv *psdpriv = adapter->dvobj;
struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
int save_cnt = false;
/* switch counter to RX fifo */
/* printk("8723b or 8192e , MAC_667 set 0xf0\n"); */
rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xf0);
save_cnt = true;
/* todo: other chips */
if (save_cnt) {
/* rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xa0); */
pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow-pdbgpriv->dbg_rx_fifo_last_overflow;
}
}
void rtl8188es_set_output_gpio(_adapter* padapter, u8 index, u8 outputval)
{
if ( index <= 7 ) {
/* config GPIO mode */
rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index) );
/* config GPIO Sel */
/* 0: input */
/* 1: output */
rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
/* set output value */
if ( outputval ) {
rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
} else {
rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
}
} else {
/* 88C Series: */
/* index: 11~8 transform to 3~0 */
/* 8723 Series: */
/* index: 12~8 transform to 4~0 */
index -= 8;
/* config GPIO mode */
rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index) );
/* config GPIO Sel */
/* 0: input */
/* 1: output */
rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
/* set output value */
if ( outputval ) {
rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
} else {
rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
}
}
}
static void rpwmtimeout_workitem_callback(struct work_struct *work)
{
struct adapter *padapter;
struct dvobj_priv *dvobj;
struct pwrctrl_priv *pwrpriv;
pwrpriv = container_of(work, struct pwrctrl_priv, rpwmtimeoutwi);
dvobj = pwrctl_to_dvobj(pwrpriv);
padapter = dvobj->if1;
/* DBG_871X("+%s: rpwm = 0x%02X cpwm = 0x%02X\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm); */
down(&pwrpriv->lock);
if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
DBG_871X("%s: rpwm = 0x%02X cpwm = 0x%02X CPWM done!\n", __func__, pwrpriv->rpwm, pwrpriv->cpwm);
goto exit;
}
up(&pwrpriv->lock);
if (rtw_read8(padapter, 0x100) != 0xEA) {
struct reportpwrstate_parm report;
report.state = PS_STATE_S2;
DBG_871X("\n%s: FW already leave 32K!\n\n", __func__);
cpwm_int_hdl(padapter, &report);
return;
}
down(&pwrpriv->lock);
if ((pwrpriv->rpwm == pwrpriv->cpwm) || (pwrpriv->cpwm >= PS_STATE_S2)) {
DBG_871X("%s: cpwm =%d, nothing to do!\n", __func__, pwrpriv->cpwm);
goto exit;
}
pwrpriv->brpwmtimeout = true;
rtw_set_rpwm(padapter, pwrpriv->rpwm);
pwrpriv->brpwmtimeout = false;
exit:
up(&pwrpriv->lock);
}
VOID
rtl8192d_PHY_PowerDownAnotherPHY(
IN PADAPTER Adapter,
IN BOOLEAN bMac0
)
{
u8 u1bTmp;
#ifdef CONFIG_PCI_HCI
u8 Direct = bMac0==_TRUE?BIT3|BIT2:BIT3;
#endif //CONFIG_PCI_HCI
u8 MAC_REG = bMac0==_TRUE?REG_MAC1:REG_MAC0;
u8 MAC_ON_BIT = bMac0==_TRUE?MAC1_ON:MAC0_ON;
#ifdef CONFIG_USB_HCI
u32 MaskforPhySet = 0;
#endif
//RT_TRACE(COMP_RF, DBG_LOUD, ("====>PHY_PowerDownAnotherPHY\n"));
// check MAC0 enable or not again now, if enabled, not power down radio A.
u1bTmp = rtw_read8(Adapter, MAC_REG);
if (!(u1bTmp&MAC_ON_BIT))
{
//RT_TRACE(COMP_INIT, DBG_LOUD, ("PHY_PowerDownAnotherPHY power down\n"));
// power down RF radio A according to YuNan's advice.
#ifdef CONFIG_PCI_HCI
MpWritePCIDwordDBI8192D(Adapter,
rFPGA0_XA_LSSIParameter,
0x00000000,
Direct);
#elif defined(CONFIG_USB_HCI)
if(bMac0)
MaskforPhySet = MAC0_ACCESS_PHY1;
else
MaskforPhySet = MAC1_ACCESS_PHY0;
rtw_write32(Adapter, rFPGA0_XA_LSSIParameter|MaskforPhySet, 0x00000000);
#endif
}
//RT_TRACE(COMP_RF, DBG_LOUD, ("<====PHY_PowerDownAnotherPHY\n"));
}
u32 read_macreg(struct adapter *padapter, u32 addr, u32 sz)
{
u32 val = 0;
switch (sz) {
case 1:
val = rtw_read8(padapter, addr);
break;
case 2:
val = rtw_read16(padapter, addr);
break;
case 4:
val = rtw_read32(padapter, addr);
break;
default:
val = 0xffffffff;
break;
}
return val;
}
void rtl8723a_InitHalDm(struct rtw_adapter *Adapter)
{
struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
u8 i;
pdmpriv->DM_Type = DM_Type_ByDriver;
pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE;
#ifdef CONFIG_8723AU_BT_COEXIST
pdmpriv->DMFlag |= DYNAMIC_FUNC_BT;
#endif
pdmpriv->InitDMFlag = pdmpriv->DMFlag;
Update_ODM_ComInfo_8723a(Adapter);
ODM23a_DMInit(pDM_Odm);
/* Save REG_INIDATA_RATE_SEL value for TXDESC. */
for (i = 0; i < 32; i++)
pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL+i) & 0x3f;
}
static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 msgbox_num)
{
u8 read_down = _FALSE;
int retry_cnts = 100;
u8 valid;
//DBG_8192C(" _is_fw_read_cmd_down ,reg_1cc(%x),msg_box(%d)...\n",rtw_read8(padapter,REG_HMETFR),msgbox_num);
do{
valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num);
if(0 == valid ){
read_down = _TRUE;
}
else
rtw_msleep_os(1);
}while( (!read_down) && (retry_cnts--));
return read_down;
}
/*
* Description:
* Turn on LED according to LedPin specified.
* */
VOID
SwLedOn_8821AE(
IN PADAPTER Adapter,
IN PLED_PCIE pLed
)
{
u16 LedReg = REG_LEDCFG0;
u8 LedCfg = 0;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct led_priv *ledpriv = &(Adapter->ledpriv);
if (RTW_CANNOT_RUN(Adapter))
return;
switch (pLed->LedPin) {
case LED_PIN_LED0:
if (ledpriv->LedStrategy == SW_LED_MODE10)
LedReg = REG_LEDCFG0;
else
LedReg = REG_LEDCFG2;
break;
case LED_PIN_LED1:
LedReg = REG_LEDCFG1;
break;
case LED_PIN_GPIO0:
default:
break;
}
/* RTW_INFO("In SwLedOn, LedAddr:%X LEDPIN=%d\n", LedReg, pLed->LedPin); */
LedCfg = rtw_read8(Adapter, LedReg);
LedCfg |= BIT5; /* Set 0x4c[21] */
LedCfg &= ~BIT3; /* Clear 0x4c[19] */
LedCfg &= ~(BIT6 | BIT2 | BIT1 | BIT0); /* Clear 0x4c[22] and 0x4c[18:16] */
rtw_write8(Adapter, LedReg, LedCfg); /* SW control led0 on. */
pLed->bLedOn = _TRUE;
}
//
// Description:
// Turn off LED according to LedPin specified.
//
void
SwLedOff(
_adapter *padapter,
PLED_871x pLed
)
{
u8 LedCfg;
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE))
{
goto exit;
}
switch(pLed->LedPin)
{
case LED_PIN_GPIO0:
break;
case LED_PIN_LED0:
rtw_write8(padapter, REG_LEDCFG0, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on.
break;
case LED_PIN_LED1:
rtw_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT5|BIT6); // SW control led1 on.
break;
case LED_PIN_LED2:
LedCfg=rtw_read8(padapter, REG_LEDCFG2);
rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT3|BIT5); // SW control led1 on.
break;
default:
break;
}
exit:
pLed->bLedOn = _FALSE;
}
//
// Initialize GPIO setting registers
//
static void
dm_InitGPIOSetting(
IN PADAPTER Adapter
)
{
PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter);
u8 tmp1byte;
tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG);
tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT);
#ifdef CONFIG_BT_COEXIST
// UMB-B cut bug. We need to support the modification.
if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) &&
pHalData->bt_coexist.BT_Coexist)
{
tmp1byte |= (BIT5);
}
#endif
rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte);
}
static void disable_dm(PADAPTER padapter)
{
u8 v8;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
//3 1. disable firmware dynamic mechanism
// disable Power Training, Rate Adaptive
v8 = rtw_read8(padapter, REG_BCN_CTRL);
v8 &= ~EN_BCN_FUNCTION;
rtw_write8(padapter, REG_BCN_CTRL, v8);
//3 2. disable driver dynamic mechanism
// disable Dynamic Initial Gain
// disable High Power
// disable Power Tracking
Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
// enable APK, LCK and IQK but disable power tracking
pdmpriv->TxPowerTrackControl = _FALSE;
Switch_DM_Func(padapter, DYNAMIC_FUNC_SS, _TRUE);
}
VOID
odm_DynamicTxPowerSavePowerIndex(
IN PVOID pDM_VOID
)
{
PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
u1Byte index;
u4Byte Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
for(index = 0; index< 6; index++)
pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]);
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
struct dm_priv *pdmpriv = &pHalData->dmpriv;
for(index = 0; index< 6; index++)
pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
#endif
#endif
}
int proc_get_read_reg(char *page, char **start,
off_t offset, int count,
int *eof, void *data)
{
struct net_device *dev = data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
int len = 0;
if(proc_get_read_addr==0xeeeeeeee)
{
*eof = 1;
return len;
}
switch(proc_get_read_len)
{
case 1:
len += snprintf(page + len, count - len, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr));
break;
case 2:
len += snprintf(page + len, count - len, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr));
break;
case 4:
len += snprintf(page + len, count - len, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr));
break;
default:
len += snprintf(page + len, count - len, "error read length=%d\n", proc_get_read_len);
break;
}
*eof = 1;
return len;
}
static void shutdown_card(void)
{
u32 addr;
u8 tmp8, cnt=0;
if (NULL == g_test_adapter)
{
DBG_871X("%s: padapter==NULL\n", __FUNCTION__);
return;
}
#ifdef CONFIG_FWLPS_IN_IPS
LeaveAllPowerSaveMode(g_test_adapter);
#endif // CONFIG_FWLPS_IN_IPS
// Leave SDIO HCI Suspend
addr = 0x10250086;
rtw_write8(g_test_adapter, addr, 0);
do {
tmp8 = rtw_read8(g_test_adapter, addr);
cnt++;
DBG_871X(FUNC_ADPT_FMT ": polling SDIO_HSUS_CTRL(0x%x)=0x%x, cnt=%d\n",
FUNC_ADPT_ARG(g_test_adapter), addr, tmp8, cnt);
if (tmp8 & BIT(1))
break;
if (cnt >= 100)
{
DBG_871X(FUNC_ADPT_FMT ": polling 0x%x[1]==1 FAIL!!\n",
FUNC_ADPT_ARG(g_test_adapter), addr);
break;
}
rtw_mdelay_os(10);
} while (1);
// unlock register I/O
rtw_write8(g_test_adapter, 0x1C, 0);
// enable power down function
// 0x04[4] = 1
// 0x05[7] = 1
addr = 0x04;
tmp8 = rtw_read8(g_test_adapter, addr);
tmp8 |= BIT(4);
rtw_write8(g_test_adapter, addr, tmp8);
DBG_871X(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n",
FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));
addr = 0x05;
tmp8 = rtw_read8(g_test_adapter, addr);
tmp8 |= BIT(7);
rtw_write8(g_test_adapter, addr, tmp8);
DBG_871X(FUNC_ADPT_FMT ": read after write 0x%x=0x%x\n",
FUNC_ADPT_ARG(g_test_adapter), addr, rtw_read8(g_test_adapter, addr));
// lock register page0 0x0~0xB read/write
rtw_write8(g_test_adapter, 0x1C, 0x0E);
g_test_adapter->bSurpriseRemoved = _TRUE;
DBG_871X(FUNC_ADPT_FMT ": bSurpriseRemoved=%d\n",
FUNC_ADPT_ARG(g_test_adapter), g_test_adapter->bSurpriseRemoved);
#ifdef CONFIG_CONCURRENT_MODE
if (g_test_adapter->pbuddy_adapter)
{
PADAPTER pbuddy;
pbuddy = g_test_adapter->pbuddy_adapter;
pbuddy->bSurpriseRemoved = _TRUE;
DBG_871X(FUNC_ADPT_FMT ": buddy(" ADPT_FMT ") bSurpriseRemoved=%d\n",
FUNC_ADPT_ARG(g_test_adapter), ADPT_ARG(pbuddy), pbuddy->bSurpriseRemoved);
}
#endif // CONFIG_CONCURRENT_MODE
}
void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode)
{
struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv;
#ifdef CONFIG_P2P
struct wifidirect_info *pwdinfo = &( padapter->wdinfo );
#endif //CONFIG_P2P
#ifdef CONFIG_TDLS
struct sta_priv *pstapriv = &padapter->stapriv;
_irqL irqL;
int i, j;
_list *plist, *phead;
struct sta_info *ptdls_sta;
#endif //CONFIG_TDLS
_func_enter_;
RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_notice_,
("%s: PowerMode=%d Smart_PS=%d\n",
__FUNCTION__, ps_mode, smart_ps));
if(ps_mode > PM_Card_Disable) {
RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("ps_mode:%d error\n", ps_mode));
return;
}
if (pwrpriv->pwr_mode == ps_mode)
{
if (PS_MODE_ACTIVE == ps_mode) return;
if ((pwrpriv->smart_ps == smart_ps) &&
(pwrpriv->bcn_ant_mode == bcn_ant_mode))
{
return;
}
}
#ifdef CONFIG_LPS_LCLK
_enter_pwrlock(&pwrpriv->lock);
#endif
//if(pwrpriv->pwr_mode == PS_MODE_ACTIVE)
if(ps_mode == PS_MODE_ACTIVE)
{
#ifdef CONFIG_P2P_PS
if(pwdinfo->opp_ps == 0)
#endif //CONFIG_P2P_PS
{
DBG_871X("rtw_set_ps_mode: Leave 802.11 power save\n");
#ifdef CONFIG_TDLS
_enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
for(i=0; i< NUM_STA; i++)
{
phead = &(pstapriv->sta_hash[i]);
plist = get_next(phead);
while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
{
ptdls_sta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
if( ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE )
issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 0);
plist = get_next(plist);
}
}
_exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
#endif //CONFIG_TDLS
pwrpriv->pwr_mode = ps_mode;
rtw_set_rpwm(padapter, PS_STATE_S4);
#ifdef CONFIG_WOWLAN
if (padapter->pwrctrlpriv.wowlan_mode == _TRUE)
{
u32 start_time, delay_ms;
u8 val8;
delay_ms = 20;
start_time = rtw_get_current_time();
do {
val8 = rtw_read8(padapter, 0x90);
if (!(val8 & BIT(0))) break;
if (rtw_get_passing_time_ms(start_time) > delay_ms)
{
DBG_871X("%s: Wait for FW 32K leave more than %u ms!!!\n", __FUNCTION__, delay_ms);
break;
}
rtw_usleep_os(100);
} while (1);
pwrpriv->cpwm = PS_STATE_S4;
}
#endif
rtw_hal_set_hwreg(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode));
pwrpriv->bFwCurrentInPSMode = _FALSE;
}
}
static u8 rtl8723bs_query_tx_freepage(_adapter *padapter, struct xmit_buf *pxmitbuf)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
u8 TxRequiredPageNum = 0;
u8 DedicatedPgNum = 0;
u8 RequiredPublicFreePgNum = 0;
u8 PageIdx = 0;
u8 bResult = _TRUE;
u32 n, deviceId;
TxRequiredPageNum = pxmitbuf->pg_num;
deviceId = ffaddr2deviceId(pdvobjpriv, pxmitbuf->ff_hwaddr);
// translate fifo addr to queue index
switch (deviceId) {
case WLAN_TX_HIQ_DEVICE_ID:
PageIdx = HI_QUEUE_IDX;
break;
case WLAN_TX_MIQ_DEVICE_ID:
PageIdx = MID_QUEUE_IDX;
break;
case WLAN_TX_LOQ_DEVICE_ID:
PageIdx = LOW_QUEUE_IDX;
break;
}
// check if hardware tx fifo page is enough
n = 0;
do {
if ((padapter->bSurpriseRemoved == _TRUE) || (padapter->bDriverStopped == _TRUE)) {
RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
("%s: bSurpriseRemoved(update TX FIFO page)\n", __FUNCTION__));
break;
}
// The number of page which public page is included is available .
if ((pHalData->SdioTxFIFOFreePage[PageIdx]+pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX]) > (TxRequiredPageNum+1)) {
DedicatedPgNum = pHalData->SdioTxFIFOFreePage[PageIdx];
if (TxRequiredPageNum <= DedicatedPgNum) {
pHalData->SdioTxFIFOFreePage[PageIdx] -= TxRequiredPageNum;
break;
} else {
pHalData->SdioTxFIFOFreePage[PageIdx] = 0;
RequiredPublicFreePgNum = TxRequiredPageNum - DedicatedPgNum;
pHalData->SdioTxFIFOFreePage[PUBLIC_QUEUE_IDX] -= RequiredPublicFreePgNum;
break;
}
}
n++;
#if 0
if (n >= 5000)
{
u8 reg_value_1 = 0;
u8 reg_value_2 = 0;
u8 reg_value_3 = 0;
//try to recover the transmission
reg_value_1 = rtw_read8(padapter, REG_SYS_FUNC_EN);
reg_value_2 = rtw_read8(padapter, REG_CR);
reg_value_3 = rtw_read8(padapter, REG_TXPAUSE);
DBG_871X("Before recovery: REG_SYS_FUNC_EN = 0x%X, REG_CR = 0x%X, REG_TXPAUSE = 0x%X\n", reg_value_1, reg_value_2, reg_value_3);
rtw_write8(padapter, REG_SYS_FUNC_EN, reg_value_1 | 0x01);
rtw_write8(padapter, REG_CR, reg_value_2 | 0xC0);
rtw_write8(padapter, REG_TXPAUSE, 0);
DBG_871X("After recovery: REG_SYS_FUNC_EN = 0x%X, REG_CR = 0x%X, REG_TXPAUSE = 0x%X\n",
rtw_read8(padapter, REG_SYS_FUNC_EN), rtw_read8(padapter, REG_CR), rtw_read8(padapter, REG_TXPAUSE));
}
#endif
if ((n % 0x7F) == 0) {//or 80
//DBG_871X("%s: FIFO starvation!(%d) len=%d agg=%d page=(R)%d(A)%d\n",
// __func__, n, pxmitbuf->len, pxmitbuf->agg_num, pframe->pg_num, freePage[PageIdx] + freePage[PUBLIC_QUEUE_IDX]);
rtw_msleep_os(1);
}
// Total number of page is NOT available, so update current FIFO status
HalQueryTxBufferStatus8723BSdio(padapter);
} while (1);
return bResult;
}
static void _restore_network_status(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
unsigned short caps;
u8 join_type;
#if 1
//=======================================================
// reset related register of Beacon control
//set MSR to nolink
Set_NETYPE0_MSR(padapter, _HW_STATE_NOLINK_);
// reject all data frame
rtw_write16(padapter, REG_RXFLTMAP2,0x00);
//reset TSF
rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
//disable update TSF
if(IS_NORMAL_CHIP(pHalData->VersionID))
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4));
else
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4)|BIT(5));
//=======================================================
rtw_joinbss_reset(padapter);
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
//pmlmeinfo->assoc_AP_vendor = maxAP;
if (padapter->registrypriv.wifi_spec) {
// for WiFi test, follow WMM test plan spec
rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002F431C);
rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005E541C);
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x0000A525);
rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A549);
// for WiFi test, mixed mode with intel STA under bg mode throughput issue
if (padapter->mlmepriv.htpriv.ht_option == 0)
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x00004320);
} else {
rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002F3217);
rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005E4317);
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x00105320);
rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A444);
}
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
#endif
padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
join_type = 0;
padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
Set_NETYPE0_MSR(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback(padapter, 1);
//restore Sequence No.
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
}
u8 SetHalDefVar(
struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
)
{
struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &(hal_data->odmpriv);
u8 bResult = _SUCCESS;
switch (variable) {
case HW_DEF_FA_CNT_DUMP:
/* ODM_COMP_COMMON */
if (*((u8 *)value))
odm->DebugComponents |= (ODM_COMP_DIG | ODM_COMP_FA_CNT);
else
odm->DebugComponents &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT);
break;
case HAL_DEF_DBG_RX_INFO_DUMP:
DBG_871X("============ Rx Info dump ===================\n");
DBG_871X("bLinked = %d, RSSI_Min = %d(%%)\n",
odm->bLinked, odm->RSSI_Min);
if (odm->bLinked) {
DBG_871X("RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
#ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
rtw_dump_raw_rssi_info(adapter);
#endif
}
break;
case HW_DEF_ODM_DBG_FLAG:
ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_COMP, *((u64 *)value));
break;
case HW_DEF_ODM_DBG_LEVEL:
ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_LEVEL, *((u32 *)value));
break;
case HAL_DEF_DBG_DM_FUNC:
{
u8 dm_func = *((u8 *)value);
struct dm_priv *dm = &hal_data->dmpriv;
if (dm_func == 0) { /* disable all dynamic func */
odm->SupportAbility = DYNAMIC_FUNC_DISABLE;
DBG_8192C("==> Disable all dynamic function...\n");
} else if (dm_func == 1) {/* disable DIG */
odm->SupportAbility &= (~DYNAMIC_BB_DIG);
DBG_8192C("==> Disable DIG...\n");
} else if (dm_func == 2) {/* disable High power */
odm->SupportAbility &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
} else if (dm_func == 3) {/* disable tx power tracking */
odm->SupportAbility &= (~DYNAMIC_RF_CALIBRATION);
DBG_8192C("==> Disable tx power tracking...\n");
} else if (dm_func == 4) {/* disable BT coexistence */
dm->DMFlag &= (~DYNAMIC_FUNC_BT);
} else if (dm_func == 5) {/* disable antenna diversity */
odm->SupportAbility &= (~DYNAMIC_BB_ANT_DIV);
} else if (dm_func == 6) {/* turn on all dynamic func */
if (!(odm->SupportAbility & DYNAMIC_BB_DIG)) {
DIG_T *pDigTable = &odm->DM_DigTable;
pDigTable->CurIGValue = rtw_read8(adapter, 0xc50);
}
dm->DMFlag |= DYNAMIC_FUNC_BT;
odm->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
DBG_8192C("==> Turn on all dynamic function...\n");
}
}
break;
case HAL_DEF_DBG_DUMP_RXPKT:
hal_data->bDumpRxPkt = *((u8 *)value);
break;
case HAL_DEF_DBG_DUMP_TXPKT:
hal_data->bDumpTxPkt = *((u8 *)value);
break;
case HAL_DEF_ANT_DETECT:
hal_data->AntDetection = *((u8 *)value);
break;
default:
DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
bResult = _FAIL;
break;
}
return bResult;
}
void SetHwReg(struct adapter *adapter, u8 variable, u8 *val)
{
struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &(hal_data->odmpriv);
switch (variable) {
case HW_VAR_PORT_SWITCH:
hw_var_port_switch(adapter);
break;
case HW_VAR_INIT_RTS_RATE:
rtw_warn_on(1);
break;
case HW_VAR_SEC_CFG:
{
u16 reg_scr;
reg_scr = rtw_read16(adapter, REG_SECCFG);
rtw_write16(adapter, REG_SECCFG, reg_scr|SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable);
}
break;
case HW_VAR_SEC_DK_CFG:
{
struct security_priv *sec = &adapter->securitypriv;
u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
if (val) { /* Enable default key related setting */
reg_scr |= SCR_TXBCUSEDK;
if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
reg_scr |= (SCR_RxUseDK|SCR_TxUseDK);
} else /* Disable default key related setting */
reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK);
rtw_write8(adapter, REG_SECCFG, reg_scr);
}
break;
case HW_VAR_DM_FLAG:
odm->SupportAbility = *((u32 *)val);
break;
case HW_VAR_DM_FUNC_OP:
if (*((u8 *)val) == true) {
/* save dm flag */
odm->BK_SupportAbility = odm->SupportAbility;
} else {
/* restore dm flag */
odm->SupportAbility = odm->BK_SupportAbility;
}
break;
case HW_VAR_DM_FUNC_SET:
if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
struct dm_priv *dm = &hal_data->dmpriv;
dm->DMFlag = dm->InitDMFlag;
odm->SupportAbility = dm->InitODMFlag;
} else {
odm->SupportAbility |= *((u32 *)val);
}
break;
case HW_VAR_DM_FUNC_CLR:
/*
* input is already a mask to clear function
* don't invert it again! George, Lucas@20130513
*/
odm->SupportAbility &= *((u32 *)val);
break;
case HW_VAR_AMPDU_MIN_SPACE:
/* TODO - Is something needed here? */
break;
case HW_VAR_WIRELESS_MODE:
/* TODO - Is something needed here? */
break;
default:
DBG_871X_LEVEL(
_drv_always_,
FUNC_ADPT_FMT" variable(%d) not defined!\n",
FUNC_ADPT_ARG(adapter),
variable
);
break;
}
}
/*****************************************
* H2C Msg format :
*| 31 - 8 |7 | 6 - 0 |
*| h2c_msg |Ext_bit |CMD_ID |
*
******************************************/
static void _FillH2CCmd92D(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
u8 BoxNum;
u16 BOXReg=0, BOXExtReg=0;
u8 BoxContent[4], BoxExtContent[2];
u8 BufIndex=0;
u8 U1btmp; //Read 0x1bf
u8 bWriteSucess = _FALSE;
u8 IsFwRead = _FALSE;
u8 WaitH2cLimmit = 100;
u8 WaitWriteH2cLimmit = 100;
u8 idx=0;
_func_enter_;
padapter = GET_PRIMARY_ADAPTER(padapter);
pHalData = GET_HAL_DATA(padapter);
_enter_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
//DBG_8192C("FillH2CCmd : ElementID=%d \n",ElementID);
while(!bWriteSucess)
{
WaitWriteH2cLimmit--;
if(WaitWriteH2cLimmit == 0)
{
DBG_8192C("FillH2CCmd92C():Write H2C fail because no trigger for FW INT!!!!!!!!\n");
break;
}
// 2. Find the last BOX number which has been writen.
BoxNum = pHalData->LastHMEBoxNum;
switch(BoxNum)
{
case 0:
BOXReg = REG_HMEBOX_0;
BOXExtReg = REG_HMEBOX_EXT_0;
break;
case 1:
BOXReg = REG_HMEBOX_1;
BOXExtReg = REG_HMEBOX_EXT_1;
break;
case 2:
BOXReg = REG_HMEBOX_2;
BOXExtReg = REG_HMEBOX_EXT_2;
break;
case 3:
BOXReg = REG_HMEBOX_3;
BOXExtReg = REG_HMEBOX_EXT_3;
break;
default:
break;
}
// 3. Check if the box content is empty.
IsFwRead = CheckFwReadLastH2C(padapter, BoxNum);
while(!IsFwRead)
{
//wait until Fw read
WaitH2cLimmit--;
if(WaitH2cLimmit == 0)
{
DBG_8192C("FillH2CCmd92C(): Wating too long for FW read clear HMEBox(%d)!!!\n", BoxNum);
break;
}
rtw_udelay_os(10); //us
IsFwRead = CheckFwReadLastH2C(padapter, BoxNum);
U1btmp = rtw_read8(padapter, 0x1BF);
//DBG_8192C("FillH2CCmd92C(): Wating for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", BoxNum, U1btmp);
}
// If Fw has not read the last H2C cmd, break and give up this H2C.
if(!IsFwRead)
{
DBG_8192C("FillH2CCmd92C(): Write H2C register BOX[%d] fail!!!!! Fw do not read. \n", BoxNum);
break;
}
// 4. Fill the H2C cmd into box
_rtw_memset(BoxContent, 0, sizeof(BoxContent));
_rtw_memset(BoxExtContent, 0, sizeof(BoxExtContent));
BoxContent[0] = ElementID; // Fill element ID
//DBG_8192C("FillH2CCmd92C():Write ElementID BOXReg(%4x) = %2x \n", BOXReg, ElementID);
switch(CmdLen)
{
case 1:
{
BoxContent[0] &= ~(BIT7);
_rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex, 1);
//PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent));
//For Endian Free.
for(idx= 0; idx < 4; idx++)
{
rtw_write8(padapter, BOXReg+idx, BoxContent[idx]);
}
break;
}
case 2:
{
BoxContent[0] &= ~(BIT7);
_rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex, 2);
//PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent));
for(idx=0; idx < 4; idx++)
{
rtw_write8(padapter, BOXReg+idx, BoxContent[idx]);
}
break;
}
case 3:
{
BoxContent[0] &= ~(BIT7);
_rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex, 3);
//PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent));
for(idx = 0; idx < 4 ; idx++)
{
rtw_write8(padapter, BOXReg+idx, BoxContent[idx]);
}
break;
}
case 4:
{
BoxContent[0] |= (BIT7);
_rtw_memcpy((u8 *)(BoxExtContent), pCmdBuffer+BufIndex, 2);
_rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex+2, 2);
//PlatformEFIOWrite2Byte(Adapter, BOXExtReg, *((pu2Byte)BoxExtContent));
//PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent));
for(idx = 0 ; idx < 2 ; idx ++)
{
rtw_write8(padapter, BOXExtReg+idx, BoxExtContent[idx]);
}
for(idx = 0 ; idx < 4 ; idx ++)
{
rtw_write8(padapter, BOXReg+idx, BoxContent[idx]);
}
break;
}
case 5:
{
BoxContent[0] |= (BIT7);
_rtw_memcpy((u8 *)(BoxExtContent), pCmdBuffer+BufIndex, 2);
_rtw_memcpy((u8 *)(BoxContent)+1, pCmdBuffer+BufIndex+2, 3);
//PlatformEFIOWrite2Byte(Adapter, BOXExtReg, *((pu2Byte)BoxExtContent));
//PlatformEFIOWrite4Byte(Adapter, BOXReg, *((pu4Byte)BoxContent));
for(idx = 0 ; idx < 2 ; idx ++)
{
rtw_write8(padapter, BOXExtReg+idx, BoxExtContent[idx]);
}
for(idx = 0 ; idx < 4 ; idx ++)
{
rtw_write8(padapter, BOXReg+idx, BoxContent[idx]);
}
break;
}
default:
break;
}
//DBG_8192C("FillH2CCmd(): BoxExtContent=0x%04x\n", *(u16*)BoxExtContent);
//DBG_8192C("FillH2CCmd(): BoxContent=0x%08x\n", *(u32*)BoxContent);
// 5. Normal chip does not need to check if the H2C cmd has be written successfully.
// 92D test chip does not need to check,
bWriteSucess = _TRUE;
// Record the next BoxNum
pHalData->LastHMEBoxNum = BoxNum+1;
if(pHalData->LastHMEBoxNum == 4) // loop to 0
pHalData->LastHMEBoxNum = 0;
//DBG_8192C("FillH2CCmd92C():pHalData->LastHMEBoxNum = %d\n", pHalData->LastHMEBoxNum);
}
_exit_critical_mutex(&(adapter_to_dvobj(padapter)->h2c_fwcmd_mutex), NULL);
_func_exit_;
}