/* Check if all uses in DEF_INSN can be used in TARGET_INSN. This
would require full computation of available expressions;
we check only restricted conditions, see use_killed_between. */
static bool
all_uses_available_at (rtx_insn *def_insn, rtx_insn *target_insn)
{
df_ref use;
struct df_insn_info *insn_info = DF_INSN_INFO_GET (def_insn);
rtx def_set = single_set (def_insn);
rtx_insn *next;
gcc_assert (def_set);
/* If target_insn comes right after def_insn, which is very common
for addresses, we can use a quicker test. Ignore debug insns
other than target insns for this. */
next = NEXT_INSN (def_insn);
while (next && next != target_insn && DEBUG_INSN_P (next))
next = NEXT_INSN (next);
if (next == target_insn && REG_P (SET_DEST (def_set)))
{
rtx def_reg = SET_DEST (def_set);
/* If the insn uses the reg that it defines, the substitution is
invalid. */
FOR_EACH_INSN_INFO_USE (use, insn_info)
if (rtx_equal_p (DF_REF_REG (use), def_reg))
return false;
FOR_EACH_INSN_INFO_EQ_USE (use, insn_info)
if (rtx_equal_p (DF_REF_REG (use), def_reg))
return false;
}
static bool
can_eliminate_compare (rtx compare, rtx eh_note, struct comparison *cmp)
{
/* Take care that it's in the same EH region. */
if (cfun->can_throw_non_call_exceptions
&& !rtx_equal_p (eh_note, cmp->eh_note))
return false;
/* Make sure the compare is redundant with the previous. */
if (!rtx_equal_p (XEXP (compare, 0), cmp->in_a)
|| !rtx_equal_p (XEXP (compare, 1), cmp->in_b))
return false;
/* New mode must be compatible with the previous compare mode. */
enum machine_mode new_mode
= targetm.cc_modes_compatible (GET_MODE (compare), cmp->orig_mode);
if (new_mode == VOIDmode)
return false;
if (cmp->orig_mode != new_mode)
{
/* Generate new comparison for substitution. */
rtx flags = gen_rtx_REG (new_mode, targetm.flags_regnum);
rtx x = gen_rtx_COMPARE (new_mode, cmp->in_a, cmp->in_b);
x = gen_rtx_SET (flags, x);
if (!validate_change (cmp->insn, &PATTERN (cmp->insn), x, false))
return false;
cmp->orig_mode = new_mode;
}
return true;
}
rtx
compare_and_jump_seq (rtx op0, rtx op1, enum rtx_code comp, rtx label, int prob,
rtx cinsn)
{
rtx seq, jump, cond;
enum machine_mode mode;
mode = GET_MODE (op0);
if (mode == VOIDmode)
mode = GET_MODE (op1);
start_sequence ();
if (GET_MODE_CLASS (mode) == MODE_CC)
{
/* A hack -- there seems to be no easy generic way how to make a
conditional jump from a ccmode comparison. */
gcc_assert (cinsn);
cond = XEXP (SET_SRC (pc_set (cinsn)), 0);
gcc_assert (GET_CODE (cond) == comp);
gcc_assert (rtx_equal_p (op0, XEXP (cond, 0)));
gcc_assert (rtx_equal_p (op1, XEXP (cond, 1)));
emit_jump_insn (copy_insn (PATTERN (cinsn)));
jump = get_last_insn ();
gcc_assert (JUMP_P (jump));
JUMP_LABEL (jump) = JUMP_LABEL (cinsn);
LABEL_NUSES (JUMP_LABEL (jump))++;
redirect_jump (jump, label, 0);
}
else
{
gcc_assert (!cinsn);
op0 = force_operand (op0, NULL_RTX);
op1 = force_operand (op1, NULL_RTX);
do_compare_rtx_and_jump (op0, op1, comp, 0,
mode, NULL_RTX, NULL_RTX, label, -1);
jump = get_last_insn ();
gcc_assert (JUMP_P (jump));
JUMP_LABEL (jump) = label;
LABEL_NUSES (label)++;
}
add_reg_note (jump, REG_BR_PROB, GEN_INT (prob));
seq = get_insns ();
end_sequence ();
return seq;
}
static bool
should_replace_address (rtx old_rtx, rtx new_rtx, machine_mode mode,
addr_space_t as, bool speed)
{
int gain;
if (rtx_equal_p (old_rtx, new_rtx)
|| !memory_address_addr_space_p (mode, new_rtx, as))
return false;
/* Copy propagation is always ok. */
if (REG_P (old_rtx) && REG_P (new_rtx))
return true;
/* Prefer the new address if it is less expensive. */
gain = (address_cost (old_rtx, mode, as, speed)
- address_cost (new_rtx, mode, as, speed));
/* If the addresses have equivalent cost, prefer the new address
if it has the highest `set_src_cost'. That has the potential of
eliminating the most insns without additional costs, and it
is the same that cse.c used to do. */
if (gain == 0)
gain = (set_src_cost (new_rtx, VOIDmode, speed)
- set_src_cost (old_rtx, VOIDmode, speed));
return (gain > 0);
}
static void
maybe_propagate_label_ref (rtx jump_insn, rtx prev_nonjump_insn)
{
rtx label_note, pc, pc_src;
pc = pc_set (jump_insn);
pc_src = pc != NULL ? SET_SRC (pc) : NULL;
label_note = find_reg_note (prev_nonjump_insn, REG_LABEL_OPERAND, NULL);
/* If the previous non-jump insn sets something to a label,
something that this jump insn uses, make that label the primary
target of this insn if we don't yet have any. That previous
insn must be a single_set and not refer to more than one label.
The jump insn must not refer to other labels as jump targets
and must be a plain (set (pc) ...), maybe in a parallel, and
may refer to the item being set only directly or as one of the
arms in an IF_THEN_ELSE. */
if (label_note != NULL && pc_src != NULL)
{
rtx label_set = single_set (prev_nonjump_insn);
rtx label_dest = label_set != NULL ? SET_DEST (label_set) : NULL;
if (label_set != NULL
/* The source must be the direct LABEL_REF, not a
PLUS, UNSPEC, IF_THEN_ELSE etc. */
&& GET_CODE (SET_SRC (label_set)) == LABEL_REF
&& (rtx_equal_p (label_dest, pc_src)
|| (GET_CODE (pc_src) == IF_THEN_ELSE
&& (rtx_equal_p (label_dest, XEXP (pc_src, 1))
|| rtx_equal_p (label_dest, XEXP (pc_src, 2))))))
{
/* The CODE_LABEL referred to in the note must be the
CODE_LABEL in the LABEL_REF of the "set". We can
conveniently use it for the marker function, which
requires a LABEL_REF wrapping. */
gcc_assert (XEXP (label_note, 0) == XEXP (SET_SRC (label_set), 0));
mark_jump_label_1 (label_set, jump_insn, false, true);
gcc_assert (JUMP_LABEL (jump_insn) == XEXP (label_note, 0));
}
}
}
static void
sdbout_reg_parms (tree parms)
{
for (; parms; parms = TREE_CHAIN (parms))
if (DECL_NAME (parms))
{
const char *name = IDENTIFIER_POINTER (DECL_NAME (parms));
/* Report parms that live in registers during the function
but were passed in memory. */
if (REG_P (DECL_RTL (parms))
&& REGNO (DECL_RTL (parms)) < FIRST_PSEUDO_REGISTER
&& PARM_PASSED_IN_MEMORY (parms))
{
if (name == 0 || *name == 0)
name = gen_fake_label ();
PUT_SDB_DEF (name);
PUT_SDB_INT_VAL (DBX_REGISTER_NUMBER (REGNO (DECL_RTL (parms))));
PUT_SDB_SCL (C_REG);
PUT_SDB_TYPE (plain_type (TREE_TYPE (parms)));
PUT_SDB_ENDEF;
}
/* Report parms that live in memory but not where they were passed. */
else if (MEM_P (DECL_RTL (parms))
&& GET_CODE (XEXP (DECL_RTL (parms), 0)) == PLUS
&& CONST_INT_P (XEXP (XEXP (DECL_RTL (parms), 0), 1))
&& PARM_PASSED_IN_MEMORY (parms)
&& ! rtx_equal_p (DECL_RTL (parms), DECL_INCOMING_RTL (parms)))
{
#if 0 /* ??? It is not clear yet what should replace this. */
int offset = DECL_OFFSET (parms) / BITS_PER_UNIT;
/* A parm declared char is really passed as an int,
so it occupies the least significant bytes.
On a big-endian machine those are not the low-numbered ones. */
if (BYTES_BIG_ENDIAN
&& offset != -1
&& TREE_TYPE (parms) != DECL_ARG_TYPE (parms))
offset += (GET_MODE_SIZE (TYPE_MODE (DECL_ARG_TYPE (parms)))
- GET_MODE_SIZE (GET_MODE (DECL_RTL (parms))));
if (INTVAL (XEXP (XEXP (DECL_RTL (parms), 0), 1)) != offset) {...}
#endif
{
if (name == 0 || *name == 0)
name = gen_fake_label ();
PUT_SDB_DEF (name);
PUT_SDB_INT_VAL (DEBUGGER_AUTO_OFFSET
(XEXP (DECL_RTL (parms), 0)));
PUT_SDB_SCL (C_AUTO);
PUT_SDB_TYPE (plain_type (TREE_TYPE (parms)));
PUT_SDB_ENDEF;
}
}
}
static void
kill_set_value (rtx x, const_rtx set, void *data)
{
struct kill_set_value_data *ksvd = (struct kill_set_value_data *) data;
if (rtx_equal_p (x, ksvd->ignore_set_reg))
return;
if (GET_CODE (set) != CLOBBER)
{
kill_value (x, ksvd->vd);
if (REG_P (x))
set_value_regno (REGNO (x), GET_MODE (x), ksvd->vd);
}
}
rtx
get_hard_reg_initial_reg (rtx reg)
{
struct initial_value_struct *ivs = crtl->hard_reg_initial_vals;
int i;
if (ivs == 0)
return NULL_RTX;
for (i = 0; i < ivs->num_entries; i++)
if (rtx_equal_p (ivs->entries[i].pseudo, reg))
return ivs->entries[i].hard_reg;
return NULL_RTX;
}
static bool
interesting_second_load (rtx set, struct load ***load, rtx insn)
{
rtx mem, reg;
if (!set)
return false;
mem = SET_SRC (set);
reg = SET_DEST (set);
if (!MEM_P (mem) || MEM_VOLATILE_P (mem) || !REG_P (reg))
return false;
*load = (struct load **)
htab_find_slot_with_hash (htab_load, mem, load_rtx_hash (mem),
NO_INSERT);
if (!*load)
return false;
/* Don't work on cases that never happen: if there is no kill, we
would have inherited the reload; if the store and load regs are
the same we would need to find an available register. If the
kill insn was already replaced by a move this information is
stale, disregard it. */
if (rtx_equal_p (reg, (**load)->reg)
|| !(**load)->reg_kill
|| INSN_DELETED_P ((**load)->reg_kill)
|| reg_used_between_p (reg, PREV_INSN ((**load)->reg_kill),
NEXT_INSN (insn))
|| reg_set_between_p (reg, PREV_INSN ((**load)->reg_kill), insn))
{
if (dump_file)
{
fputs ("\nCan't insert the move before the kill for this load:\n ",
dump_file);
print_inline_rtx (dump_file, insn, 2);
fputs ("\n\n", dump_file);
}
return false;
}
return true;
}
static void
matching_length (rtx insn1, rtx insn2, int* len, int* cost)
{
rtx x1;
rtx x2;
x1 = insn1;
x2 = insn2;
*len = 0;
*cost = 0;
while (x1 && x2 && (x1 != insn2) && (x2 != insn1)
&& rtx_equal_p (PATTERN (x1), PATTERN (x2)))
{
(*len)++;
(*cost) += compute_rtx_cost (x1);
x1 = prev_insn_in_block (x1);
x2 = prev_insn_in_block (x2);
}
}
void
ix86_expand_vector_init (unsigned char mmx_ok, rtx target, rtx vals)
{
enum machine_mode mode = ((enum machine_mode) (target)->mode);
enum machine_mode inner_mode = ((enum machine_mode) mode_inner[mode]);
int n_elts = mode_nunits[mode];
int n_var = 0, one_var = -1;
unsigned char all_same = 1, all_const_zero = 1;
int i;
rtx x;
for (i = 0; i < n_elts; ++i)
{
x = (((((vals)->u.fld[0]).rt_rtvec))->elem[i]);
if (!((((enum rtx_code) (x)->code) == CONST_INT)
|| ((enum rtx_code) (x)->code) == CONST_DOUBLE
|| ((enum rtx_code) (x)->code) == CONST_FIXED))
n_var++, one_var = i;
else
all_const_zero = 0;
if (i > 0 && !rtx_equal_p (x, (((((vals)->u.fld[0]).rt_rtvec))->elem[0])))
all_same = 0;
}
if (n_var == 0)
{
return;
}
if (all_same)
return;
if (n_var == 1)
{
if (all_const_zero)
return;
}
ix86_expand_vector_init_general (mmx_ok, mode, target, vals);
}
bool
rtvec_all_equal_p (const_rtvec vec)
{
const_rtx first = RTVEC_ELT (vec, 0);
/* Optimize the important special case of a vector of constants.
The main use of this function is to detect whether every element
of CONST_VECTOR is the same. */
switch (GET_CODE (first))
{
CASE_CONST_UNIQUE:
for (int i = 1, n = GET_NUM_ELEM (vec); i < n; ++i)
if (first != RTVEC_ELT (vec, i))
return false;
return true;
default:
for (int i = 1, n = GET_NUM_ELEM (vec); i < n; ++i)
if (!rtx_equal_p (first, RTVEC_ELT (vec, i)))
return false;
return true;
}
}
/* Find the group that the target register definition DEF belongs
to in the list starting with *ALL_BTR_DEF_GROUPS. If no such
group exists, create one. Add def to the group. */
static void
find_btr_def_group (btr_def_group *all_btr_def_groups, btr_def def)
{
if (insn_sets_btr_p (def->insn, 1, NULL))
{
btr_def_group this_group;
rtx def_src = SET_SRC (single_set (def->insn));
/* ?? This linear search is an efficiency concern, particularly
as the search will almost always fail to find a match. */
for (this_group = *all_btr_def_groups;
this_group != NULL;
this_group = this_group->next)
if (rtx_equal_p (def_src, this_group->src))
break;
if (!this_group)
{
this_group = XOBNEW (&migrate_btrl_obstack, struct btr_def_group_s);
this_group->src = def_src;
this_group->members = NULL;
this_group->next = *all_btr_def_groups;
*all_btr_def_groups = this_group;
}
/* Do transform 1) on INSN if applicable. */
static bool
divmod_fixed_value_transform (rtx insn)
{
rtx set, set_src, set_dest, op1, op2, value, histogram;
enum rtx_code code;
enum machine_mode mode;
gcov_type val, count, all;
edge e;
int prob;
set = single_set (insn);
if (!set)
return false;
set_src = SET_SRC (set);
set_dest = SET_DEST (set);
code = GET_CODE (set_src);
mode = GET_MODE (set_dest);
if (code != DIV && code != MOD && code != UDIV && code != UMOD)
return false;
op1 = XEXP (set_src, false);
op2 = XEXP (set_src, 1);
for (histogram = REG_NOTES (insn);
histogram;
histogram = XEXP (histogram, 1))
if (REG_NOTE_KIND (histogram) == REG_VALUE_PROFILE
&& XEXP (XEXP (histogram, 0), 0) == GEN_INT (HIST_TYPE_SINGLE_VALUE))
break;
if (!histogram)
return false;
histogram = XEXP (XEXP (histogram, 0), 1);
value = XEXP (histogram, 0);
histogram = XEXP (histogram, 1);
val = INTVAL (XEXP (histogram, 0));
histogram = XEXP (histogram, 1);
count = INTVAL (XEXP (histogram, 0));
histogram = XEXP (histogram, 1);
all = INTVAL (XEXP (histogram, 0));
/* We require that count be at least half of all; this means
that for the transformation to fire the value must be constant
at least 50% of time (and 75% gives the guarantee of usage). */
if (!rtx_equal_p (op2, value) || 2 * count < all)
return false;
if (dump_file)
fprintf (dump_file, "Div/mod by constant transformation on insn %d\n",
INSN_UID (insn));
/* Compute probability of taking the optimal path. */
prob = (count * REG_BR_PROB_BASE + all / 2) / all;
e = split_block (BLOCK_FOR_INSN (insn), PREV_INSN (insn));
delete_insn (insn);
insert_insn_on_edge (
gen_divmod_fixed_value (mode, code, set_dest,
op1, op2, val, prob), e);
return true;
}
/* Do transform 2) on INSN if applicable. */
static bool
mod_pow2_value_transform (rtx insn)
{
rtx set, set_src, set_dest, op1, op2, value, histogram;
enum rtx_code code;
enum machine_mode mode;
gcov_type wrong_values, count;
edge e;
int i, all, prob;
set = single_set (insn);
if (!set)
return false;
set_src = SET_SRC (set);
set_dest = SET_DEST (set);
code = GET_CODE (set_src);
mode = GET_MODE (set_dest);
if (code != UMOD)
return false;
op1 = XEXP (set_src, 0);
op2 = XEXP (set_src, 1);
for (histogram = REG_NOTES (insn);
histogram;
histogram = XEXP (histogram, 1))
if (REG_NOTE_KIND (histogram) == REG_VALUE_PROFILE
&& XEXP (XEXP (histogram, 0), 0) == GEN_INT (HIST_TYPE_POW2))
break;
if (!histogram)
return false;
histogram = XEXP (XEXP (histogram, 0), 1);
value = XEXP (histogram, 0);
histogram = XEXP (histogram, 1);
wrong_values =INTVAL (XEXP (histogram, 0));
histogram = XEXP (histogram, 1);
count = 0;
for (i = 0; i < GET_MODE_BITSIZE (mode); i++)
{
count += INTVAL (XEXP (histogram, 0));
histogram = XEXP (histogram, 1);
}
if (!rtx_equal_p (op2, value))
return false;
/* We require that we hit a power of two at least half of all evaluations. */
if (count < wrong_values)
return false;
if (dump_file)
fprintf (dump_file, "Mod power of 2 transformation on insn %d\n",
INSN_UID (insn));
/* Compute probability of taking the optimal path. */
all = count + wrong_values;
prob = (count * REG_BR_PROB_BASE + all / 2) / all;
e = split_block (BLOCK_FOR_INSN (insn), PREV_INSN (insn));
delete_insn (insn);
insert_insn_on_edge (
gen_mod_pow2 (mode, code, set_dest, op1, op2, prob), e);
return true;
}
int
rtx_equal_p (const_rtx x, const_rtx y)
{
int i;
int j;
enum rtx_code code;
const char *fmt;
if (x == y)
return 1;
if (x == 0 || y == 0)
return 0;
code = GET_CODE (x);
/* Rtx's of different codes cannot be equal. */
if (code != GET_CODE (y))
return 0;
/* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
(REG:SI x) and (REG:HI x) are NOT equivalent. */
if (GET_MODE (x) != GET_MODE (y))
return 0;
/* MEMs referring to different address space are not equivalent. */
if (code == MEM && MEM_ADDR_SPACE (x) != MEM_ADDR_SPACE (y))
return 0;
/* Some RTL can be compared nonrecursively. */
switch (code)
{
case REG:
return (REGNO (x) == REGNO (y));
case LABEL_REF:
return XEXP (x, 0) == XEXP (y, 0);
case SYMBOL_REF:
return XSTR (x, 0) == XSTR (y, 0);
case DEBUG_EXPR:
case VALUE:
case SCRATCH:
case CONST_DOUBLE:
case CONST_INT:
case CONST_FIXED:
return 0;
case DEBUG_IMPLICIT_PTR:
return DEBUG_IMPLICIT_PTR_DECL (x)
== DEBUG_IMPLICIT_PTR_DECL (y);
case DEBUG_PARAMETER_REF:
return DEBUG_PARAMETER_REF_DECL (x)
== DEBUG_PARAMETER_REF_DECL (y);
case ENTRY_VALUE:
return rtx_equal_p (ENTRY_VALUE_EXP (x), ENTRY_VALUE_EXP (y));
default:
break;
}
/* Compare the elements. If any pair of corresponding elements
fail to match, return 0 for the whole thing. */
fmt = GET_RTX_FORMAT (code);
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
{
switch (fmt[i])
{
case 'w':
if (XWINT (x, i) != XWINT (y, i))
return 0;
break;
case 'n':
case 'i':
if (XINT (x, i) != XINT (y, i))
{
#ifndef GENERATOR_FILE
if (((code == ASM_OPERANDS && i == 6)
|| (code == ASM_INPUT && i == 1))
&& locator_eq (XINT (x, i), XINT (y, i)))
break;
#endif
return 0;
}
break;
case 'V':
case 'E':
/* Two vectors must have the same length. */
if (XVECLEN (x, i) != XVECLEN (y, i))
return 0;
/* And the corresponding elements must match. */
for (j = 0; j < XVECLEN (x, i); j++)
if (rtx_equal_p (XVECEXP (x, i, j), XVECEXP (y, i, j)) == 0)
return 0;
break;
case 'e':
if (rtx_equal_p (XEXP (x, i), XEXP (y, i)) == 0)
return 0;
break;
case 'S':
case 's':
if ((XSTR (x, i) || XSTR (y, i))
&& (! XSTR (x, i) || ! XSTR (y, i)
|| strcmp (XSTR (x, i), XSTR (y, i))))
return 0;
break;
case 'u':
/* These are just backpointers, so they don't matter. */
break;
case '0':
case 't':
break;
/* It is believed that rtx's at this level will never
contain anything but integers and other rtx's,
except for within LABEL_REFs and SYMBOL_REFs. */
default:
gcc_unreachable ();
}
}
return 1;
}
static void
mark_all_labels (rtx f)
{
rtx insn;
rtx prev_nonjump_insn = NULL;
for (insn = f; insn; insn = NEXT_INSN (insn))
if (INSN_P (insn))
{
mark_jump_label (PATTERN (insn), insn, 0);
/* If the previous non-jump insn sets something to a label,
something that this jump insn uses, make that label the primary
target of this insn if we don't yet have any. That previous
insn must be a single_set and not refer to more than one label.
The jump insn must not refer to other labels as jump targets
and must be a plain (set (pc) ...), maybe in a parallel, and
may refer to the item being set only directly or as one of the
arms in an IF_THEN_ELSE. */
if (! INSN_DELETED_P (insn)
&& JUMP_P (insn)
&& JUMP_LABEL (insn) == NULL)
{
rtx label_note = NULL;
rtx pc = pc_set (insn);
rtx pc_src = pc != NULL ? SET_SRC (pc) : NULL;
if (prev_nonjump_insn != NULL)
label_note
= find_reg_note (prev_nonjump_insn, REG_LABEL_OPERAND, NULL);
if (label_note != NULL && pc_src != NULL)
{
rtx label_set = single_set (prev_nonjump_insn);
rtx label_dest
= label_set != NULL ? SET_DEST (label_set) : NULL;
if (label_set != NULL
/* The source must be the direct LABEL_REF, not a
PLUS, UNSPEC, IF_THEN_ELSE etc. */
&& GET_CODE (SET_SRC (label_set)) == LABEL_REF
&& (rtx_equal_p (label_dest, pc_src)
|| (GET_CODE (pc_src) == IF_THEN_ELSE
&& (rtx_equal_p (label_dest, XEXP (pc_src, 1))
|| rtx_equal_p (label_dest,
XEXP (pc_src, 2))))))
{
/* The CODE_LABEL referred to in the note must be the
CODE_LABEL in the LABEL_REF of the "set". We can
conveniently use it for the marker function, which
requires a LABEL_REF wrapping. */
gcc_assert (XEXP (label_note, 0)
== XEXP (SET_SRC (label_set), 0));
mark_jump_label_1 (label_set, insn, false, true);
gcc_assert (JUMP_LABEL (insn)
== XEXP (SET_SRC (label_set), 0));
}
}
}
else if (! INSN_DELETED_P (insn))
prev_nonjump_insn = insn;
}
else if (LABEL_P (insn))
prev_nonjump_insn = NULL;
/* If we are in cfglayout mode, there may be non-insns between the
basic blocks. If those non-insns represent tablejump data, they
contain label references that we must record. */
if (current_ir_type () == IR_RTL_CFGLAYOUT)
{
basic_block bb;
rtx insn;
FOR_EACH_BB (bb)
{
for (insn = bb->il.rtl->header; insn; insn = NEXT_INSN (insn))
if (INSN_P (insn))
{
gcc_assert (JUMP_TABLE_DATA_P (insn));
mark_jump_label (PATTERN (insn), insn, 0);
}
for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
if (INSN_P (insn))
{
gcc_assert (JUMP_TABLE_DATA_P (insn));
mark_jump_label (PATTERN (insn), insn, 0);
}
}
}
static bool
speculative_prefetching_transform (rtx insn)
{
rtx histogram, value;
gcov_type val, count, all;
edge e;
rtx mem, address;
int write;
if (!maybe_hot_bb_p (BLOCK_FOR_INSN (insn)))
return false;
if (!find_mem_reference (insn, &mem, &write))
return false;
address = XEXP (mem, 0);
if (side_effects_p (address))
return false;
if (CONSTANT_P (address))
return false;
for (histogram = REG_NOTES (insn);
histogram;
histogram = XEXP (histogram, 1))
if (REG_NOTE_KIND (histogram) == REG_VALUE_PROFILE
&& XEXP (XEXP (histogram, 0), 0) == GEN_INT (HIST_TYPE_CONST_DELTA))
break;
if (!histogram)
return false;
histogram = XEXP (XEXP (histogram, 0), 1);
value = XEXP (histogram, 0);
histogram = XEXP (histogram, 1);
/* Skip last value referenced. */
histogram = XEXP (histogram, 1);
val = INTVAL (XEXP (histogram, 0));
histogram = XEXP (histogram, 1);
count = INTVAL (XEXP (histogram, 0));
histogram = XEXP (histogram, 1);
all = INTVAL (XEXP (histogram, 0));
/* With that few executions we do not really have a reason to optimize the
statement, and more importantly, the data about differences of addresses
are spoiled by the first item that had no previous value to compare
with. */
if (all < 4)
return false;
/* We require that count be at least half of all; this means
that for the transformation to fire the value must be constant
at least 50% of time (and 75% gives the guarantee of usage). */
if (!rtx_equal_p (address, value) || 2 * count < all)
return false;
/* If the difference is too small, it does not make too much sense to
prefetch, as the memory is probably already in cache. */
if (val >= NOPREFETCH_RANGE_MIN && val <= NOPREFETCH_RANGE_MAX)
return false;
if (dump_file)
fprintf (dump_file, "Speculative prefetching for insn %d\n",
INSN_UID (insn));
e = split_block (BLOCK_FOR_INSN (insn), PREV_INSN (insn));
insert_insn_on_edge (gen_speculative_prefetch (address, val, write), e);
return true;
}
static bool
find_call_stack_args (rtx_call_insn *call_insn, bool do_mark, bool fast,
bitmap arg_stores)
{
rtx p;
rtx_insn *insn, *prev_insn;
bool ret;
HOST_WIDE_INT min_sp_off, max_sp_off;
bitmap sp_bytes;
gcc_assert (CALL_P (call_insn));
if (!ACCUMULATE_OUTGOING_ARGS)
return true;
if (!do_mark)
{
gcc_assert (arg_stores);
bitmap_clear (arg_stores);
}
min_sp_off = INTTYPE_MAXIMUM (HOST_WIDE_INT);
max_sp_off = 0;
/* First determine the minimum and maximum offset from sp for
stored arguments. */
for (p = CALL_INSN_FUNCTION_USAGE (call_insn); p; p = XEXP (p, 1))
if (GET_CODE (XEXP (p, 0)) == USE
&& MEM_P (XEXP (XEXP (p, 0), 0)))
{
rtx mem = XEXP (XEXP (p, 0), 0), addr;
HOST_WIDE_INT off = 0, size;
if (!MEM_SIZE_KNOWN_P (mem))
return false;
size = MEM_SIZE (mem);
addr = XEXP (mem, 0);
if (GET_CODE (addr) == PLUS
&& REG_P (XEXP (addr, 0))
&& CONST_INT_P (XEXP (addr, 1)))
{
off = INTVAL (XEXP (addr, 1));
addr = XEXP (addr, 0);
}
if (addr != stack_pointer_rtx)
{
if (!REG_P (addr))
return false;
/* If not fast, use chains to see if addr wasn't set to
sp + offset. */
if (!fast)
{
df_ref use;
struct df_link *defs;
rtx set;
FOR_EACH_INSN_USE (use, call_insn)
if (rtx_equal_p (addr, DF_REF_REG (use)))
break;
if (use == NULL)
return false;
for (defs = DF_REF_CHAIN (use); defs; defs = defs->next)
if (! DF_REF_IS_ARTIFICIAL (defs->ref))
break;
if (defs == NULL)
return false;
set = single_set (DF_REF_INSN (defs->ref));
if (!set)
return false;
if (GET_CODE (SET_SRC (set)) != PLUS
|| XEXP (SET_SRC (set), 0) != stack_pointer_rtx
|| !CONST_INT_P (XEXP (SET_SRC (set), 1)))
return false;
off += INTVAL (XEXP (SET_SRC (set), 1));
}
else
return false;
void
find_comparison_dom_walker::before_dom_children (basic_block bb)
{
struct comparison *last_cmp;
rtx insn, next, last_clobber;
bool last_cmp_valid;
bool need_purge = false;
bitmap killed;
killed = BITMAP_ALLOC (NULL);
/* The last comparison that was made. Will be reset to NULL
once the flags are clobbered. */
last_cmp = NULL;
/* True iff the last comparison has not been clobbered, nor
have its inputs. Used to eliminate duplicate compares. */
last_cmp_valid = false;
/* The last insn that clobbered the flags, if that insn is of
a form that may be valid for eliminating a following compare.
To be reset to NULL once the flags are set otherwise. */
last_clobber = NULL;
/* Propagate the last live comparison throughout the extended basic block. */
if (single_pred_p (bb))
{
last_cmp = (struct comparison *) single_pred (bb)->aux;
if (last_cmp)
last_cmp_valid = last_cmp->inputs_valid;
}
for (insn = BB_HEAD (bb); insn; insn = next)
{
rtx src;
next = (insn == BB_END (bb) ? NULL_RTX : NEXT_INSN (insn));
if (!NONDEBUG_INSN_P (insn))
continue;
/* Compute the set of registers modified by this instruction. */
bitmap_clear (killed);
df_simulate_find_defs (insn, killed);
src = conforming_compare (insn);
if (src)
{
enum machine_mode src_mode = GET_MODE (src);
rtx eh_note = NULL;
if (flag_non_call_exceptions)
eh_note = find_reg_note (insn, REG_EH_REGION, NULL);
if (!last_cmp_valid)
goto dont_delete;
/* Take care that it's in the same EH region. */
if (flag_non_call_exceptions
&& !rtx_equal_p (eh_note, last_cmp->eh_note))
goto dont_delete;
/* Make sure the compare is redundant with the previous. */
if (!rtx_equal_p (last_cmp->in_a, XEXP (src, 0))
|| !rtx_equal_p (last_cmp->in_b, XEXP (src, 1)))
goto dont_delete;
/* New mode must be compatible with the previous compare mode. */
{
enum machine_mode new_mode
= targetm.cc_modes_compatible (last_cmp->orig_mode, src_mode);
if (new_mode == VOIDmode)
goto dont_delete;
if (new_mode != last_cmp->orig_mode)
{
rtx x, flags = gen_rtx_REG (src_mode, targetm.flags_regnum);
/* Generate new comparison for substitution. */
x = gen_rtx_COMPARE (new_mode, XEXP (src, 0), XEXP (src, 1));
x = gen_rtx_SET (VOIDmode, flags, x);
if (!validate_change (last_cmp->insn,
&PATTERN (last_cmp->insn), x, false))
goto dont_delete;
last_cmp->orig_mode = new_mode;
}
}
/* All tests and substitutions succeeded! */
if (eh_note)
need_purge = true;
delete_insn (insn);
continue;
dont_delete:
last_cmp = XCNEW (struct comparison);
last_cmp->insn = insn;
last_cmp->prev_clobber = last_clobber;
last_cmp->in_a = XEXP (src, 0);
last_cmp->in_b = XEXP (src, 1);
last_cmp->eh_note = eh_note;
last_cmp->orig_mode = src_mode;
all_compares.safe_push (last_cmp);
/* It's unusual, but be prepared for comparison patterns that
also clobber an input, or perhaps a scratch. */
last_clobber = NULL;
last_cmp_valid = true;
}
/* Notice if this instruction kills the flags register. */
else if (bitmap_bit_p (killed, targetm.flags_regnum))
{
/* See if this insn could be the "clobber" that eliminates
a future comparison. */
last_clobber = (arithmetic_flags_clobber_p (insn) ? insn : NULL);
/* In either case, the previous compare is no longer valid. */
last_cmp = NULL;
last_cmp_valid = false;
continue;
}
/* Notice if this instruction uses the flags register. */
else if (last_cmp)
find_flags_uses_in_insn (last_cmp, insn);
/* Notice if any of the inputs to the comparison have changed. */
if (last_cmp_valid
&& (bitmap_bit_p (killed, REGNO (last_cmp->in_a))
|| (REG_P (last_cmp->in_b)
&& bitmap_bit_p (killed, REGNO (last_cmp->in_b)))))
last_cmp_valid = false;
}
static bool
propagate_rtx_1 (rtx *px, rtx old_rtx, rtx new_rtx, int flags)
{
rtx x = *px, tem = NULL_RTX, op0, op1, op2;
enum rtx_code code = GET_CODE (x);
machine_mode mode = GET_MODE (x);
machine_mode op_mode;
bool can_appear = (flags & PR_CAN_APPEAR) != 0;
bool valid_ops = true;
if (!(flags & PR_HANDLE_MEM) && MEM_P (x) && !MEM_READONLY_P (x))
{
/* If unsafe, change MEMs to CLOBBERs or SCRATCHes (to preserve whether
they have side effects or not). */
*px = (side_effects_p (x)
? gen_rtx_CLOBBER (GET_MODE (x), const0_rtx)
: gen_rtx_SCRATCH (GET_MODE (x)));
return false;
}
/* If X is OLD_RTX, return NEW_RTX. But not if replacing only within an
address, and we are *not* inside one. */
if (x == old_rtx)
{
*px = new_rtx;
return can_appear;
}
/* If this is an expression, try recursive substitution. */
switch (GET_RTX_CLASS (code))
{
case RTX_UNARY:
op0 = XEXP (x, 0);
op_mode = GET_MODE (op0);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0))
return true;
tem = simplify_gen_unary (code, mode, op0, op_mode);
break;
case RTX_BIN_ARITH:
case RTX_COMM_ARITH:
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
return true;
tem = simplify_gen_binary (code, mode, op0, op1);
break;
case RTX_COMPARE:
case RTX_COMM_COMPARE:
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
op_mode = GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
return true;
tem = simplify_gen_relational (code, mode, op_mode, op0, op1);
break;
case RTX_TERNARY:
case RTX_BITFIELD_OPS:
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
op2 = XEXP (x, 2);
op_mode = GET_MODE (op0);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);
valid_ops &= propagate_rtx_1 (&op2, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1) && op2 == XEXP (x, 2))
return true;
if (op_mode == VOIDmode)
op_mode = GET_MODE (op0);
tem = simplify_gen_ternary (code, mode, op_mode, op0, op1, op2);
break;
case RTX_EXTRA:
/* The only case we try to handle is a SUBREG. */
if (code == SUBREG)
{
op0 = XEXP (x, 0);
valid_ops &= propagate_rtx_1 (&op0, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0))
return true;
tem = simplify_gen_subreg (mode, op0, GET_MODE (SUBREG_REG (x)),
SUBREG_BYTE (x));
}
break;
case RTX_OBJ:
if (code == MEM && x != new_rtx)
{
rtx new_op0;
op0 = XEXP (x, 0);
/* There are some addresses that we cannot work on. */
if (!can_simplify_addr (op0))
return true;
op0 = new_op0 = targetm.delegitimize_address (op0);
valid_ops &= propagate_rtx_1 (&new_op0, old_rtx, new_rtx,
flags | PR_CAN_APPEAR);
/* Dismiss transformation that we do not want to carry on. */
if (!valid_ops
|| new_op0 == op0
|| !(GET_MODE (new_op0) == GET_MODE (op0)
|| GET_MODE (new_op0) == VOIDmode))
return true;
canonicalize_address (new_op0);
/* Copy propagations are always ok. Otherwise check the costs. */
if (!(REG_P (old_rtx) && REG_P (new_rtx))
&& !should_replace_address (op0, new_op0, GET_MODE (x),
MEM_ADDR_SPACE (x),
flags & PR_OPTIMIZE_FOR_SPEED))
return true;
tem = replace_equiv_address_nv (x, new_op0);
}
else if (code == LO_SUM)
{
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
/* The only simplification we do attempts to remove references to op0
or make it constant -- in both cases, op0's invalidity will not
make the result invalid. */
propagate_rtx_1 (&op0, old_rtx, new_rtx, flags | PR_CAN_APPEAR);
valid_ops &= propagate_rtx_1 (&op1, old_rtx, new_rtx, flags);
if (op0 == XEXP (x, 0) && op1 == XEXP (x, 1))
return true;
/* (lo_sum (high x) x) -> x */
if (GET_CODE (op0) == HIGH && rtx_equal_p (XEXP (op0, 0), op1))
tem = op1;
else
tem = gen_rtx_LO_SUM (mode, op0, op1);
/* OP1 is likely not a legitimate address, otherwise there would have
been no LO_SUM. We want it to disappear if it is invalid, return
false in that case. */
return memory_address_p (mode, tem);
}
else if (code == REG)
{
if (rtx_equal_p (x, old_rtx))
{
*px = new_rtx;
return can_appear;
}
}
break;
default:
break;
}
/* No change, no trouble. */
if (tem == NULL_RTX)
return true;
*px = tem;
/* Allow replacements that simplify operations on a vector or complex
value to a component. The most prominent case is
(subreg ([vec_]concat ...)). */
if (REG_P (tem) && !HARD_REGISTER_P (tem)
&& (VECTOR_MODE_P (GET_MODE (new_rtx))
|| COMPLEX_MODE_P (GET_MODE (new_rtx)))
&& GET_MODE (tem) == GET_MODE_INNER (GET_MODE (new_rtx)))
return true;
/* The replacement we made so far is valid, if all of the recursive
replacements were valid, or we could simplify everything to
a constant. */
return valid_ops || can_appear || CONSTANT_P (tem);
}
static rtx
may_unswitch_on (basic_block bb, struct loop *loop, rtx *cinsn)
{
rtx test, at, op[2], stest;
struct rtx_iv iv;
unsigned i;
enum machine_mode mode;
/* BB must end in a simple conditional jump. */
if (EDGE_COUNT (bb->succs) != 2)
return NULL_RTX;
if (!any_condjump_p (BB_END (bb)))
return NULL_RTX;
/* With branches inside loop. */
if (!flow_bb_inside_loop_p (loop, EDGE_SUCC (bb, 0)->dest)
|| !flow_bb_inside_loop_p (loop, EDGE_SUCC (bb, 1)->dest))
return NULL_RTX;
/* It must be executed just once each iteration (because otherwise we
are unable to update dominator/irreducible loop information correctly). */
if (!just_once_each_iteration_p (loop, bb))
return NULL_RTX;
/* Condition must be invariant. */
test = get_condition (BB_END (bb), &at, true, false);
if (!test)
return NULL_RTX;
for (i = 0; i < 2; i++)
{
op[i] = XEXP (test, i);
if (CONSTANT_P (op[i]))
continue;
if (!iv_analyze (at, op[i], &iv))
return NULL_RTX;
if (iv.step != const0_rtx
|| iv.first_special)
return NULL_RTX;
op[i] = get_iv_value (&iv, const0_rtx);
}
mode = GET_MODE (op[0]);
if (mode == VOIDmode)
mode = GET_MODE (op[1]);
if (GET_MODE_CLASS (mode) == MODE_CC)
{
if (at != BB_END (bb))
return NULL_RTX;
if (!rtx_equal_p (op[0], XEXP (test, 0))
|| !rtx_equal_p (op[1], XEXP (test, 1)))
return NULL_RTX;
*cinsn = BB_END (bb);
return test;
}
stest = simplify_gen_relational (GET_CODE (test), SImode,
mode, op[0], op[1]);
if (stest == const0_rtx
|| stest == const_true_rtx)
return stest;
return canon_condition (gen_rtx_fmt_ee (GET_CODE (test), SImode,
op[0], op[1]));
}
int
rtx_equal_p (rtx x, rtx y)
{
int i;
int j;
enum rtx_code code;
const char *fmt;
if (x == y)
return 1;
if (x == 0 || y == 0)
return 0;
code = GET_CODE (x);
/* Rtx's of different codes cannot be equal. */
if (code != GET_CODE (y))
return 0;
/* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
(REG:SI x) and (REG:HI x) are NOT equivalent. */
if (GET_MODE (x) != GET_MODE (y))
return 0;
/* Some RTL can be compared nonrecursively. */
switch (code)
{
case REG:
return (REGNO (x) == REGNO (y));
case LABEL_REF:
return XEXP (x, 0) == XEXP (y, 0);
case SYMBOL_REF:
return XSTR (x, 0) == XSTR (y, 0);
case SCRATCH:
case CONST_DOUBLE:
case CONST_INT:
return 0;
default:
break;
}
/* Compare the elements. If any pair of corresponding elements
fail to match, return 0 for the whole thing. */
fmt = GET_RTX_FORMAT (code);
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
{
switch (fmt[i])
{
case 'w':
if (XWINT (x, i) != XWINT (y, i))
return 0;
break;
case 'n':
case 'i':
if (XINT (x, i) != XINT (y, i))
return 0;
break;
case 'V':
case 'E':
/* Two vectors must have the same length. */
if (XVECLEN (x, i) != XVECLEN (y, i))
return 0;
/* And the corresponding elements must match. */
for (j = 0; j < XVECLEN (x, i); j++)
if (rtx_equal_p (XVECEXP (x, i, j), XVECEXP (y, i, j)) == 0)
return 0;
break;
case 'e':
if (rtx_equal_p (XEXP (x, i), XEXP (y, i)) == 0)
return 0;
break;
case 'S':
case 's':
if ((XSTR (x, i) || XSTR (y, i))
&& (! XSTR (x, i) || ! XSTR (y, i)
|| strcmp (XSTR (x, i), XSTR (y, i))))
return 0;
break;
case 'u':
/* These are just backpointers, so they don't matter. */
break;
case '0':
case 't':
break;
/* It is believed that rtx's at this level will never
contain anything but integers and other rtx's,
except for within LABEL_REFs and SYMBOL_REFs. */
default:
gcc_unreachable ();
}
}
return 1;
}
static bool
find_inc (bool first_try)
{
rtx insn;
basic_block bb = BLOCK_FOR_INSN (mem_insn.insn);
rtx other_insn;
df_ref *def_rec;
/* Make sure this reg appears only once in this insn. */
if (count_occurrences (PATTERN (mem_insn.insn), mem_insn.reg0, 1) != 1)
{
if (dump_file)
fprintf (dump_file, "mem count failure\n");
return false;
}
if (dump_file)
dump_mem_insn (dump_file);
/* Find the next use that is an inc. */
insn = get_next_ref (REGNO (mem_insn.reg0),
BLOCK_FOR_INSN (mem_insn.insn),
reg_next_inc_use);
if (!insn)
return false;
/* Even though we know the next use is an add or inc because it came
from the reg_next_inc_use, we must still reparse. */
if (!parse_add_or_inc (insn, false))
{
/* Next use was not an add. Look for one extra case. It could be
that we have:
*(a + b)
...= a;
...= b + a
if we reverse the operands in the mem ref we would
find this. Only try it once though. */
if (first_try && !mem_insn.reg1_is_const)
{
reverse_mem ();
return find_inc (false);
}
else
return false;
}
/* Need to assure that none of the operands of the inc instruction are
assigned to by the mem insn. */
for (def_rec = DF_INSN_DEFS (mem_insn.insn); *def_rec; def_rec++)
{
df_ref def = *def_rec;
unsigned int regno = DF_REF_REGNO (def);
if ((regno == REGNO (inc_insn.reg0))
|| (regno == REGNO (inc_insn.reg_res)))
{
if (dump_file)
fprintf (dump_file, "inc conflicts with store failure.\n");
return false;
}
if (!inc_insn.reg1_is_const && (regno == REGNO (inc_insn.reg1)))
{
if (dump_file)
fprintf (dump_file, "inc conflicts with store failure.\n");
return false;
}
}
if (dump_file)
dump_inc_insn (dump_file);
if (inc_insn.form == FORM_POST_ADD)
{
/* Make sure that there is no insn that assigns to inc_insn.res
between the mem_insn and the inc_insn. */
rtx other_insn = get_next_ref (REGNO (inc_insn.reg_res),
BLOCK_FOR_INSN (mem_insn.insn),
reg_next_def);
if (other_insn != inc_insn.insn)
{
if (dump_file)
fprintf (dump_file,
"result of add is assigned to between mem and inc insns.\n");
return false;
}
other_insn = get_next_ref (REGNO (inc_insn.reg_res),
BLOCK_FOR_INSN (mem_insn.insn),
reg_next_use);
if (other_insn
&& (other_insn != inc_insn.insn)
&& (DF_INSN_LUID (inc_insn.insn) > DF_INSN_LUID (other_insn)))
{
if (dump_file)
fprintf (dump_file,
"result of add is used between mem and inc insns.\n");
return false;
}
/* For the post_add to work, the result_reg of the inc must not be
used in the mem insn since this will become the new index
register. */
if (reg_overlap_mentioned_p (inc_insn.reg_res, PATTERN (mem_insn.insn)))
{
if (dump_file)
fprintf (dump_file, "base reg replacement failure.\n");
return false;
}
}
if (mem_insn.reg1_is_const)
{
if (mem_insn.reg1_val == 0)
{
if (!inc_insn.reg1_is_const)
{
/* The mem looks like *r0 and the rhs of the add has two
registers. */
int luid = DF_INSN_LUID (inc_insn.insn);
if (inc_insn.form == FORM_POST_ADD)
{
/* The trick is that we are not going to increment r0,
we are going to increment the result of the add insn.
For this trick to be correct, the result reg of
the inc must be a valid addressing reg. */
addr_space_t as = MEM_ADDR_SPACE (*mem_insn.mem_loc);
if (GET_MODE (inc_insn.reg_res)
!= targetm.addr_space.address_mode (as))
{
if (dump_file)
fprintf (dump_file, "base reg mode failure.\n");
return false;
}
/* We also need to make sure that the next use of
inc result is after the inc. */
other_insn
= get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_use);
if (other_insn && luid > DF_INSN_LUID (other_insn))
return false;
if (!rtx_equal_p (mem_insn.reg0, inc_insn.reg0))
reverse_inc ();
}
other_insn
= get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def);
if (other_insn && luid > DF_INSN_LUID (other_insn))
return false;
}
}
/* Both the inc/add and the mem have a constant. Need to check
that the constants are ok. */
else if ((mem_insn.reg1_val != inc_insn.reg1_val)
&& (mem_insn.reg1_val != -inc_insn.reg1_val))
return false;
}
else
{
/* The mem insn is of the form *(a + b) where a and b are both
regs. It may be that in order to match the add or inc we
need to treat it as if it was *(b + a). It may also be that
the add is of the form a + c where c does not match b and
then we just abandon this. */
int luid = DF_INSN_LUID (inc_insn.insn);
rtx other_insn;
/* Make sure this reg appears only once in this insn. */
if (count_occurrences (PATTERN (mem_insn.insn), mem_insn.reg1, 1) != 1)
return false;
if (inc_insn.form == FORM_POST_ADD)
{
/* For this trick to be correct, the result reg of the inc
must be a valid addressing reg. */
addr_space_t as = MEM_ADDR_SPACE (*mem_insn.mem_loc);
if (GET_MODE (inc_insn.reg_res)
!= targetm.addr_space.address_mode (as))
{
if (dump_file)
fprintf (dump_file, "base reg mode failure.\n");
return false;
}
if (rtx_equal_p (mem_insn.reg0, inc_insn.reg0))
{
if (!rtx_equal_p (mem_insn.reg1, inc_insn.reg1))
{
/* See comment above on find_inc (false) call. */
if (first_try)
{
reverse_mem ();
return find_inc (false);
}
else
return false;
}
/* Need to check that there are no assignments to b
before the add insn. */
other_insn
= get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def);
if (other_insn && luid > DF_INSN_LUID (other_insn))
return false;
/* All ok for the next step. */
}
else
{
/* We know that mem_insn.reg0 must equal inc_insn.reg1
or else we would not have found the inc insn. */
reverse_mem ();
if (!rtx_equal_p (mem_insn.reg0, inc_insn.reg0))
{
/* See comment above on find_inc (false) call. */
if (first_try)
return find_inc (false);
else
return false;
}
/* To have gotten here know that.
*(b + a)
... = (b + a)
We also know that the lhs of the inc is not b or a. We
need to make sure that there are no assignments to b
between the mem ref and the inc. */
other_insn
= get_next_ref (REGNO (inc_insn.reg0), bb, reg_next_def);
if (other_insn && luid > DF_INSN_LUID (other_insn))
return false;
}
/* Need to check that the next use of the add result is later than
add insn since this will be the reg incremented. */
other_insn
= get_next_ref (REGNO (inc_insn.reg_res), bb, reg_next_use);
if (other_insn && luid > DF_INSN_LUID (other_insn))
return false;
}
else /* FORM_POST_INC. There is less to check here because we
know that operands must line up. */
{
if (!rtx_equal_p (mem_insn.reg1, inc_insn.reg1))
/* See comment above on find_inc (false) call. */
{
if (first_try)
{
reverse_mem ();
return find_inc (false);
}
else
return false;
}
/* To have gotten here know that.
*(a + b)
... = (a + b)
We also know that the lhs of the inc is not b. We need to make
sure that there are no assignments to b between the mem ref and
the inc. */
other_insn
= get_next_ref (REGNO (inc_insn.reg1), bb, reg_next_def);
if (other_insn && luid > DF_INSN_LUID (other_insn))
return false;
}
}
if (inc_insn.form == FORM_POST_INC)
{
other_insn
= get_next_ref (REGNO (inc_insn.reg0), bb, reg_next_use);
/* When we found inc_insn, we were looking for the
next add or inc, not the next insn that used the
reg. Because we are going to increment the reg
in this form, we need to make sure that there
were no intervening uses of reg. */
if (inc_insn.insn != other_insn)
return false;
}
return try_merge ();
}
/* Check if *XP is equivalent to Y. Until an an unreconcilable difference is
found, use in-group changes with validate_change on *XP to make register
assignments agree. It is the (not necessarily direct) callers
responsibility to verify / confirm / cancel these changes, as appropriate.
RVALUE indicates if the processed piece of rtl is used as a destination, in
which case we can't have different registers being an input. Returns
nonzero if the two blocks have been identified as equivalent, zero otherwise.
RVALUE == 0: destination
RVALUE == 1: source
RVALUE == -1: source, ignore SET_DEST of SET / clobber. */
bool
rtx_equiv_p (rtx *xp, rtx y, int rvalue, struct equiv_info *info)
{
rtx x = *xp;
enum rtx_code code;
int length;
const char *format;
int i;
if (!y || !x)
return x == y;
code = GET_CODE (y);
if (code != REG && x == y)
return true;
if (GET_CODE (x) != code
|| GET_MODE (x) != GET_MODE (y))
return false;
/* ??? could extend to allow CONST_INT inputs. */
switch (code)
{
case REG:
{
unsigned x_regno = REGNO (x);
unsigned y_regno = REGNO (y);
int x_common_live, y_common_live;
if (reload_completed
&& (x_regno >= FIRST_PSEUDO_REGISTER
|| y_regno >= FIRST_PSEUDO_REGISTER))
{
/* We should only see this in REG_NOTEs. */
gcc_assert (!info->live_update);
/* Returning false will cause us to remove the notes. */
return false;
}
#ifdef STACK_REGS
/* After reg-stack, can only accept literal matches of stack regs. */
if (info->mode & CLEANUP_POST_REGSTACK
&& (IN_RANGE (x_regno, FIRST_STACK_REG, LAST_STACK_REG)
|| IN_RANGE (y_regno, FIRST_STACK_REG, LAST_STACK_REG)))
return x_regno == y_regno;
#endif
/* If the register is a locally live one in one block, the
corresponding one must be locally live in the other, too, and
match of identical regnos doesn't apply. */
if (REGNO_REG_SET_P (info->x_local_live, x_regno))
{
if (!REGNO_REG_SET_P (info->y_local_live, y_regno))
return false;
}
else if (REGNO_REG_SET_P (info->y_local_live, y_regno))
return false;
else if (x_regno == y_regno)
{
if (!rvalue && info->cur.input_valid
&& (reg_overlap_mentioned_p (x, info->x_input)
|| reg_overlap_mentioned_p (x, info->y_input)))
return false;
/* Update liveness information. */
if (info->live_update
&& assign_reg_reg_set (info->common_live, x, rvalue))
info->cur.version++;
return true;
}
x_common_live = REGNO_REG_SET_P (info->common_live, x_regno);
y_common_live = REGNO_REG_SET_P (info->common_live, y_regno);
if (x_common_live != y_common_live)
return false;
else if (x_common_live)
{
if (! rvalue || info->input_cost < 0 || no_new_pseudos)
return false;
/* If info->live_update is not set, we are processing notes.
We then allow a match with x_input / y_input found in a
previous pass. */
if (info->live_update && !info->cur.input_valid)
{
info->cur.input_valid = true;
info->x_input = x;
info->y_input = y;
info->cur.input_count += optimize_size ? 2 : 1;
if (info->input_reg
&& GET_MODE (info->input_reg) != GET_MODE (info->x_input))
info->input_reg = NULL_RTX;
if (!info->input_reg)
info->input_reg = gen_reg_rtx (GET_MODE (info->x_input));
}
else if ((info->live_update
? ! info->cur.input_valid : ! info->x_input)
|| ! rtx_equal_p (x, info->x_input)
|| ! rtx_equal_p (y, info->y_input))
return false;
validate_change (info->cur.x_start, xp, info->input_reg, 1);
}
else
{
int x_nregs = (x_regno >= FIRST_PSEUDO_REGISTER
? 1 : hard_regno_nregs[x_regno][GET_MODE (x)]);
int y_nregs = (y_regno >= FIRST_PSEUDO_REGISTER
? 1 : hard_regno_nregs[y_regno][GET_MODE (y)]);
int size = GET_MODE_SIZE (GET_MODE (x));
enum machine_mode x_mode = GET_MODE (x);
unsigned x_regno_i, y_regno_i;
int x_nregs_i, y_nregs_i, size_i;
int local_count = info->cur.local_count;
/* This might be a register local to each block. See if we have
it already registered. */
for (i = local_count - 1; i >= 0; i--)
{
x_regno_i = REGNO (info->x_local[i]);
x_nregs_i = (x_regno_i >= FIRST_PSEUDO_REGISTER
? 1 : hard_regno_nregs[x_regno_i][GET_MODE (x)]);
y_regno_i = REGNO (info->y_local[i]);
y_nregs_i = (y_regno_i >= FIRST_PSEUDO_REGISTER
? 1 : hard_regno_nregs[y_regno_i][GET_MODE (y)]);
size_i = GET_MODE_SIZE (GET_MODE (info->x_local[i]));
/* If we have a new pair of registers that is wider than an
old pair and enclosing it with matching offsets,
remove the old pair. If we find a matching, wider, old
pair, use the old one. If the width is the same, use the
old one if the modes match, but the new if they don't.
We don't want to get too fancy with subreg_regno_offset
here, so we just test two straightforward cases each. */
if (info->live_update
&& (x_mode != GET_MODE (info->x_local[i])
? size >= size_i : size > size_i))
{
/* If the new pair is fully enclosing a matching
existing pair, remove the old one. N.B. because
we are removing one entry here, the check below
if we have space for a new entry will succeed. */
if ((x_regno <= x_regno_i
&& x_regno + x_nregs >= x_regno_i + x_nregs_i
&& x_nregs == y_nregs && x_nregs_i == y_nregs_i
&& x_regno - x_regno_i == y_regno - y_regno_i)
|| (x_regno == x_regno_i && y_regno == y_regno_i
&& x_nregs >= x_nregs_i && y_nregs >= y_nregs_i))
{
info->cur.local_count = --local_count;
info->x_local[i] = info->x_local[local_count];
info->y_local[i] = info->y_local[local_count];
continue;
}
}
else
{
/* If the new pair is fully enclosed within a matching
existing pair, succeed. */
if (x_regno >= x_regno_i
&& x_regno + x_nregs <= x_regno_i + x_nregs_i
&& x_nregs == y_nregs && x_nregs_i == y_nregs_i
&& x_regno - x_regno_i == y_regno - y_regno_i)
break;
if (x_regno == x_regno_i && y_regno == y_regno_i
&& x_nregs <= x_nregs_i && y_nregs <= y_nregs_i)
break;
}
/* Any other overlap causes a match failure. */
if (x_regno + x_nregs > x_regno_i
&& x_regno_i + x_nregs_i > x_regno)
return false;
if (y_regno + y_nregs > y_regno_i
&& y_regno_i + y_nregs_i > y_regno)
return false;
}
if (i < 0)
{
/* Not found. Create a new entry if possible. */
if (!info->live_update
|| info->cur.local_count >= STRUCT_EQUIV_MAX_LOCAL)
return false;
info->x_local[info->cur.local_count] = x;
info->y_local[info->cur.local_count] = y;
info->cur.local_count++;
info->cur.version++;
}
note_local_live (info, x, y, rvalue);
}
return true;
}
case SET:
gcc_assert (rvalue < 0);
/* Ignore the destinations role as a destination. Still, we have
to consider input registers embedded in the addresses of a MEM.
N.B., we process the rvalue aspect of STRICT_LOW_PART /
ZERO_EXTEND / SIGN_EXTEND along with their lvalue aspect. */
if(!set_dest_addr_equiv_p (SET_DEST (x), SET_DEST (y), info))
return false;
/* Process source. */
return rtx_equiv_p (&SET_SRC (x), SET_SRC (y), 1, info);
case PRE_MODIFY:
/* Process destination. */
if (!rtx_equiv_p (&XEXP (x, 0), XEXP (y, 0), 0, info))
return false;
/* Process source. */
return rtx_equiv_p (&XEXP (x, 1), XEXP (y, 1), 1, info);
case POST_MODIFY:
{
rtx x_dest0, x_dest1;
/* Process destination. */
x_dest0 = XEXP (x, 0);
gcc_assert (REG_P (x_dest0));
if (!rtx_equiv_p (&XEXP (x, 0), XEXP (y, 0), 0, info))
return false;
x_dest1 = XEXP (x, 0);
/* validate_change might have changed the destination. Put it back
so that we can do a proper match for its role a an input. */
XEXP (x, 0) = x_dest0;
if (!rtx_equiv_p (&XEXP (x, 0), XEXP (y, 0), 1, info))
return false;
gcc_assert (x_dest1 == XEXP (x, 0));
/* Process source. */
return rtx_equiv_p (&XEXP (x, 1), XEXP (y, 1), 1, info);
}
case CLOBBER:
gcc_assert (rvalue < 0);
return true;
/* Some special forms are also rvalues when they appear in lvalue
positions. However, we must ont try to match a register after we
have already altered it with validate_change, consider the rvalue
aspect while we process the lvalue. */
case STRICT_LOW_PART:
case ZERO_EXTEND:
case SIGN_EXTEND:
{
rtx x_inner, y_inner;
enum rtx_code code;
int change;
if (rvalue)
break;
x_inner = XEXP (x, 0);
y_inner = XEXP (y, 0);
if (GET_MODE (x_inner) != GET_MODE (y_inner))
return false;
code = GET_CODE (x_inner);
if (code != GET_CODE (y_inner))
return false;
/* The address of a MEM is an input that will be processed during
rvalue == -1 processing. */
if (code == SUBREG)
{
if (SUBREG_BYTE (x_inner) != SUBREG_BYTE (y_inner))
return false;
x = x_inner;
x_inner = SUBREG_REG (x_inner);
y_inner = SUBREG_REG (y_inner);
if (GET_MODE (x_inner) != GET_MODE (y_inner))
return false;
code = GET_CODE (x_inner);
if (code != GET_CODE (y_inner))
return false;
}
if (code == MEM)
return true;
gcc_assert (code == REG);
if (! rtx_equiv_p (&XEXP (x, 0), y_inner, rvalue, info))
return false;
if (REGNO (x_inner) == REGNO (y_inner))
{
change = assign_reg_reg_set (info->common_live, x_inner, 1);
info->cur.version++;
}
else
change = note_local_live (info, x_inner, y_inner, 1);
gcc_assert (change);
return true;
}
/* The AUTO_INC / POST_MODIFY / PRE_MODIFY sets are modelled to take
place during input processing, however, that is benign, since they
are paired with reads. */
case MEM:
return !rvalue || rtx_equiv_p (&XEXP (x, 0), XEXP (y, 0), rvalue, info);
case POST_INC: case POST_DEC: case PRE_INC: case PRE_DEC:
return (rtx_equiv_p (&XEXP (x, 0), XEXP (y, 0), 0, info)
&& rtx_equiv_p (&XEXP (x, 0), XEXP (y, 0), 1, info));
case PARALLEL:
/* If this is a top-level PATTERN PARALLEL, we expect the caller to
have handled the SET_DESTs. A complex or vector PARALLEL can be
identified by having a mode. */
gcc_assert (rvalue < 0 || GET_MODE (x) != VOIDmode);
break;
case LABEL_REF:
/* Check special tablejump match case. */
if (XEXP (y, 0) == info->y_label)
return (XEXP (x, 0) == info->x_label);
/* We can't assume nonlocal labels have their following insns yet. */
if (LABEL_REF_NONLOCAL_P (x) || LABEL_REF_NONLOCAL_P (y))
return XEXP (x, 0) == XEXP (y, 0);
/* Two label-refs are equivalent if they point at labels
in the same position in the instruction stream. */
return (next_real_insn (XEXP (x, 0))
== next_real_insn (XEXP (y, 0)));
case SYMBOL_REF:
return XSTR (x, 0) == XSTR (y, 0);
/* Some rtl is guaranteed to be shared, or unique; If we didn't match
EQ equality above, they aren't the same. */
case CONST_INT:
case CODE_LABEL:
return false;
default:
break;
}
/* For commutative operations, the RTX match if the operands match in any
order. */
if (targetm.commutative_p (x, UNKNOWN))
return ((rtx_equiv_p (&XEXP (x, 0), XEXP (y, 0), rvalue, info)
&& rtx_equiv_p (&XEXP (x, 1), XEXP (y, 1), rvalue, info))
|| (rtx_equiv_p (&XEXP (x, 0), XEXP (y, 1), rvalue, info)
&& rtx_equiv_p (&XEXP (x, 1), XEXP (y, 0), rvalue, info)));
/* Process subexpressions - this is similar to rtx_equal_p. */
length = GET_RTX_LENGTH (code);
format = GET_RTX_FORMAT (code);
for (i = 0; i < length; ++i)
{
switch (format[i])
{
case 'w':
if (XWINT (x, i) != XWINT (y, i))
return false;
break;
case 'n':
case 'i':
if (XINT (x, i) != XINT (y, i))
return false;
break;
case 'V':
case 'E':
if (XVECLEN (x, i) != XVECLEN (y, i))
return false;
if (XVEC (x, i) != 0)
{
int j;
for (j = 0; j < XVECLEN (x, i); ++j)
{
if (! rtx_equiv_p (&XVECEXP (x, i, j), XVECEXP (y, i, j),
rvalue, info))
return false;
}
}
break;
case 'e':
if (! rtx_equiv_p (&XEXP (x, i), XEXP (y, i), rvalue, info))
return false;
break;
case 'S':
case 's':
if ((XSTR (x, i) || XSTR (y, i))
&& (! XSTR (x, i) || ! XSTR (y, i)
|| strcmp (XSTR (x, i), XSTR (y, i))))
return false;
break;
case 'u':
/* These are just backpointers, so they don't matter. */
break;
case '0':
case 't':
break;
/* It is believed that rtx's at this level will never
contain anything but integers and other rtx's,
except for within LABEL_REFs and SYMBOL_REFs. */
default:
gcc_unreachable ();
}
}
return true;
}
static bool
parse_add_or_inc (rtx insn, bool before_mem)
{
rtx pat = single_set (insn);
if (!pat)
return false;
/* Result must be single reg. */
if (!REG_P (SET_DEST (pat)))
return false;
if ((GET_CODE (SET_SRC (pat)) != PLUS)
&& (GET_CODE (SET_SRC (pat)) != MINUS))
return false;
if (!REG_P (XEXP (SET_SRC (pat), 0)))
return false;
inc_insn.insn = insn;
inc_insn.pat = pat;
inc_insn.reg_res = SET_DEST (pat);
inc_insn.reg0 = XEXP (SET_SRC (pat), 0);
if (rtx_equal_p (inc_insn.reg_res, inc_insn.reg0))
inc_insn.form = before_mem ? FORM_PRE_INC : FORM_POST_INC;
else
inc_insn.form = before_mem ? FORM_PRE_ADD : FORM_POST_ADD;
if (CONST_INT_P (XEXP (SET_SRC (pat), 1)))
{
/* Process a = b + c where c is a const. */
inc_insn.reg1_is_const = true;
if (GET_CODE (SET_SRC (pat)) == PLUS)
{
inc_insn.reg1 = XEXP (SET_SRC (pat), 1);
inc_insn.reg1_val = INTVAL (inc_insn.reg1);
}
else
{
inc_insn.reg1_val = -INTVAL (XEXP (SET_SRC (pat), 1));
inc_insn.reg1 = GEN_INT (inc_insn.reg1_val);
}
return true;
}
else if ((HAVE_PRE_MODIFY_REG || HAVE_POST_MODIFY_REG)
&& (REG_P (XEXP (SET_SRC (pat), 1)))
&& GET_CODE (SET_SRC (pat)) == PLUS)
{
/* Process a = b + c where c is a reg. */
inc_insn.reg1 = XEXP (SET_SRC (pat), 1);
inc_insn.reg1_is_const = false;
if (inc_insn.form == FORM_PRE_INC
|| inc_insn.form == FORM_POST_INC)
return true;
else if (rtx_equal_p (inc_insn.reg_res, inc_insn.reg1))
{
/* Reverse the two operands and turn *_ADD into *_INC since
a = c + a. */
reverse_inc ();
inc_insn.form = before_mem ? FORM_PRE_INC : FORM_POST_INC;
return true;
}
else
return true;
}
return false;
}
static int
load_htab_eq (const void *x, const void *y)
{
return rtx_equal_p (((const struct load *) x)->mem, (const_rtx) y);
}
static int
find_address (rtx *address_of_x)
{
rtx x = *address_of_x;
enum rtx_code code = GET_CODE (x);
const char *const fmt = GET_RTX_FORMAT (code);
int i;
int value = 0;
int tem;
if (code == MEM && rtx_equal_p (XEXP (x, 0), inc_insn.reg_res))
{
/* Match with *reg0. */
mem_insn.mem_loc = address_of_x;
mem_insn.reg0 = inc_insn.reg_res;
mem_insn.reg1_is_const = true;
mem_insn.reg1_val = 0;
mem_insn.reg1 = GEN_INT (0);
return -1;
}
if (code == MEM && GET_CODE (XEXP (x, 0)) == PLUS
&& rtx_equal_p (XEXP (XEXP (x, 0), 0), inc_insn.reg_res))
{
rtx b = XEXP (XEXP (x, 0), 1);
mem_insn.mem_loc = address_of_x;
mem_insn.reg0 = inc_insn.reg_res;
mem_insn.reg1 = b;
mem_insn.reg1_is_const = inc_insn.reg1_is_const;
if (CONST_INT_P (b))
{
/* Match with *(reg0 + reg1) where reg1 is a const. */
HOST_WIDE_INT val = INTVAL (b);
if (inc_insn.reg1_is_const
&& (inc_insn.reg1_val == val || inc_insn.reg1_val == -val))
{
mem_insn.reg1_val = val;
return -1;
}
}
else if (!inc_insn.reg1_is_const
&& rtx_equal_p (inc_insn.reg1, b))
/* Match with *(reg0 + reg1). */
return -1;
}
if (code == SIGN_EXTRACT || code == ZERO_EXTRACT)
{
/* If REG occurs inside a MEM used in a bit-field reference,
that is unacceptable. */
if (find_address (&XEXP (x, 0)))
return 1;
}
if (x == inc_insn.reg_res)
return 1;
/* Time for some deep diving. */
for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
{
if (fmt[i] == 'e')
{
tem = find_address (&XEXP (x, i));
/* If this is the first use, let it go so the rest of the
insn can be checked. */
if (value == 0)
value = tem;
else if (tem != 0)
/* More than one match was found. */
return 1;
}
else if (fmt[i] == 'E')
{
int j;
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
{
tem = find_address (&XVECEXP (x, i, j));
/* If this is the first use, let it go so the rest of
the insn can be checked. */
if (value == 0)
value = tem;
else if (tem != 0)
/* More than one match was found. */
return 1;
}
}
}
return value;
}
const char *
vax_output_int_add (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
enum machine_mode mode)
{
switch (mode)
{
case SImode:
if (rtx_equal_p (operands[0], operands[1]))
{
if (operands[2] == const1_rtx)
return "incl %0";
if (operands[2] == constm1_rtx)
return "decl %0";
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) (- INTVAL (operands[2])) < 64)
return "subl2 $%n2,%0";
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) INTVAL (operands[2]) >= 64
&& GET_CODE (operands[1]) == REG
&& ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
|| REGNO (operands[1]) > 11))
return "movab %c2(%1),%0";
return "addl2 %2,%0";
}
if (rtx_equal_p (operands[0], operands[2]))
return "addl2 %1,%0";
if (GET_CODE (operands[2]) == CONST_INT
&& INTVAL (operands[2]) < 32767
&& INTVAL (operands[2]) > -32768
&& GET_CODE (operands[1]) == REG
&& push_operand (operands[0], SImode))
return "pushab %c2(%1)";
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) (- INTVAL (operands[2])) < 64)
return "subl3 $%n2,%1,%0";
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) INTVAL (operands[2]) >= 64
&& GET_CODE (operands[1]) == REG
&& ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
|| REGNO (operands[1]) > 11))
return "movab %c2(%1),%0";
/* Add this if using gcc on a VAX 3xxx:
if (REG_P (operands[1]) && REG_P (operands[2]))
return "movab (%1)[%2],%0";
*/
return "addl3 %1,%2,%0";
case HImode:
if (rtx_equal_p (operands[0], operands[1]))
{
if (operands[2] == const1_rtx)
return "incw %0";
if (operands[2] == constm1_rtx)
return "decw %0";
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) (- INTVAL (operands[2])) < 64)
return "subw2 $%n2,%0";
return "addw2 %2,%0";
}
if (rtx_equal_p (operands[0], operands[2]))
return "addw2 %1,%0";
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) (- INTVAL (operands[2])) < 64)
return "subw3 $%n2,%1,%0";
return "addw3 %1,%2,%0";
case QImode:
if (rtx_equal_p (operands[0], operands[1]))
{
if (operands[2] == const1_rtx)
return "incb %0";
if (operands[2] == constm1_rtx)
return "decb %0";
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) (- INTVAL (operands[2])) < 64)
return "subb2 $%n2,%0";
return "addb2 %2,%0";
}
if (rtx_equal_p (operands[0], operands[2]))
return "addb2 %1,%0";
if (GET_CODE (operands[2]) == CONST_INT
&& (unsigned) (- INTVAL (operands[2])) < 64)
return "subb3 $%n2,%1,%0";
return "addb3 %1,%2,%0";
default:
gcc_unreachable ();
}
}
