static int s3c_serial_resume(struct platform_device *dev)
{
struct uart_port *port = s3c_dev_to_port(&dev->dev);
struct s3c_uart_port *ourport = to_ourport(port);
if (port) {
clk_enable(ourport->clk);
s3c_serial_resetport(port, s3c_port_to_cfg(port));
clk_disable(ourport->clk);
uart_resume_port(&s3c_uart_drv, port);
}
return 0;
}
static int s3c_serial_resume(struct platform_device *dev)
{
struct uart_port *port = s3c_dev_to_port(&dev->dev);
struct s3c_uart_port *ourport = to_ourport(port);
unsigned int gpadata = 0;
if (port) {
clk_enable(ourport->clk);
s3c_serial_resetport(port, s3c_port_to_cfg(port));
clk_disable(ourport->clk);
s3c6410_pm_do_restore(uart_save + port->line * SAVE_UART_PORT, SAVE_UART_PORT);
uart_resume_port(&s3c_uart_drv, port);
}
if (port->line == 0) {
gpadata = __raw_readl(S3C64XX_GPADAT);
gpadata &= ~(1<<3);
__raw_writel(gpadata, S3C64XX_GPADAT);
} else if(port->line == 1) {
s3c_gpio_cfgpin(S3C64XX_GPA(7), S3C_GPIO_SFN(1));
gpadata = __raw_readl(S3C64XX_GPADAT);
gpadata &= ~(1<<7);
__raw_writel(gpadata, S3C64XX_GPADAT);
s3c_gpio_setpull(S3C64XX_GPA(7), S3C_GPIO_PULL_NONE);
s3c_gpio_cfgpin(S3C64XX_GPA(7), S3C_GPIO_SFN(2));
}
return 0;
}
static int s3c_serial_init_port(struct s3c_uart_port *ourport,
struct s3c_uart_info *info,
struct platform_device *platdev)
{
struct uart_port *port = &ourport->port;
struct s3c_uartcfg *cfg;
struct resource *res;
int ret;
dbg("s3c_serial_init_port: port=%p, platdev=%p\n", port, platdev);
if (platdev == NULL)
return -ENODEV;
cfg = s3c_dev_to_cfg(&platdev->dev);
if (port->mapbase != 0)
return 0;
if (cfg->hwport > CONFIG_SERIAL_SAMSUNG_UARTS) {
printk(KERN_ERR "%s: port %d bigger than %d\n", __func__,
cfg->hwport, CONFIG_SERIAL_SAMSUNG_UARTS);
return -ERANGE;
}
/* setup info for port */
port->dev = &platdev->dev;
ourport->info = info;
/* copy the info in from provided structure */
ourport->port.fifosize = info->fifosize;
dbg("s3c_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
port->uartclk = 1;
if (cfg->uart_flags & UPF_CONS_FLOW) {
dbg("s3c_serial_init_port: enabling flow control\n");
port->flags |= UPF_CONS_FLOW;
}
/* sort our the physical and virtual addresses for each UART */
res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
if (res == NULL) {
printk(KERN_ERR "failed to find memory resource for uart\n");
return -EINVAL;
}
dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
port->mapbase = res->start;
port->membase = S3C_VA_UART + res->start - (S3C_PA_UART & 0xfff00000);
ret = platform_get_irq(platdev, 0);
if (ret < 0)
port->irq = 0;
else {
port->irq = ret;
ourport->rx_irq = ret;
ourport->tx_irq = ret + 1;
}
ret = platform_get_irq(platdev, 1);
if (ret > 0)
ourport->tx_irq = ret;
ourport->clk = clk_get(&platdev->dev, "uart");
dbg("port: map=%08x, mem=%08x, irq=%d (%d,%d), clock=%ld\n",
port->mapbase, port->membase, port->irq,
ourport->rx_irq, ourport->tx_irq, port->uartclk);
/* reset the fifos (and setup the uart) */
s3c_serial_resetport(port, cfg);
s3c_setup_uart_cfg_gpio(cfg->hwport, port);
return 0;
}
static int s3c_serial_init_port(struct s3c_uart_port *ourport,
struct s3c_uart_info *info,
struct platform_device *plat_dev)
{
struct uart_port *port = &ourport->port;
struct s3c2410_uartcfg *cfg;
struct resource *res;
dbg("s3c_serial_init_port: port=%p, plat_dev=%p\n", port, plat_dev);
if (plat_dev == NULL)
return -ENODEV;
cfg = s3c_dev_to_cfg(&plat_dev->dev);
if (port->mapbase != 0)
return 0;
if (cfg->hwport > NR_PORTS)
return -EINVAL;
/*GPIO setup for each port*/
switch(port->line) {
case 0:
gpio_set_pin(S3C_GPA0, S3C_GPA0_UART_RXD0);
gpio_set_pin(S3C_GPA1, S3C_GPA1_UART_TXD0);
gpio_set_pin(S3C_GPA2, S3C_GPA2_UART_CTS0);
gpio_set_pin(S3C_GPA3, S3C_GPA3_UART_RTS0);
break;
case 1:
gpio_set_pin(S3C_GPA4, S3C_GPA4_UART_RXD1);
gpio_set_pin(S3C_GPA5, S3C_GPA5_UART_TXD1);
gpio_set_pin(S3C_GPA5, S3C_GPA6_UART_CTS1);
gpio_set_pin(S3C_GPA7, S3C_GPA7_UART_RTS1);
break;
case 2:
gpio_set_pin(S3C_GPB0, S3C_GPB0_UART_RXD2);
gpio_set_pin(S3C_GPB1, S3C_GPB1_UART_TXD2);
break;
case 3:
gpio_set_pin(S3C_GPB2, S3C_GPB2_UART_RXD3);
gpio_set_pin(S3C_GPB3, S3C_GPB3_UART_TXD3);
break;
default:
break;
}
/* setup info for port */
port->dev = &plat_dev->dev;
ourport->info = info;
/* copy the info in from provided structure */
ourport->port.fifosize = info->fifosize;
dbg("s3c_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
port->uartclk = UART_CLK;
if (cfg->uart_flags & UPF_CONS_FLOW) {
dbg("s3c_serial_init_port: enabling flow control\n");
port->flags |= UPF_CONS_FLOW;
}
/* sort our the physical and virtual addresses for each UART */
res = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
if (res == NULL) {
printk(KERN_ERR "failed to find memory resource for uart\n");
return -EINVAL;
}
dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
port->mapbase = res->start;
port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
port->irq = platform_get_irq(plat_dev, 0);
ourport->clk = clk_get(&plat_dev->dev, "UART0");
dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
port->mapbase, port->membase, port->irq, port->uartclk);
/* reset the fifos (and setup the uart) */
s3c_serial_resetport(port, cfg);
return 0;
}
