void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
{
    unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
    unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
    struct clk *xtal_clk;
    unsigned long xtal;
    unsigned long pll;
    int ptr;

    xtal_clk = clk_get(NULL, "xtal");
    xtal = clk_get_rate(xtal_clk);
    clk_put(xtal_clk);

    pll = get_mpll(mpllcon, xtal);
    clk_msysclk.clk.rate = pll;
    clk_mpll.rate = pll;

    printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
           (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
           print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)),
           print_mhz(clk_get_rate(&clk_h)),
           print_mhz(clk_get_rate(&clk_p)));

    for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
        s3c_set_clksrc(&clksrc_clks[ptr], true);

    /* ensure usb bus clock is within correct rate of 48MHz */

    if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
        printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
        clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
    }

    printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
           (epllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
           print_mhz(clk_get_rate(&clk_epll)),
           print_mhz(clk_get_rate(&clk_usb_bus)));
}
void __init_or_cpufreq s5pv210_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long vpllsrc;
	unsigned long armclk;
	unsigned long hclk_msys;
	unsigned long hclk_dsys;
	unsigned long hclk_psys;
	unsigned long pclk_msys;
	unsigned long pclk_dsys;
	unsigned long pclk_psys;
	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned long vpll;
	unsigned int ptr;
	u32 clkdiv0, clkdiv1;

	/* Set functions for clk_fout_epll */
	clk_fout_epll.enable = s5p_epll_enable;
	clk_fout_epll.ops = &s5pv210_epll_ops;

	clk_fout_vpll.enable = s5pv210_vpll_enable;
	clk_fout_vpll.ops = &s5pv210_vpll_ops;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	clkdiv0 = __raw_readl(S5P_CLK_DIV0);
	clkdiv1 = __raw_readl(S5P_CLK_DIV1);

	printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
				__func__, clkdiv0, clkdiv1);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
	epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
				__raw_readl(S5P_EPLL_CON1), pll_4600);
	vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
	vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);

	clk_fout_apll.ops = &clk_fout_apll_ops;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_vpll.rate = vpll;

	printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
			apll, mpll, epll, vpll);

	armclk = clk_get_rate(&clk_armclk.clk);
	hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
	hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
	hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
	pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
	pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
	pclk_psys = clk_get_rate(&clk_pclk_psys.clk);

	printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
			 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
			armclk, hclk_msys, hclk_dsys, hclk_psys,
			pclk_msys, pclk_dsys, pclk_psys);

	clk_f.rate = armclk;
	clk_h.rate = hclk_psys;
	clk_p.rate = pclk_psys;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}
Beispiel #3
0
void __init_or_cpufreq s5pv310_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned long vpll;
	unsigned long vpllsrc;
	unsigned long xtal;
	unsigned long armclk;
	unsigned long aclk_corem0;
	unsigned long aclk_cores;
	unsigned long aclk_corem1;
	unsigned long periphclk;
	unsigned long sclk_dmc;
	unsigned long aclk_cored;
	unsigned long aclk_corep;
	unsigned long aclk_acp;
	unsigned long pclk_acp;
	unsigned int ptr;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
	epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
				__raw_readl(S5P_EPLL_CON1), pll_4500);

	vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
	vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
				__raw_readl(S5P_VPLL_CON1), pll_4502);

	clk_fout_apll.rate = apll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_vpll.rate = vpll;

	printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
			apll, mpll, epll, vpll);

	armclk = clk_get_rate(&clk_armclk.clk);
	aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
	aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
	aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
	periphclk = clk_get_rate(&clk_periphclk.clk);
	sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
	aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
	aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
	aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
	pclk_acp = clk_get_rate(&clk_pclk_acp.clk);

	printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
			 "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
			 "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
			armclk, aclk_corem0, aclk_cores, aclk_corem1,
			periphclk, sclk_dmc, aclk_cored, aclk_corep,
			aclk_acp, pclk_acp);

	clk_f.rate = armclk;
	clk_h.rate = sclk_dmc;
	clk_p.rate = periphclk;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}
void __init_or_cpufreq exynos5_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long apll;
	unsigned long bpll;
	unsigned long cpll;
	unsigned long mpll;
	unsigned long epll;
	unsigned long vpll;
	unsigned long vpllsrc;
	unsigned long xtal;
	unsigned long armclk;
	unsigned long mout_cdrex;
	unsigned long aclk_400;
	unsigned long aclk_333;
	unsigned long aclk_266;
	unsigned long aclk_200;
	unsigned long aclk_166;
	unsigned long aclk_66;
	unsigned int ptr;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);

	xtal_rate = xtal;

	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
	bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
	cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
	mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
	epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
			__raw_readl(EXYNOS5_EPLL_CON1));

	vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
	vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
			__raw_readl(EXYNOS5_VPLL_CON1));

	clk_fout_apll.ops = &exynos5_fout_apll_ops;
	clk_fout_bpll.rate = bpll;
	clk_fout_cpll.rate = cpll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_vpll.rate = vpll;

	printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
			"M=%ld, E=%ld V=%ld",
			apll, bpll, cpll, mpll, epll, vpll);

	armclk = clk_get_rate(&exynos5_clk_armclk);
	mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);

	aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
	aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
	aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
	aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
	aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
	aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);

	printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
			"ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
			"ACLK166=%ld, ACLK66=%ld\n",
			armclk, mout_cdrex, aclk_400,
			aclk_333, aclk_266, aclk_200,
			aclk_166, aclk_66);


	clk_fout_epll.ops = &exynos5_epll_ops;

	if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
		printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
				clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);

	clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
	clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);

	clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
	clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);

	for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
		s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
}
void __init_or_cpufreq s5pv210_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long vpllsrc;
	unsigned long armclk;
	unsigned long hclk_msys;
	unsigned long hclk_dsys;
	unsigned long hclk_psys;
	unsigned long pclk_msys;
	unsigned long pclk_dsys;
	unsigned long pclk_psys;
	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned long vpll;
	unsigned int ptr;
	u32 clkdiv0, clkdiv1;
	struct clksrc_clk *pclkSrc;

	/* Set functions for clk_fout_epll */
	clk_fout_epll.enable = s5p_epll_enable;
	clk_fout_epll.ops = &s5pv210_epll_ops;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	clkdiv0 = __raw_readl(S5P_CLK_DIV0);
	clkdiv1 = __raw_readl(S5P_CLK_DIV1);

	printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
				__func__, clkdiv0, clkdiv1);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
	epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
				__raw_readl(S5P_EPLL_CON1), pll_4600);
	vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
	vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);

	clk_fout_apll.ops = &clk_fout_apll_ops;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_vpll.rate = vpll;

	printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
			apll, mpll, epll, vpll);

	armclk = clk_get_rate(&clk_armclk.clk);
	hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
	hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
	hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
	pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
	pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
	pclk_psys = clk_get_rate(&clk_pclk_psys.clk);

	printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
			 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
			armclk, hclk_msys, hclk_dsys, hclk_psys,
			pclk_msys, pclk_dsys, pclk_psys);

	clk_f.rate = armclk;
	clk_h.rate = hclk_psys;
	clk_p.rate = pclk_psys;

	/*Assign clock source and rates for IP's*/
	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) {
		pclkSrc = &clksrcs[ptr];
		if (!strcmp(pclkSrc->clk.name, "sclk_mdnie")) {
			clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk);
			clk_set_rate(&pclkSrc->clk, 167*MHZ);
		} else if (!strcmp(pclkSrc->clk.name, "sclk_mmc")) {
			clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk);

			if (pclkSrc->clk.id == 0)
				clk_set_rate(&pclkSrc->clk, 52*MHZ);
			else
				clk_set_rate(&pclkSrc->clk, 50*MHZ);
		} else if (!strcmp(pclkSrc->clk.name, "sclk_spi")) {
			clk_set_parent(&pclkSrc->clk, &clk_mout_epll.clk);
		} else if (!strcmp(pclkSrc->clk.name, "sclk_cam") &&
			   (pclkSrc->clk.id == 0)) {
			clk_set_parent(&pclkSrc->clk, &clk_xusbxti);
		} else if (!strcmp(pclkSrc->clk.name, "sclk_g2d")) {
			clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk);
			clk_set_rate(&pclkSrc->clk, 250*MHZ);
		} else if (!strcmp(pclkSrc->clk.name, "sclk")) {
			clk_set_parent(&pclkSrc->clk, &clk_mout_mpll.clk);

			if (pclkSrc->clk.id == 0)
				clk_set_rate(&pclkSrc->clk, 133400000);
			else
				clk_set_rate(&pclkSrc->clk, 66700000);
		}
		/* Display the clock source */
		s3c_set_clksrc(pclkSrc, true);
	}
}
Beispiel #6
0
void __init_or_cpufreq exynos4_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long apll = 0;
	unsigned long mpll = 0;
	unsigned long epll = 0;
	unsigned long vpll = 0;
	unsigned long vpllsrc;
	unsigned long xtal;
	unsigned long armclk;
	unsigned long sclk_dmc;
	unsigned long aclk_200;
	unsigned long aclk_100;
	unsigned long aclk_160;
	unsigned long aclk_133;
	unsigned int ptr;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);

	xtal_rate = xtal;

	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	if (soc_is_exynos4210()) {
		apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
					pll_4508);
		mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
					pll_4508);
		epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
					__raw_readl(S5P_EPLL_CON1), pll_4600);

		vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
		vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
					__raw_readl(S5P_VPLL_CON1), pll_4650c);
	} else if (soc_is_exynos4212() || soc_is_exynos4412()) {
		apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
		mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
		epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
					__raw_readl(S5P_EPLL_CON1));

		vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
		vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
					__raw_readl(S5P_VPLL_CON1));
	} else {
		/* nothing */
	}

	clk_fout_apll.ops = &exynos4_fout_apll_ops;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_vpll.ops = &exynos4_vpll_ops;
	clk_fout_vpll.rate = vpll;

	printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
			apll, mpll, epll, vpll);

	armclk = clk_get_rate(&clk_armclk.clk);
	sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);

	aclk_200 = clk_get_rate(&clk_aclk_200.clk);
	aclk_100 = clk_get_rate(&clk_aclk_100.clk);
	aclk_160 = clk_get_rate(&clk_aclk_160.clk);
	aclk_133 = clk_get_rate(&clk_aclk_133.clk);

	printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
			 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
			armclk, sclk_dmc, aclk_200,
			aclk_100, aclk_160, aclk_133);

	clk_f.rate = armclk;
	clk_h.rate = sclk_dmc;
	clk_p.rate = aclk_100;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}
void __init_or_cpufreq s5p6442_setup_clocks(void)
{
	struct clk *pclkd0_clk;
	struct clk *pclkd1_clk;

	unsigned long xtal;
	unsigned long arm;
	unsigned long hclkd0 = 0;
	unsigned long hclkd1 = 0;
	unsigned long pclkd0 = 0;
	unsigned long pclkd1 = 0;

	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned int ptr;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	xtal = clk_get_rate(&clk_xtal);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
	epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);

	printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld",
			apll, mpll, epll);

	clk_fout_apll.rate = apll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;

	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
		s3c_set_clksrc(init_parents[ptr], true);

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);

	arm = clk_get_rate(&clk_dout_apll);
	hclkd0 = clk_get_rate(&clk_hclkd0);
	hclkd1 = clk_get_rate(&clk_hclkd1);

	pclkd0_clk = clk_get(NULL, "pclkd0");
	BUG_ON(IS_ERR(pclkd0_clk));

	pclkd0 = clk_get_rate(pclkd0_clk);
	clk_put(pclkd0_clk);

	pclkd1_clk = clk_get(NULL, "pclkd1");
	BUG_ON(IS_ERR(pclkd1_clk));

	pclkd1 = clk_get_rate(pclkd1_clk);
	clk_put(pclkd1_clk);

	printk(KERN_INFO "S5P6442: HCLKD0=%ld, HCLKD1=%ld, PCLKD0=%ld, PCLKD1=%ld\n",
			hclkd0, hclkd1, pclkd0, pclkd1);

	/* For backward compatibility */
	clk_f.rate = arm;
	clk_h.rate = hclkd1;
	clk_p.rate = pclkd1;

	clk_pclkd0.rate = pclkd0;
	clk_pclkd1.rate = pclkd1;
}
Beispiel #8
0
void __init_or_cpufreq s5p6450_setup_clocks(void)
{
	struct clk *xtal_clk;

	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long hclk_low;
	unsigned long pclk;
	unsigned long pclk_low;

	unsigned long apll;
	unsigned long mpll;
	unsigned long epll;
	unsigned long dpll;
	unsigned int ptr;

	/* Set S5P6450 functions for clk_fout_epll */

	clk_fout_epll.enable = s5p_epll_enable;
	clk_fout_epll.ops = &s5p6450_epll_ops;

	clk_48m.enable = s5p64x0_clk48m_ctrl;

	xtal_clk = clk_get(NULL, "ext_xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
	epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
				__raw_readl(S5P64X0_EPLL_CON_K));
	dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
				__raw_readl(S5P6450_DPLL_CON_K), pll_4650c);

	clk_fout_apll.rate = apll;
	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_dpll.rate = dpll;

	printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
			" E=%ld.%ldMHz, D=%ld.%ldMHz\n",
			print_mhz(apll), print_mhz(mpll), print_mhz(epll),
			print_mhz(dpll));

	fclk = clk_get_rate(&clk_armclk.clk);
	hclk = clk_get_rate(&clk_hclk.clk);
	pclk = clk_get_rate(&clk_pclk.clk);
	hclk_low = clk_get_rate(&clk_hclk_low.clk);
	pclk_low = clk_get_rate(&clk_pclk_low.clk);

	printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
			" PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
			print_mhz(hclk), print_mhz(hclk_low),
			print_mhz(pclk), print_mhz(pclk_low));

	clk_f.rate = fclk;
	clk_h.rate = hclk;
	clk_p.rate = pclk;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}
Beispiel #9
0
void __init_or_cpufreq s3c6400_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long hclk2;
	unsigned long pclk;
	unsigned long epll;
	unsigned long apll;
	unsigned long mpll;
	unsigned int ptr;
	u32 clkdiv0;

	printk(KERN_DEBUG "%s: registering clocks\n", __func__);

	clkdiv0 = __raw_readl(S3C_CLK_DIV0);
	printk(KERN_DEBUG "%s: clkdiv0 = %08x\n", __func__, clkdiv0);

	xtal_clk = clk_get(NULL, "xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);

	/* For now assume the mux always selects the crystal */
	clk_ext_xtal_mux.parent = xtal_clk;

	epll = s3c6400_get_epll(xtal);
	mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
	apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));

	fclk = mpll;

	printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
	       apll, mpll, epll);

	if(__raw_readl(S3C64XX_OTHERS) & S3C64XX_OTHERS_SYNCMUXSEL_SYNC) {
		/* Synchronous mode */
		hclk2 = apll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
	} else {
		/* Asynchronous mode */
		hclk2 = mpll / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK2);
	}

	hclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_HCLK);
	pclk = hclk2 / GET_DIV(clkdiv0, S3C6400_CLKDIV0_PCLK);

	printk(KERN_INFO "S3C64XX: HCLK2=%ld, HCLK=%ld, PCLK=%ld\n",
	       hclk2, hclk, pclk);

	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_apll.rate = apll;

	clk_h2.rate = hclk2;
	clk_h.rate = hclk;
	clk_p.rate = pclk;
	clk_f.rate = fclk;

	for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
		s3c_set_clksrc(init_parents[ptr], true);

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}
Beispiel #10
0
void __init_or_cpufreq s5p6450_setup_clocks(void)
{
	struct clk *xtal_clk;
	unsigned long xtal;
	unsigned long fclk;
	unsigned long hclk;
	unsigned long hclk_low;
	unsigned long pclk;
	unsigned long pclk_low;
	unsigned long epll;
	unsigned long dpll;
	unsigned long apll;
	unsigned long mpll;
	unsigned int ptr;
	
	/* Set S5P6450 functions for clk_fout_epll */
	clk_fout_epll.enable = s5p6450_epll_enable;
	clk_fout_epll.ops = &s5p6450_epll_ops;

	clk_48m.enable = s5p6450_clk48m_ctrl;

	xtal_clk = clk_get(NULL, "ext_xtal");
	BUG_ON(IS_ERR(xtal_clk));

	xtal = clk_get_rate(xtal_clk);
	clk_put(xtal_clk);

	epll = s5p_get_pll90xx(xtal, __raw_readl(S5P_EPLL_CON),
				__raw_readl(S5P_EPLL_CON_K));
	dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P_DPLL_CON),
				__raw_readl(S5P_DPLL_CON_K), pll_4650c);
	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4502);

	clk_fout_mpll.rate = mpll;
	clk_fout_epll.rate = epll;
	clk_fout_dpll.rate = dpll;
	clk_fout_apll.rate = apll;
	
	ctable.apll_rate = clk_fout_apll.rate/1000000;
	
	switch (ctable.apll_rate)
	{
		case IS_ARM_800 :
	                ctable.clock_table_size = ARRAY_SIZE(clock_table_800);
        	        ctable.clock_table = clock_table_800;
			break;
		case IS_ARM_667:
	                ctable.clock_table_size = ARRAY_SIZE(clock_table_667);
        	        ctable.clock_table = clock_table_667;

			break;
		case IS_ARM_533:
                	ctable.clock_table_size = ARRAY_SIZE(clock_table_533);
	                ctable.clock_table = clock_table_533;

			break;
		default:
	  		printk("------------------------- UNKNOW FREQ   WARNING !!!!!!!!!---------------  e   \n");
	
	}
/*
	if(ctable.apll_rate == IS_ARM_667){
		printk("-----------------------------------------  667 Freq table   \n");
		ctable.clock_table_size = ARRAY_SIZE(clock_table_667);
		ctable.clock_table = clock_table_667;
	}else if(ctable.apll_rate == IS_ARM_533) 
	{
		printk("-----------------------------------------  533 Freq table   \n");
		ctable.clock_table_size = ARRAY_SIZE(clock_table_533);
		ctable.clock_table = clock_table_533;	
	}

*/
	printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
			" E=%ld.%ldMHz, D=%ld.%ldMHz\n",
			print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(dpll));

	fclk = clk_get_rate(&clk_armclk.clk);
	hclk = clk_get_rate(&clk_hclk166.clk);
	pclk = clk_get_rate(&clk_pclk83.clk);
	hclk_low = clk_get_rate(&clk_hclk133.clk);
	pclk_low = clk_get_rate(&clk_pclk66.clk);

	printk(KERN_INFO "S5P6450: HCLK166=%ld.%ldMHz, HCLK133=%ld.%ldMHz," \
			" PCLK83=%ld.%ldMHz, PCLK66=%ld.%ldMHz\n",
			print_mhz(hclk), print_mhz(hclk_low),
			print_mhz(pclk), print_mhz(pclk_low));

	clk_f.rate = fclk;
	clk_h.rate = hclk;
	clk_p.rate = pclk;
	clk_h_low.rate = hclk_low;

	for (ptr = 0; ptr < ARRAY_SIZE(clksrc_audio); ptr++)
		s3c_set_clksrc(clksrc_audio + ptr, true);

	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
		s3c_set_clksrc(&clksrcs[ptr], true);
}