/* register exynos5410 clocks */
static void __init exynos5410_clk_init(struct device_node *np)
{
	struct samsung_clk_provider *ctx;
	void __iomem *reg_base;

	reg_base = of_iomap(np, 0);
	if (!reg_base)
		panic("%s: failed to map registers\n", __func__);

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);

	samsung_clk_register_pll(ctx, exynos5410_plls,
			ARRAY_SIZE(exynos5410_plls), reg_base);

	samsung_clk_register_mux(ctx, exynos5410_mux_clks,
			ARRAY_SIZE(exynos5410_mux_clks));
	samsung_clk_register_div(ctx, exynos5410_div_clks,
			ARRAY_SIZE(exynos5410_div_clks));
	samsung_clk_register_gate(ctx, exynos5410_gate_clks,
			ARRAY_SIZE(exynos5410_gate_clks));

	samsung_clk_of_add_provider(np, ctx);

	pr_debug("Exynos5410: clock setup completed.\n");
}
Beispiel #2
0
static void __init exynos3250_cmu_dmc_init(struct device_node *np)
{
	struct samsung_clk_provider *ctx;

	dmc_reg_base = of_iomap(np, 0);
	if (!dmc_reg_base)
		panic("%s: failed to map registers\n", __func__);

	ctx = samsung_clk_init(np, dmc_reg_base, NR_CLKS_DMC);
	if (!ctx)
		panic("%s: unable to allocate context.\n", __func__);

	exynos3250_dmc_plls[bpll].rate_table = exynos3250_pll_rates;
	exynos3250_dmc_plls[epll].rate_table = exynos3250_epll_rates;

	pr_err("CLK registering epll bpll: %d, %d, %d, %d\n",
			exynos3250_dmc_plls[bpll].rate_table[0].rate,
			exynos3250_dmc_plls[bpll].rate_table[0].mdiv,
			exynos3250_dmc_plls[bpll].rate_table[0].pdiv,
			exynos3250_dmc_plls[bpll].rate_table[0].sdiv
	      );
	samsung_clk_register_pll(ctx, exynos3250_dmc_plls,
				ARRAY_SIZE(exynos3250_dmc_plls), dmc_reg_base);

	samsung_clk_register_mux(ctx, dmc_mux_clks, ARRAY_SIZE(dmc_mux_clks));
	samsung_clk_register_div(ctx, dmc_div_clks, ARRAY_SIZE(dmc_div_clks));

	exynos3250_dmc_clk_sleep_init();

	samsung_clk_of_add_provider(np, ctx);
}
Beispiel #3
0
static void __init exynos3250_cmu_init(struct device_node *np)
{
	struct samsung_clk_provider *ctx;

	reg_base = of_iomap(np, 0);
	if (!reg_base)
		panic("%s: failed to map registers\n", __func__);

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
	if (!ctx)
		panic("%s: unable to allocate context.\n", __func__);

	samsung_clk_register_fixed_factor(ctx, fixed_factor_clks,
					  ARRAY_SIZE(fixed_factor_clks));

	exynos3250_plls[apll].rate_table = exynos3250_pll_rates;
	exynos3250_plls[mpll].rate_table = exynos3250_pll_rates;
	exynos3250_plls[vpll].rate_table = exynos3250_vpll_rates;
	exynos3250_plls[upll].rate_table = exynos3250_pll_rates;

	samsung_clk_register_pll(ctx, exynos3250_plls,
					ARRAY_SIZE(exynos3250_plls), reg_base);

	samsung_clk_register_mux(ctx, mux_clks, ARRAY_SIZE(mux_clks));
	samsung_clk_register_div(ctx, div_clks, ARRAY_SIZE(div_clks));
	samsung_clk_register_gate(ctx, gate_clks, ARRAY_SIZE(gate_clks));

	exynos3_core_down_clock();

	exynos3250_clk_sleep_init();

	samsung_clk_of_add_provider(np, ctx);
}
static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
{
	struct samsung_clk_provider *ctx;
	struct device *dev = &pdev->dev;
	struct device_node *np = dev->of_node;
	struct resource *res;
	void __iomem *reg_base;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	reg_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(reg_base)) {
		dev_err(dev, "failed to map registers\n");
		return PTR_ERR(reg_base);
	}

	exynos4x12_save_isp = samsung_clk_alloc_reg_dump(exynos4x12_clk_isp_save,
					ARRAY_SIZE(exynos4x12_clk_isp_save));
	if (!exynos4x12_save_isp)
		return -ENOMEM;

	ctx = samsung_clk_init(np, reg_base, CLK_NR_ISP_CLKS);
	ctx->dev = dev;

	platform_set_drvdata(pdev, ctx);

	pm_runtime_set_active(dev);
	pm_runtime_enable(dev);
	pm_runtime_get_sync(dev);

	samsung_clk_register_div(ctx, exynos4x12_isp_div_clks,
				 ARRAY_SIZE(exynos4x12_isp_div_clks));
	samsung_clk_register_gate(ctx, exynos4x12_isp_gate_clks,
				  ARRAY_SIZE(exynos4x12_isp_gate_clks));

	samsung_clk_of_add_provider(np, ctx);
	pm_runtime_put(dev);

	return 0;
}
/* register exynos5440 clocks */
static void __init exynos5440_clk_init(struct device_node *np)
{
	void __iomem *reg_base;
	struct samsung_clk_provider *ctx;

	reg_base = of_iomap(np, 0);
	if (!reg_base) {
		pr_err("%s: failed to map clock controller registers,"
			" aborting clock initialization\n", __func__);
		return;
	}

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
	if (!ctx)
		panic("%s: unable to allocate context.\n", __func__);

	samsung_clk_of_register_fixed_ext(ctx, exynos5440_fixed_rate_ext_clks,
		ARRAY_SIZE(exynos5440_fixed_rate_ext_clks), ext_clk_match);

	samsung_clk_register_pll2550x("cplla", "xtal", reg_base + 0x1c, 0x10);
	samsung_clk_register_pll2550x("cpllb", "xtal", reg_base + 0x20, 0x10);

	samsung_clk_register_fixed_rate(ctx, exynos5440_fixed_rate_clks,
			ARRAY_SIZE(exynos5440_fixed_rate_clks));
	samsung_clk_register_fixed_factor(ctx, exynos5440_fixed_factor_clks,
			ARRAY_SIZE(exynos5440_fixed_factor_clks));
	samsung_clk_register_mux(ctx, exynos5440_mux_clks,
			ARRAY_SIZE(exynos5440_mux_clks));
	samsung_clk_register_div(ctx, exynos5440_div_clks,
			ARRAY_SIZE(exynos5440_div_clks));
	samsung_clk_register_gate(ctx, exynos5440_gate_clks,
			ARRAY_SIZE(exynos5440_gate_clks));

	samsung_clk_of_add_provider(np, ctx);

	pr_info("Exynos5440: arm_clk = %ldHz\n", _get_rate("arm_clk"));
	pr_info("exynos5440 clock initialization complete\n");
}
Beispiel #6
0
void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
				    int current_soc,
				    void __iomem *base)
{
	struct samsung_clk_provider *ctx;
	reg_base = base;

	if (np) {
		reg_base = of_iomap(np, 0);
		if (!reg_base)
			panic("%s: failed to map registers\n", __func__);
	}

	ctx = samsung_clk_init(np, reg_base, NR_CLKS);

	/* Register external clocks only in non-dt cases */
	if (!np)
		s3c2410_common_clk_register_fixed_ext(ctx, xti_f);

	if (current_soc == S3C2410) {
		if (_get_rate("xti") == 12 * MHZ) {
			s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
			s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
		}

		/* Register PLLs. */
		samsung_clk_register_pll(ctx, s3c2410_plls,
				ARRAY_SIZE(s3c2410_plls), reg_base);

	} else { /* S3C2440, S3C2442 */
		if (_get_rate("xti") == 12 * MHZ) {
			/*
			 * plls follow different calculation schemes, with the
			 * upll following the same scheme as the s3c2410 plls
			 */
			s3c244x_common_plls[mpll].rate_table =
							pll_s3c244x_12mhz_tbl;
			s3c244x_common_plls[upll].rate_table =
							pll_s3c2410_12mhz_tbl;
		}

		/* Register PLLs. */
		samsung_clk_register_pll(ctx, s3c244x_common_plls,
				ARRAY_SIZE(s3c244x_common_plls), reg_base);
	}

	/* Register common internal clocks. */
	samsung_clk_register_mux(ctx, s3c2410_common_muxes,
			ARRAY_SIZE(s3c2410_common_muxes));
	samsung_clk_register_div(ctx, s3c2410_common_dividers,
			ARRAY_SIZE(s3c2410_common_dividers));
	samsung_clk_register_gate(ctx, s3c2410_common_gates,
		ARRAY_SIZE(s3c2410_common_gates));

	if (current_soc == S3C2440 || current_soc == S3C2442) {
		samsung_clk_register_div(ctx, s3c244x_common_dividers,
				ARRAY_SIZE(s3c244x_common_dividers));
		samsung_clk_register_gate(ctx, s3c244x_common_gates,
				ARRAY_SIZE(s3c244x_common_gates));
		samsung_clk_register_mux(ctx, s3c244x_common_muxes,
				ARRAY_SIZE(s3c244x_common_muxes));
		samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
				ARRAY_SIZE(s3c244x_common_ffactor));
	}

	/* Register SoC-specific clocks. */
	switch (current_soc) {
	case S3C2410:
		samsung_clk_register_div(ctx, s3c2410_dividers,
				ARRAY_SIZE(s3c2410_dividers));
		samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
				ARRAY_SIZE(s3c2410_ffactor));
		samsung_clk_register_alias(ctx, s3c2410_aliases,
			ARRAY_SIZE(s3c2410_aliases));
		break;
	case S3C2440:
		samsung_clk_register_mux(ctx, s3c2440_muxes,
				ARRAY_SIZE(s3c2440_muxes));
		samsung_clk_register_gate(ctx, s3c2440_gates,
				ARRAY_SIZE(s3c2440_gates));
		break;
	case S3C2442:
		samsung_clk_register_mux(ctx, s3c2442_muxes,
				ARRAY_SIZE(s3c2442_muxes));
		samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
				ARRAY_SIZE(s3c2442_ffactor));
		break;
	}

	/*
	 * Register common aliases at the end, as some of the aliased clocks
	 * are SoC specific.
	 */
	samsung_clk_register_alias(ctx, s3c2410_common_aliases,
		ARRAY_SIZE(s3c2410_common_aliases));

	if (current_soc == S3C2440 || current_soc == S3C2442) {
		samsung_clk_register_alias(ctx, s3c244x_common_aliases,
			ARRAY_SIZE(s3c244x_common_aliases));
	}

	samsung_clk_sleep_init(reg_base, s3c2410_clk_regs,
			       ARRAY_SIZE(s3c2410_clk_regs));

	samsung_clk_of_add_provider(np, ctx);
}
Beispiel #7
0
/* register exynox5250 clocks */
static void __init exynos5250_clk_init(struct device_node *np)
{
	struct samsung_clk_provider *ctx;
	unsigned int tmp;

	if (np) {
		reg_base = of_iomap(np, 0);
		if (!reg_base)
			panic("%s: failed to map registers\n", __func__);
	} else {
		panic("%s: unable to determine soc\n", __func__);
	}

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
	if (!ctx)
		panic("%s: unable to allocate context.\n", __func__);
	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
			ARRAY_SIZE(exynos5250_fixed_rate_ext_clks),
			ext_clk_match);
	samsung_clk_register_mux(ctx, exynos5250_pll_pmux_clks,
				ARRAY_SIZE(exynos5250_pll_pmux_clks));

	if (_get_rate("fin_pll") == 24 * MHZ) {
		exynos5250_plls[epll].rate_table = epll_24mhz_tbl;
		exynos5250_plls[apll].rate_table = apll_24mhz_tbl;
	}

	if (_get_rate("mout_vpllsrc") == 24 * MHZ)
		exynos5250_plls[vpll].rate_table =  vpll_24mhz_tbl;

	samsung_clk_register_pll(ctx, exynos5250_plls,
			ARRAY_SIZE(exynos5250_plls),
			reg_base);
	samsung_clk_register_fixed_rate(ctx, exynos5250_fixed_rate_clks,
			ARRAY_SIZE(exynos5250_fixed_rate_clks));
	samsung_clk_register_fixed_factor(ctx, exynos5250_fixed_factor_clks,
			ARRAY_SIZE(exynos5250_fixed_factor_clks));
	samsung_clk_register_mux(ctx, exynos5250_mux_clks,
			ARRAY_SIZE(exynos5250_mux_clks));
	samsung_clk_register_div(ctx, exynos5250_div_clks,
			ARRAY_SIZE(exynos5250_div_clks));
	samsung_clk_register_gate(ctx, exynos5250_gate_clks,
			ARRAY_SIZE(exynos5250_gate_clks));
	exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
			mout_cpu_p[0], mout_cpu_p[1], 0x200,
			exynos5250_armclk_d, ARRAY_SIZE(exynos5250_armclk_d),
			CLK_CPU_HAS_DIV1);

	/*
	 * Enable arm clock down (in idle) and set arm divider
	 * ratios in WFI/WFE state.
	 */
	tmp = (PWR_CTRL1_CORE2_DOWN_RATIO | PWR_CTRL1_CORE1_DOWN_RATIO |
		PWR_CTRL1_DIV2_DOWN_EN | PWR_CTRL1_DIV1_DOWN_EN |
		PWR_CTRL1_USE_CORE1_WFE | PWR_CTRL1_USE_CORE0_WFE |
		PWR_CTRL1_USE_CORE1_WFI | PWR_CTRL1_USE_CORE0_WFI);
	__raw_writel(tmp, reg_base + PWR_CTRL1);

	/*
	 * Enable arm clock up (on exiting idle). Set arm divider
	 * ratios when not in idle along with the standby duration
	 * ratios.
	 */
	tmp = (PWR_CTRL2_DIV2_UP_EN | PWR_CTRL2_DIV1_UP_EN |
		PWR_CTRL2_DUR_STANDBY2_VAL | PWR_CTRL2_DUR_STANDBY1_VAL |
		PWR_CTRL2_CORE2_UP_RATIO | PWR_CTRL2_CORE1_UP_RATIO);
	__raw_writel(tmp, reg_base + PWR_CTRL2);

	exynos5250_clk_sleep_init();

	samsung_clk_of_add_provider(np, ctx);

	pr_info("Exynos5250: clock setup completed, armclk=%ld\n",
			_get_rate("div_arm2"));
}
/* Register s3c64xx clocks. */
void __init s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
			     unsigned long xusbxti_f, bool s3c6400,
			     void __iomem *base)
{
	struct samsung_clk_provider *ctx;

	reg_base = base;
	is_s3c6400 = s3c6400;

	if (np) {
		reg_base = of_iomap(np, 0);
		if (!reg_base)
			panic("%s: failed to map registers\n", __func__);
	}

	ctx = samsung_clk_init(np, reg_base, NR_CLKS);
	if (!ctx)
		panic("%s: unable to allocate context.\n", __func__);

	/* Register external clocks. */
	if (!np)
		s3c64xx_clk_register_fixed_ext(ctx, xtal_f, xusbxti_f);

	/* Register PLLs. */
	samsung_clk_register_pll(ctx, s3c64xx_pll_clks,
				ARRAY_SIZE(s3c64xx_pll_clks), reg_base);

	/* Register common internal clocks. */
	samsung_clk_register_fixed_rate(ctx, s3c64xx_fixed_rate_clks,
					ARRAY_SIZE(s3c64xx_fixed_rate_clks));
	samsung_clk_register_mux(ctx, s3c64xx_mux_clks,
					ARRAY_SIZE(s3c64xx_mux_clks));
	samsung_clk_register_div(ctx, s3c64xx_div_clks,
					ARRAY_SIZE(s3c64xx_div_clks));
	samsung_clk_register_gate(ctx, s3c64xx_gate_clks,
					ARRAY_SIZE(s3c64xx_gate_clks));

	/* Register SoC-specific clocks. */
	if (is_s3c6400) {
		samsung_clk_register_mux(ctx, s3c6400_mux_clks,
					ARRAY_SIZE(s3c6400_mux_clks));
		samsung_clk_register_div(ctx, s3c6400_div_clks,
					ARRAY_SIZE(s3c6400_div_clks));
		samsung_clk_register_gate(ctx, s3c6400_gate_clks,
					ARRAY_SIZE(s3c6400_gate_clks));
		samsung_clk_register_alias(ctx, s3c6400_clock_aliases,
					ARRAY_SIZE(s3c6400_clock_aliases));
	} else {
		samsung_clk_register_mux(ctx, s3c6410_mux_clks,
					ARRAY_SIZE(s3c6410_mux_clks));
		samsung_clk_register_div(ctx, s3c6410_div_clks,
					ARRAY_SIZE(s3c6410_div_clks));
		samsung_clk_register_gate(ctx, s3c6410_gate_clks,
					ARRAY_SIZE(s3c6410_gate_clks));
		samsung_clk_register_alias(ctx, s3c6410_clock_aliases,
					ARRAY_SIZE(s3c6410_clock_aliases));
	}

	samsung_clk_register_alias(ctx, s3c64xx_clock_aliases,
					ARRAY_SIZE(s3c64xx_clock_aliases));
	s3c64xx_clk_sleep_init();

	samsung_clk_of_add_provider(np, ctx);

	pr_info("%s clocks: apll = %lu, mpll = %lu\n"
		"\tepll = %lu, arm_clk = %lu\n",
		is_s3c6400 ? "S3C6400" : "S3C6410",
		_get_rate("fout_apll"),	_get_rate("fout_mpll"),
		_get_rate("fout_epll"), _get_rate("armclk"));
}
/* register exynos5420 clocks */
static void __init exynos5x_clk_init(struct device_node *np,
		enum exynos5x_soc soc)
{
	struct samsung_clk_provider *ctx;

	if (np) {
		reg_base = of_iomap(np, 0);
		if (!reg_base)
			panic("%s: failed to map registers\n", __func__);
	} else {
		panic("%s: unable to determine soc\n", __func__);
	}

	exynos5x_soc = soc;

	ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
	if (!ctx)
		panic("%s: unable to allocate context.\n", __func__);

	samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
			ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
			ext_clk_match);

	if (_get_rate("fin_pll") == 24 * MHZ) {
		exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
		exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
	}

	samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
					reg_base);
	samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
			ARRAY_SIZE(exynos5x_fixed_rate_clks));
	samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
			ARRAY_SIZE(exynos5x_fixed_factor_clks));
	samsung_clk_register_mux(ctx, exynos5x_mux_clks,
			ARRAY_SIZE(exynos5x_mux_clks));
	samsung_clk_register_div(ctx, exynos5x_div_clks,
			ARRAY_SIZE(exynos5x_div_clks));
	samsung_clk_register_gate(ctx, exynos5x_gate_clks,
			ARRAY_SIZE(exynos5x_gate_clks));

	if (soc == EXYNOS5420) {
		samsung_clk_register_mux(ctx, exynos5420_mux_clks,
				ARRAY_SIZE(exynos5420_mux_clks));
		samsung_clk_register_div(ctx, exynos5420_div_clks,
				ARRAY_SIZE(exynos5420_div_clks));
	} else {
		samsung_clk_register_fixed_factor(
				ctx, exynos5800_fixed_factor_clks,
				ARRAY_SIZE(exynos5800_fixed_factor_clks));
		samsung_clk_register_mux(ctx, exynos5800_mux_clks,
				ARRAY_SIZE(exynos5800_mux_clks));
		samsung_clk_register_div(ctx, exynos5800_div_clks,
				ARRAY_SIZE(exynos5800_div_clks));
		samsung_clk_register_gate(ctx, exynos5800_gate_clks,
				ARRAY_SIZE(exynos5800_gate_clks));
	}

	exynos5420_clk_sleep_init();

	samsung_clk_of_add_provider(np, ctx);
}