/* * omap4_sar_save - * Save the context to SAR_RAM1 and SAR_RAM2 as per * sar_ram1_layout and sar_ram2_layout for the device OFF mode */ void omap4_sar_save(void) { /* * Not supported on ES1.0 silicon */ if (omap_rev() == OMAP4430_REV_ES1_0) { WARN_ONCE(1, "omap4: SAR backup not supported on ES1.0 ..\n"); return; } /* * SAR bits and clocks needs to be enabled */ pwrdm_enable_hdwr_sar(l3init_pwrdm); clk_enable(usb_host_ck); clk_enable(usb_tll_ck); /* Save SAR BANK1 */ sar_save(NB_REGS_CONST_SETS_RAM1_HW, SAR_BANK1_OFFSET, sar_ram1_layout); pwrdm_disable_hdwr_sar(l3init_pwrdm); clk_disable(usb_host_ck); clk_disable(usb_tll_ck); /* Save SAR BANK2 */ sar_save(NB_REGS_CONST_SETS_RAM2_HW, SAR_BANK2_OFFSET, sar_ram2_layout); }
/* * omap4_sar_save - * Save the context to SAR_RAM1 and SAR_RAM2 as per * omap4xxx_sar_ram1_layout and omap4xxx_sar_ram2_layout for the device OFF * mode */ int omap4_sar_save(void) { /* * Not supported on ES1.0 silicon */ if (omap_rev() == OMAP4430_REV_ES1_0) { WARN_ONCE(1, "omap4: SAR backup not supported on ES1.0 ..\n"); return -ENODEV; } if (omap4_sar_not_accessible()) { pr_debug("%s: USB SAR CNTX registers are not accessible!\n", __func__); return -EBUSY; } /* * SAR bits and clocks needs to be enabled */ clkdm_wakeup(l3init_clkdm); pwrdm_enable_hdwr_sar(l3init_pwrdm); clk_enable(usb_host_ck); clk_enable(usb_tll_ck); /* Save SAR BANK1 */ if (cpu_is_omap446x()) sar_save(ARRAY_SIZE(omap446x_sar_ram1_layout), SAR_BANK1_OFFSET, omap446x_sar_ram1_layout); else sar_save(ARRAY_SIZE(omap443x_sar_ram1_layout), SAR_BANK1_OFFSET, omap443x_sar_ram1_layout); clk_disable(usb_host_ck); clk_disable(usb_tll_ck); pwrdm_disable_hdwr_sar(l3init_pwrdm); clkdm_allow_idle(l3init_clkdm); /* Save SAR BANK2 */ if (cpu_is_omap446x()) sar_save(ARRAY_SIZE(omap446x_sar_ram2_layout), SAR_BANK2_OFFSET, omap446x_sar_ram2_layout); else sar_save(ARRAY_SIZE(omap443x_sar_ram2_layout), SAR_BANK2_OFFSET, omap443x_sar_ram2_layout); return 0; }
/* * omap4_sar_save - * Save the context to SAR_RAM1 and SAR_RAM2 as per * sar_ram1_layout and sar_ram2_layout for the device OFF mode */ int omap4_sar_save(void) { struct clockdomain *l3_init_clkdm; /* * Not supported on ES1.0 silicon */ if (omap_rev() == OMAP4430_REV_ES1_0) { WARN_ONCE(1, "omap4: SAR backup not supported on ES1.0 ..\n"); return 0; } if (omap4_sar_enable_check() < 0) { WARN(1, "%s: SAR enable check failed!\n", __func__); return -EBUSY; } l3_init_clkdm = clkdm_lookup("l3_init_clkdm"); omap2_clkdm_wakeup(l3_init_clkdm); /* * SAR bits and clocks needs to be enabled */ pwrdm_enable_hdwr_sar(l3init_pwrdm); clk_enable(usb_host_ck); clk_enable(usb_tll_ck); /* Save SAR BANK1 */ sar_save(NB_REGS_CONST_SETS_RAM1_HW, SAR_BANK1_OFFSET, sar_ram1_layout); clk_disable(usb_host_ck); clk_disable(usb_tll_ck); pwrdm_disable_hdwr_sar(l3init_pwrdm); omap2_clkdm_allow_idle(l3_init_clkdm); /* Save SAR BANK2 */ sar_save(NB_REGS_CONST_SETS_RAM2_HW, SAR_BANK2_OFFSET, sar_ram2_layout); return 0; }
static void save_sar_bank3(void) { struct clockdomain *l4_secure_clkdm; /* * Not supported on ES1.0 silicon */ if (omap_rev() == OMAP4430_REV_ES1_0) { WARN_ONCE(1, "omap4: SAR backup not supported on ES1.0 ..\n"); return; } l4_secure_clkdm = clkdm_lookup("l4_secure_clkdm"); clkdm_wakeup(l4_secure_clkdm); if (cpu_is_omap446x()) sar_save(ARRAY_SIZE(omap446x_sar_ram3_layout), SAR_BANK3_OFFSET, omap446x_sar_ram3_layout); else sar_save(ARRAY_SIZE(omap443x_sar_ram3_layout), SAR_BANK3_OFFSET, omap443x_sar_ram3_layout); clkdm_allow_idle(l4_secure_clkdm); }
static void save_sar_bank3(void) { struct clockdomain *l4_secure_clkdm; /* * Not supported on ES1.0 silicon */ if (omap_rev() == OMAP4430_REV_ES1_0) { WARN_ONCE(1, "omap4: SAR backup not supported on ES1.0 ..\n"); return; } l4_secure_clkdm = clkdm_lookup("l4_secure_clkdm"); omap2_clkdm_wakeup(l4_secure_clkdm); sar_save(NB_REGS_CONST_SETS_RAM3_HW, SAR_BANK3_OFFSET, sar_ram3_layout); omap2_clkdm_allow_idle(l4_secure_clkdm); }