/*********************************************************************************
*
* Routine Description: Config SB After PCI INIT
*
* Arguments:
*
* pConfig - SBconfiguration
*
* Returns: void
*
* Reference: atiSbAfterPciInit
*
**********************************************************************************/
void sbAfterPciInit(AMDSBCFG* pConfig){
BUILDPARAM *pStaticOptions;
TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
pStaticOptions = &pConfig->BuildParameters;
usbInitMidPost(pConfig); //usb initialization which is required only during post
usbInitAfterPciInit(pConfig); // Init USB MMIO
sataInitAfterPciEnum(pConfig); // SATA port enumeration
azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
TRACE((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
}
/**
* sbAfterPciInit - Config Southbridge after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbAfterPciInit (
IN AMDSBCFG* pConfig
)
{
usbInitAfterPciInit (pConfig); // Init USB MMIO
sataInitAfterPciEnum (pConfig); // SATA port enumeration
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
#ifndef NO_HWM_SUPPORT
hwmInit (pConfig);
#endif
}
/**
* sbAfterPciInit - Config Southbridge after PCI emulation
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbAfterPciInit (
IN AMDSBCFG* pConfig
)
{
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciInit \n"));
imcEnableSurebootTimer (pConfig);
usbInitAfterPciInit (pConfig); // Init USB MMIO
sataInitAfterPciEnum (pConfig); // SATA port enumeration
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hwmUpdateData (pConfig);
TRACE ((DMSG_SB_TRACE, "CIMx - Exiting sbAfterPciInit \n"));
}
/*********************************************************************************
*
* Routine Description: Config SB after ACPI S3 resume PCI config device restore
*
* Arguments:
*
* pConfig - SBconfiguration
*
* Returns: void
*
* Reference: AtiSbAfPciRestore
*
**********************************************************************************/
void sbAfterPciRestoreInit(AMDSBCFG* pConfig){
BUILDPARAM *pStaticOptions;
pConfig->S3Resume = 1;
pStaticOptions = &pConfig->BuildParameters;
TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
commonInitLateBoot(pConfig);
sataInitAfterPciEnum(pConfig);
azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit
sataInitLatePost(pConfig);
sbSmmAcpiOn(pConfig);
}
VOID
sbAfterPciRestoreInit (
IN AMDSBCFG* pConfig
)
{
BUILDPARAM *pStaticOptions;
pConfig->S3Resume = 1;
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
pStaticOptions = &(pConfig->BuildParameters);
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
commonInitLateBoot (pConfig);
sataInitAfterPciEnum (pConfig);
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
sataInitLatePost (pConfig);
c3PopupSetting (pConfig);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
hwmInit (pConfig);
hwmImcInit (pConfig);
}
VOID
sbAfterPciRestoreInit (
IN AMDSBCFG* pConfig
)
{
BUILDPARAM *pStaticOptions;
pConfig->S3Resume = 1;
usbSetPllDuringS3 (pConfig);
pStaticOptions = &(pConfig->BuildParameters);
commonInitLateBoot (pConfig);
sataInitAfterPciEnum (pConfig);
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
sataInitLatePost (pConfig);
c3PopupSetting (pConfig);
#ifndef NO_HWM_SUPPORT
SBIMCFanInitializeS3 ();
#endif
}
static void sata_enable_resources(struct device *dev)
{
sataInitAfterPciEnum(sb_config);
pci_dev_enable_resources(dev);
}
