static bool set_gpio_config_addr(unsigned short addr)
{
if (io_Init() == false) {
err_print((char*)"%s: Init IO lib error!!\n", __FUNCTION__);
return false;
}
if ((gpio_config_addr = sb_Read16(0x62) & 0xfffe) == 0x0000)
sb_Write16(0x62, sb_Read16(0x62) | (gpio_config_addr = GPIO_CONFIG_ADDR));
sb_Write16(0x62, sb_Read16(0x62) | 0x0001);
// io_outpdw(GPIO_CONFIG_ADDR + 0x00, io_inpdw(GPIO_CONFIG_ADDR + 0x00) | 0x00000004L);
if (io_Close() == false) err_print((char*)"%s: Close IO lib error!!\n", __FUNCTION__);
return true;
}
DMP_INLINE(int) addIRQEntry(uint8_t interruptNum, void (*callback)(void), int mode, uint32_t timeout)
{
OSSPINLOCK(idc.spinlock);
idc.intr[interruptNum].used = true;
idc.intr[interruptNum].callback = callback;
idc.intr[interruptNum].mode = mode;
idc.intr[interruptNum].start = micros();
idc.intr[interruptNum].timeout = timeout;
pinMode(pin_interrupt[interruptNum], INPUT);
if(mode != LOW && mode != HIGH && timeout == 0)
{
uint16_t crossbar_ioaddr;
int32_t mc = interruptNum/3;
int32_t md = MCSIF_MODULEB;
lockMCMSIF();
if(mcm_init[mc] == false)
mcmsif_init(mc);
crossbar_ioaddr = sb_Read16(0x64)&0xfffe;
if (mc == 0)
io_outpb(crossbar_ioaddr + 2, 0x01); // GPIO port2: 0A, 0B, 0C, 3A
else if (mc == 1)
io_outpb(crossbar_ioaddr + 3, 0x02); // GPIO port3: 1A, 1B, 1C, 3B
else if(mc == 2)
io_outpb(crossbar_ioaddr, 0x03); // GPIO port0: 2A, 2B, 2C, 3C
else if(mc == 3)
{
io_outpb(crossbar_ioaddr + 2, 0x01);
io_outpb(crossbar_ioaddr + 3, 0x02);
io_outpb(crossbar_ioaddr, 0x03);
}
mcsif_Disable(mc, md);
switch (mode)
{
case CHANGE:
sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_BOTH);
break;
case FALLING:
sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_1TO0);
break;
case RISING:
sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_0TO1);
break;
default:
break;
}
// switch crossbar to MCM_SIF_PIN
io_outpb(crossbar_ioaddr + 0x90 + pin_offset[interruptNum], 0x08);//RICH IO
mcsif_Enable(mc, md);
unLockMCMSIF();
}
OSSPINUNLOCK(idc.spinlock);
}
static void open_mcm_crossbar(int mc) {
unsigned short crossbar_ioaddr;
crossbar_ioaddr = sb_Read16(0x64)&0xfffe;
if (mc == 0)
io_outpb(crossbar_ioaddr + 2, 0x01); // GPIO port2: 0A, 0B, 0C, 3A
else if (mc == 1)
io_outpb(crossbar_ioaddr + 3, 0x02); // GPIO port3: 1A, 1B, 1C, 3B
else if(mc == 2)
io_outpb(crossbar_ioaddr, 0x03); // GPIO port0: 2A, 2B, 2C, 3C
else if(mc == 3)
{
io_outpb(crossbar_ioaddr + 2, 0x01);
io_outpb(crossbar_ioaddr + 3, 0x02);
io_outpb(crossbar_ioaddr, 0x03);
}
}
void attachInterrupt(uint8_t interruptNum, void (*userFunc)(void), int mode) {
int i;
unsigned short crossbar_ioaddr;
if(interruptNum >= EXTERNAL_NUM_INTERRUPTS)
{
printf("This interrupt%d has no one pin to use\n", interruptNum);
return;
}
mc = interruptNum/3;
md = MCSIF_MODULEB;
if(_userfunc[interruptNum] != NULL) return;
if(interrupt_init() == false) return;
mcmsif_init();
clear_INTSTATUS();
enable_MCINT(0xfc); // SIFB FAULT INT3/2/1 + STAT3/2/1 = 6 bits
crossbar_ioaddr = sb_Read16(0x64)&0xfffe;
if (mc == 0)
io_outpb(crossbar_ioaddr + 2, 0x01); // GPIO port2: 0A, 0B, 0C, 3A
else if (mc == 1)
io_outpb(crossbar_ioaddr + 3, 0x02); // GPIO port3: 1A, 1B, 1C, 3B
else if(mc == 2)
io_outpb(crossbar_ioaddr, 0x03); // GPIO port0: 2A, 2B, 2C, 3C
else if(mc == 3)
{
io_outpb(crossbar_ioaddr + 2, 0x01);
io_outpb(crossbar_ioaddr + 3, 0x02);
io_outpb(crossbar_ioaddr, 0x03);
}
mcsif_Disable(mc, md);
io_DisableINT();
_userfunc[interruptNum] = userFunc;
io_RestoreINT();
switch (mode)
{
case LOW:
sifSetPol[interruptNum%3](mc, md, MCPFAU_POL_INVERSE);
sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_INACTIVE);
sifSetRelease[interruptNum%3](mc, md, MCPFAU_FAURELS_FSTAT0);
sifClearStat[interruptNum%3](mc, md);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_LEVEL0;
clear_INTSTATUS();
break;
case HIGH:
sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_INACTIVE);
sifSetRelease[interruptNum%3](mc, md, MCPFAU_FAURELS_FSTAT0);
sifClearStat[interruptNum%3](mc, md);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_LEVEL1;
clear_INTSTATUS();
break;
case CHANGE:
sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_BOTH);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_BOTH;
break;
case FALLING:
sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_1TO0);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_1TO0;
break;
case RISING:
sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_0TO1);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_0TO1;
break;
default:
printf("No support this mode\n");
return;
}
// switch crossbar to MCM_SIF_PIN
io_outpb(crossbar_ioaddr + 0x90 + pin_offset[interruptNum], 0x08);//RICH IO
mcsif_Enable(mc, md);
// If select level-trigger, switch the MASK to "NONE" after sif is enabled.
switch (mode)
{
case LOW: case HIGH:
sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_NONE);
break;
default: break;
}
}
bool init() {
int i, crossbarBase, gpioBase;
if(io_Init() == false) return false;
timer_NowTime(); // initialize timer
CLOCKS_PER_MICROSEC = vx86_CpuCLK();
VORTEX86EX_CLOCKS_PER_MS = CLOCKS_PER_MICROSEC*1000UL;
// Set IRQ4 as level-trigger
io_outpb(0x4D0, io_inpb(0x4D0) | 0x10);
//set corssbar Base Address
crossbarBase = sb_Read16(SB_CROSSBASE) & 0xfffe;
if(crossbarBase == 0 || crossbarBase == 0xfffe)
sb_Write16(SB_CROSSBASE, CROSSBARBASE | 0x01);
// Force set HIGH speed ISA on SB
sb_Write(SB_FCREG, sb_Read(SB_FCREG) | 0x8000C000L);
//set SB GPIO Base Address
gpioBase = sb_Read16(SB_GPIOBASE) & 0xfffe;
if(gpioBase == 0 || gpioBase == 0xfffe)
{
sb_Write16(SB_GPIOBASE, GPIOCTRLBASE | 0x01);
gpioBase = GPIOCTRLBASE;
}
// Enable GPIO 0 ~ 7
io_outpdw(gpioBase, 0x00ff);
// set GPIO Port 0~7 dircetion & data Address
for(i=0;i<8;i++)
io_outpdw(gpioBase + (i+1)*4,((GPIODIRBASE + i*4)<<16) + GPIODATABASE + i*4);
// set ADC Base Address
sb_Write(0xbc, sb_Read(0xbc) & (~(1L<<28))); // active adc
sb1_Write16(0xde, sb1_Read16(0xde) | 0x02); // not Available for 8051A Access ADC
sb1_Write(0xe0, 0x0050fe00L); // baseaddr = 0xfe00, disable irq
// set MCM Base Address
set_MMIO();
mc_setbaseaddr();
for(i=0; i<4; i++)
mc_SetMode(i, MCMODE_PWM_SIFB);
if(Global_irq_Init == false)
{
// set MCM IRQ
if(irq_Init() == false)
{
printf("MCM IRQ init fail\n"); return false;
}
if(irq_Setting(GetMCIRQ(), IRQ_LEVEL_TRIGGER + IRQ_DISABLE_INTR) == false)
{
printf("MCM IRQ Setting fail\n"); return false;
}
Set_MCIRQ(GetMCIRQ());
Global_irq_Init = true;
}
//CDC
USBDEV = CreateUSBDevice();
if(USBDEV == NULL)
{
printf("init error\n");
return false;
}
usb_SetUSBPins(USBDEV, 7, 0, 7, 1);
usb_SetTimeOut(USBDEV, 0L, 500L); // USB RX timerout is 0ms and TX timeout is 500ms
if(usb_Init(USBDEV) == false)
{
printf("init2 error\n");
return false;
}
//io_Close();
return true;
}
static void open_encoder_pin(int mc, int pin) {
unsigned short crossbar_ioaddr;
crossbar_ioaddr = sb_Read16(0x64)&0xfffe;
io_outpb(crossbar_ioaddr + 0x90 + pin_offset[mc*3+pin], 0x08);//RICH IO
}
void analogWrite(uint8_t pin, int val) {
unsigned short crossbar_ioaddr = 0;
if(pin >= PINS) return;
if (val <= 0)
digitalWrite(pin, LOW);
else if (val >= 255)
digitalWrite(pin, HIGH);
else
{
mc = arduino_to_mc_md[MCM_MC][pin];
md = arduino_to_mc_md[MCM_MD][pin];
if(mc == NOPWM || md == NOPWM)
{
if (val < 128)
digitalWrite(pin, LOW);
else
digitalWrite(pin, HIGH);
return;
}
mc_setbaseaddr();
//Master_DX2();
crossbar_ioaddr = sb_Read16(0x64)&0xfffe;
if (pin <= 9)
io_outpb(crossbar_ioaddr + 2, 0x01); // GPIO port2: 0A, 0B, 0C, 3A
else if (pin > 28)
io_outpb(crossbar_ioaddr, 0x03); // GPIO port0: 2A, 2B, 2C, 3C
else
io_outpb(crossbar_ioaddr + 3, 0x02); // GPIO port3: 1A, 1B, 1C, 3B
// Init H/W PWM
if(mc_md_inuse[pin] == 0)
{
if (mc_SetMode(mc, MCMODE_PWM_SIFB) == false)
{
printf("ERROR: fail to change MC mode!\n");
return;
}
mcpwm_SetOutMask(mc, md, MCPWM_HMASK_NONE + MCPWM_LMASK_NONE);
mcpwm_SetOutPolarity(mc, md, MCPWM_HPOL_NORMAL + MCPWM_LPOL_NORMAL);
mcpwm_SetDeadband(mc, md, 0L);
mcpwm_ReloadOUT_Unsafe(mc, md, MCPWM_RELOAD_NOW);
mcpwm_SetWaveform(mc, md, MCPWM_EDGE_A0I1);
mcpwm_SetSamplCycle(mc, md, 1999L); // sample cycle: 20ms
mcpwm_SetOutPolarity(mc, md, MCPWM_HPOL_NORMAL + MCPWM_LPOL_NORMAL);
mcpwm_SetDeadband(mc, md, 0L);
mcpwm_ReloadOUT_Unsafe(mc, md, MCPWM_RELOAD_NOW);
io_outpb(crossbar_ioaddr + 0x90 + pinMap[pin], 0x08);
}
mcpwm_SetWidth(mc, md, 2040L*SYSCLK, (8*val*SYSCLK)); // period: 2.04ms, duty: 8us resolution: 10ns
mcpwm_ReloadPWM(mc, md, MCPWM_RELOAD_PEREND);
if(mc_md_inuse[pin] == 0)
{
mcpwm_Enable(mc, md);
mc_md_inuse[pin] = 1;
}
}
}
void attachInterrupt(uint8_t interruptNum, void (*userCallBackFunc)(void), int mode) {
unsigned short crossbar_ioaddr;
if(interruptNum >= EXTERNAL_NUM_INTERRUPTS)
{
printf("This interrupt%d has no one pin to use\n", interruptNum);
return;
}
mc = PIN86[INTPINSMAP[interruptNum]].ENCMC;
md = PIN86[INTPINSMAP[interruptNum]].ENCMD;
if(PIN86[INTPINSMAP[interruptNum]].userfunc != NULL) return;
if(interrupt_init() == false) return;
mcmsif_init();
clear_INTSTATUS();
enable_MCINT(0xfc); // SIFB FAULT INT3/2/1 + STAT3/2/1 = 6 bits
crossbar_ioaddr = sb_Read16(0x64)&0xfffe;
mcsif_Disable(mc, md);
io_DisableINT();
PIN86[INTPINSMAP[interruptNum]].userfunc = userCallBackFunc;
io_RestoreINT();
switch (mode)
{
case LOW:
sifSetPol[interruptNum%3](mc, md, MCPFAU_POL_INVERSE);
sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_INACTIVE);
sifSetRelease[interruptNum%3](mc, md, MCPFAU_FAURELS_FSTAT0);
sifClearStat[interruptNum%3](mc, md);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_LEVEL0;
clear_INTSTATUS();
break;
case HIGH:
sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_INACTIVE);
sifSetRelease[interruptNum%3](mc, md, MCPFAU_FAURELS_FSTAT0);
sifClearStat[interruptNum%3](mc, md);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_LEVEL1;
clear_INTSTATUS();
break;
case CHANGE:
sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_BOTH);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_BOTH;
break;
case FALLING:
sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_1TO0);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_1TO0;
break;
case RISING:
sifIntMode[interruptNum%3](mc, md, MCPFAU_CAP_0TO1);
_usedMode[mc][interruptNum%3] = MCPFAU_CAP_0TO1;
break;
default:
printf("No support this mode\n");
return;
}
// switch crossbar to MCM_SIF_PIN
io_outpb(crossbar_ioaddr + 0x90 + PIN86[INTPINSMAP[interruptNum]].gpN, 0x08);//RICH IO
mcsif_Enable(mc, md);
// If select level-trigger, switch the MASK to "NONE" after sif is enabled.
switch (mode)
{
case LOW: case HIGH:
sifSetMask[interruptNum%3](mc, md, MCPFAU_MASK_NONE);
break;
default: break;
}
}
