/*--------------------------------------------------------------------------------------------- * (function: ou_initialize_macro_type_lookup ) * Allows a string of a macro type to lookup the associated macro node identifying number *-------------------------------------------------------------------------------------------*/ void ou_initialize_macro_type_lookup() { int i; int sc_idx; /* initialize the has function */ macro_numbers_sc = sc_new_string_cache(); //printf("%d -1 == %d\n", MACRO_STRING_SIZE, MN_END_POINT); assert(MACRO_STRING_SIZE - 1 == MN_END_POINT); for (i = 0; i < MN_END_POINT; i++) { /* add the next macro string into the hash */ sc_idx = sc_add_string(macro_numbers_sc, macro_string[i]); if(macro_numbers_sc->data[sc_idx] == NULL) { /* IF - record the number associated with this string */ macro_numbers_sc->data[sc_idx] = (void*)i; } else { /* ELSE - the string has data */ assert(FALSE); } } }
/*--------------------------------------------------------------------------------------------- * (function: allocate_netlist) *-------------------------------------------------------------------------------------------*/ netlist_t* allocate_netlist() { netlist_t *new_netlist; new_netlist = (netlist_t *)my_malloc_struct(sizeof(netlist_t)); new_netlist->gnd_node = NULL; new_netlist->vcc_node = NULL; new_netlist->pad_node = NULL; new_netlist->zero_net = NULL; new_netlist->one_net = NULL; new_netlist->pad_net = NULL; new_netlist->top_input_nodes = NULL; new_netlist->num_top_input_nodes = 0; new_netlist->top_output_nodes = NULL; new_netlist->num_top_output_nodes = 0; new_netlist->ff_nodes = NULL; new_netlist->num_ff_nodes = 0; new_netlist->internal_nodes = NULL; new_netlist->num_internal_nodes = 0; new_netlist->clocks = NULL; new_netlist->num_clocks = 0; new_netlist->forward_levels = NULL; new_netlist->num_forward_levels = 0; new_netlist->num_at_forward_level = NULL; new_netlist->backward_levels = NULL; new_netlist->num_backward_levels = 0; new_netlist->num_at_backward_level = NULL; new_netlist->sequential_level_nodes = NULL; new_netlist->num_sequential_levels = 0; new_netlist->num_at_sequential_level = NULL; new_netlist->sequential_level_combinational_termination_node = NULL; new_netlist->num_sequential_level_combinational_termination_nodes = 0; new_netlist->num_at_sequential_level_combinational_termination_node = NULL; /* initialize the string chaches */ new_netlist->nets_sc = sc_new_string_cache(); new_netlist->out_pins_sc = sc_new_string_cache(); new_netlist->nodes_sc = sc_new_string_cache(); new_netlist->stats = NULL; return new_netlist; }
/*--------------------------------------------------------------------------- * (function: do_high_level_synthesis) *-------------------------------------------------------------------------*/ void do_high_level_synthesis() { double elaboration_time = wall_time(); printf("--------------------------------------------------------------------\n"); printf("High-level synthesis Begin\n"); /* Perform any initialization routines here */ #ifdef VPR6 find_hard_multipliers(); find_hard_adders(); //find_hard_adders_for_sub(); register_hard_blocks(); #endif global_param_table_sc = sc_new_string_cache(); /* parse to abstract syntax tree */ printf("Parser starting - we'll create an abstract syntax tree. " "Note this tree can be viewed using GraphViz (see documentation)\n"); parse_to_ast(); /* Note that the entry point for ast optimzations is done per module with the * function void next_parsed_verilog_file(ast_node_t *file_items_list) */ /* after the ast is made potentiatlly do tagging for downstream links to verilog */ if (global_args.high_level_block != NULL) { add_tag_data(); } /* Now that we have a parse tree (abstract syntax tree [ast]) of * the Verilog we want to make into a netlist. */ printf("Converting AST into a Netlist. " "Note this netlist can be viewed using GraphViz (see documentation)\n"); create_netlist(); // Can't levelize yet since the large muxes can look like combinational loops when they're not check_netlist(verilog_netlist); /* point for all netlist optimizations. */ printf("Performing Optimizations of the Netlist\n"); netlist_optimizations_top(verilog_netlist); if (configuration.output_netlist_graphs ) { /* Path is where we are */ graphVizOutputNetlist(configuration.debug_output_path, "optimized", 1, verilog_netlist); } /* point where we convert netlist to FPGA or other hardware target compatible format */ printf("Performing Partial Map to target device\n"); partial_map_top(verilog_netlist); #ifdef VPR5 /* check for problems in the partial mapped netlist */ printf("Check for liveness and combinational loops\n"); levelize_and_check_for_combinational_loop_and_liveness(TRUE, verilog_netlist); #endif /* point for outputs. This includes soft and hard mapping all structures to the * target format. Some of these could be considred optimizations */ printf("Outputting the netlist to the specified output format\n"); output_top(verilog_netlist); elaboration_time = wall_time() - elaboration_time; printf("Successful High-level synthesis by Odin in "); print_time(elaboration_time); printf("\n"); printf("--------------------------------------------------------------------\n"); // FIXME: free contents? sc_free_string_cache(global_param_table_sc); }