void simple_bus_master_non_blocking::main_action()
{
int mydata;
int cnt = 0;
unsigned int addr = m_start_address;
wait(); // ... for the next rising clock edge
while (true)
{
bus_port->read(m_unique_priority, &mydata, addr, m_lock);
while ((bus_port->get_status(m_unique_priority) != SIMPLE_BUS_OK) &&
(bus_port->get_status(m_unique_priority) != SIMPLE_BUS_ERROR))
wait();
if (bus_port->get_status(m_unique_priority) == SIMPLE_BUS_ERROR)
sb_fprintf(stdout, "%g %s : ERROR cannot read from %x\n",
sc_simulation_time(), name(), addr);
mydata += cnt;
cnt++;
bus_port->write(m_unique_priority, &mydata, addr, m_lock);
while ((bus_port->get_status(m_unique_priority) != SIMPLE_BUS_OK) &&
(bus_port->get_status(m_unique_priority) != SIMPLE_BUS_ERROR))
wait();
if (bus_port->get_status(m_unique_priority) == SIMPLE_BUS_ERROR)
sb_fprintf(stdout, "%g %s : ERROR cannot write to %x\n",
sc_simulation_time(), name(), addr);
wait(m_timeout, SC_NS);
wait(); // ... for the next rising clock edge
addr+=4; // next word (byte addressing)
if (addr > (m_start_address+0x80)) {
addr = m_start_address; cnt = 0;
}
}
}
void NoximProcessingElement::rxProcess()
{
if (reset.read()) {
ack_rx.write(0);
current_level_rx = 0;
} else {
if (req_rx.read() == 1 - current_level_rx) {
NoximFlit flit_tmp = flit_rx.read();
if (NoximGlobalParams::verbose_mode > VERBOSE_OFF) {
cout << sc_simulation_time() << ": ProcessingElement[" <<
local_id << "] RECEIVING " << flit_tmp << endl;
}
current_level_rx = 1 - current_level_rx; // Negate the old value for Alternating Bit Protocol (ABP)
}
ack_rx.write(current_level_rx);
}
}
void simple_bus_master_direct::main_action()
{
int mydata[4];
while (true)
{
bus_port->direct_read(&mydata[0], m_address);
bus_port->direct_read(&mydata[1], m_address+4);
bus_port->direct_read(&mydata[2], m_address+8);
bus_port->direct_read(&mydata[3], m_address+12);
if (m_verbose)
sb_fprintf(stdout, "%g %s : mem[%x:%x] = (%x, %x, %x, %x)\n",
sc_simulation_time(), name(), m_address, m_address+15,
mydata[0], mydata[1], mydata[2], mydata[3]);
wait(m_timeout, SC_NS);
}
}
int sc_main(int ac, char *av[])
{
//! ISA simulator
mips mips_proc1("mips");
//! Bus
ac_tlm_bus bus("bus");
// Memory
ac_tlm_mem mem("mem");
#ifdef AC_DEBUG
ac_trace("mips1_proc1.trace");
#endif
mips_proc1.DM(bus.target_export);
bus.MEM_port(mem.target_export);
mips_proc1.init(ac, av);
mips_proc1.set_prog_args();
cerr << endl;
sc_start();
mips_proc1.PrintStat();
cerr << endl;
#ifdef AC_STATS
mips1_proc1.ac_sim_stats.time = sc_simulation_time();
mips1_proc1.ac_sim_stats.print();
#endif
#ifdef AC_DEBUG
ac_close_trace();
#endif
return mips_proc1.ac_exit_status;
}
int sc_main (int argc, char *argv[]) {
sc_signal<bool> clk, reset, clear;
wait();
wait (clk.posedge_event());
wait (reset.negedge_event());
// negedge_event() and posedge_event() methods can
// be applied to a signal or a port to identify the
// specific event.
wait (clk.posedge_event() | reset.negedge_event() | clear.value_changed_event());
// A value_changed_event() method is true when any
// value change occu
sc_signal<sc_uint<4> > ready;
sc_signal<bool> data;
wait (clk.value_changed_event() & data.posedge_event() & ready.value_changed_event());
// The events can span over multiple simulation
// cycles. For example, if clk changes at 5ns,
// a positive edge on data occurs at 8ns and ready
// changes at 10ns, then the wait is triggered at
// time 10ns.
wait (20, SC_NS);
// does NOT work with sc_bit or sc_logic:
sc_signal<bool> speed_ctrl;
wait (10, SC_NS, speed_ctrl.posedge_event());
// Waits for positive edge to occur on speed_ctrl
// for 10ns and then times out.
wait (SC_ZERO_TIME);
wait (0, SC_NS);
sc_signal<sc_logic> sac;
// sc_in<sc_logic> sync_reset;
sc_signal<sc_logic> sync_reset;
wait (sac.posedge_event());
wait (sync_reset.negedge_event());
sc_event write_back;
// sensitive << write_back;
wait (write_back);
write_back.notify();
write_back.notify (20, SC_NS);
write_back.notify(SC_ZERO_TIME);
// Trigger event in next delta cycle.
write_back.cancel(); // Cancels a delayed notification.
sc_out<bool> out_port;
out_port.initialize(0);
sc_time t_res;
t_res = sc_get_time_resolution();
cout << "The time resolution is " << sc_get_time_resolution() << endl;
double time_in_dbl;
sc_time time_res = sc_get_time_resolution();
sc_time curr_time = sc_time_stamp();
time_in_dbl = curr_time / time_res;
cout << "Time as a double value is " << time_in_dbl << endl;
time_in_dbl = sc_simulation_time();
cout << "Time is " << time_in_dbl;
sc_set_default_time_unit (100, SC_PS);
sc_time t_unit (10, SC_NS);
// NOT WORKING:
// sc_set_default_time_unit (t_unit);
sc_set_default_time_unit (100, SC_PS);
sc_time tf_unit;
tf_unit = sc_get_default_time_unit();
// Wake up SC_METHOD process after 10ns:
next_trigger (10, SC_NS);
// Wake up SC_METHOD process on a rising edge
// of reset:
next_trigger (reset.posedge_event());
return 0;
}
int sc_main(int ac, char *av[])
{
//! ISA simulator
// adicionados novos processadores
mips mips1_proc1("mips1");
mips mips2_proc2("mips2");
mips mips3_proc3("mips3");
mips mips4_proc4("mips4");
mips mips5_proc5("mips5");
mips mips6_proc6("mips6");
mips mips7_proc7("mips7");
mips mips8_proc8("mips8");
//! Memory
ac_tlm_mem mem("mem");
//! Novos modulos do P3
user::bw_hardware bw("bw_hardware1");
user::bar_mem bar("bar_mem1");
user::mutex_token mutex("mutex_token1");
bar.DM_port(mem.target_export);
bar.BW_port(bw.target_export);
bar.MUTEX_port(mutex.target_export);
#ifdef AC_DEBUG
ac_trace("mips1_proc1.trace");
#endif
//conecta os processadores no barramento
mips1_proc1.DM_port(bar.target_export1);
mips2_proc2.DM_port(bar.target_export2);
mips3_proc3.DM_port(bar.target_export3);
mips4_proc4.DM_port(bar.target_export4);
mips5_proc5.DM_port(bar.target_export5);
mips6_proc6.DM_port(bar.target_export6);
mips7_proc7.DM_port(bar.target_export7);
mips8_proc8.DM_port(bar.target_export8);
char * program = av[1];
//inicia os processadores
mips1_proc1.init(ac, av);
av[1] = program;
mips2_proc2.init(ac, av);
av[1] = program;
mips3_proc3.init(ac, av);
av[1] = program;
mips4_proc4.init(ac, av);
av[1] = program;
mips5_proc5.init(ac, av);
av[1] = program;
mips6_proc6.init(ac, av);
av[1] = program;
mips7_proc7.init(ac, av);
av[1] = program;
mips8_proc8.init(ac, av);
cerr << endl;
sc_start();
//imprime o status dos processadores
mips1_proc1.PrintStat();
mips2_proc2.PrintStat();
mips3_proc3.PrintStat();
mips4_proc4.PrintStat();
mips5_proc5.PrintStat();
mips6_proc6.PrintStat();
mips7_proc7.PrintStat();
mips8_proc8.PrintStat();
cerr << endl;
#ifdef AC_STATS
mips1_proc1.ac_sim_stats.time = sc_simulation_time();
mips1_proc1.ac_sim_stats.print();
#endif
#ifdef AC_DEBUG
ac_close_trace();
#endif
return mips1_proc1.ac_exit_status;
}
void monitor::prc_monitor() {
cout << "At time " << sc_simulation_time() << "::";
cout << "(clock, reset, sel, inp): ";
cout << m_clock.read() << m_reset.read() << m_sel.read() << m_inp.read();
cout << " out: " << m_out.read() << '\n';
}
void DRAM_mem_mp::working(int idx)
{
uint32_t addr, prev_addr, size;
int burst = 0, i,j, bw;
bool wr;
PINOUT mast_pinout;
unsigned long int data;
ready[idx].write(false);
while (true)
{
must_wait[idx] = true;
__DELTA_L1;
if(!request[idx].read())
wait(request[idx].posedge_event());
if(CL_GLB_STATS)
L3_acc_cnt++;
// What's up?
mast_pinout = pinout[idx].read();
bw = mast_pinout.bw;
// Word, half word or byte?
switch (bw)
{
case 0 : size = 0x4;
break;
case 1 : size = 0x1;
break;
case 2 : size = 0x2;
break;
default : printf("Fatal error: Master %hu detected a malformed data size at %10.1f ns\n",
ID, sc_simulation_time());
exit(1);
}
burst = (int)mast_pinout.burst;
wr = mast_pinout.rw;
//addr = addresser->Logical2Physical(mast_pinout.address, global_ID);
addr = mast_pinout.address;
//////////////////////////////////
// Wait for MEM_IN_WS cycles if != 0
for(i = 0; i < (int)mem_in_ws; i++)
wait(clock.posedge_event());
// ------------------------------ READ ACCESS ------------------------------
if (!wr)
{
for (i = 0; i < burst; i ++)
{
data = this->Read(addr, bw, idx);
do
{
wait(clock.posedge_event());
ready[idx].write(false);
} while (must_wait[idx] == true);
//fflush(stdout);
// Wait cycles between burst beat
for(j=0; j<(int)mem_bb_ws && i!=0; j++)
wait(clock.posedge_event());
prev_addr = addr;
// Increment the address for the next beat
addr += size;
mast_pinout.data = data;
pinout[idx].write(mast_pinout);
ready[idx].write(true);
} // end for
wait(clock.posedge_event());
ready[idx].write(false);
}
// ------------------------------ WRITE ACCESS ------------------------------
else
{
for (i = 0; i < burst; i ++)
{
data = mast_pinout.data;
this->Write(addr, data, bw, idx);
do
{
wait(clock.posedge_event());
data = mast_pinout.data;
ready[idx].write(false);
} while (must_wait[idx] == true);
///////////////////////////////////////
// Wait cycles between burst beat
for(j=0; j<(int)mem_bb_ws && i!=0; j++)
wait(clock.posedge_event());
// Increment the address for the next beat
prev_addr = addr;
addr += size;
ready[idx].write(true);
}
wait(clock.posedge_event());
ready[idx].write(false);
}
}
}
int sc_main(int ac, char *av[])
{
//! ISA simulator
// Cria todos os modulos
mips1 mips1_proc0("mips0");
mips1 mips1_proc1("mips1");
mips1 mips1_proc2("mips2");
mips1 mips1_proc3("mips3");
mips1 mips1_proc4("mips4");
mips1 mips1_proc5("mips5");
mips1 mips1_proc6("mips6");
mips1 mips1_proc7("mips7");
ac_tlm_mem mem("mem");
ac_tlm_bus bus("bus");
ac_tlm_mutex mutex("mutex");
ac_tlm_offload offload("offload");
#ifdef AC_DEBUG
ac_trace("mips1_proc0.trace");
ac_trace("mips1_proc1.trace");
ac_trace("mips1_proc2.trace");
ac_trace("mips1_proc3.trace");
ac_trace("mips1_proc4.trace");
ac_trace("mips1_proc5.trace");
ac_trace("mips1_proc6.trace");
ac_trace("mips1_proc7.trace");
#endif
// Conecta as CPUs as bus
mips1_proc0.DM_port(bus.cpu0_target_export);
mips1_proc1.DM_port(bus.cpu1_target_export);
mips1_proc2.DM_port(bus.cpu2_target_export);
mips1_proc3.DM_port(bus.cpu3_target_export);
mips1_proc4.DM_port(bus.cpu4_target_export);
mips1_proc5.DM_port(bus.cpu5_target_export);
mips1_proc6.DM_port(bus.cpu6_target_export);
mips1_proc7.DM_port(bus.cpu7_target_export);
// Conecta a bus aos outros modulos
bus.mem_port(mem.target_export);
bus.mutex_port(mutex.target_export);
bus.offload_port(offload.target_export);
// Gera argc e argv para os processadores
char **av2 = (char **)malloc(ac*sizeof(char *));
for(int i = 0; i < ac; i++)
av2[i] = (char *)malloc(strlen(av[i])*sizeof(char));
avcpy(ac, av2, av);
mips1_proc0.init(ac, av2);
avcpy(ac, av2, av);
mips1_proc1.init(ac, av2);
avcpy(ac, av2, av);
mips1_proc2.init(ac, av2);
avcpy(ac, av2, av);
mips1_proc3.init(ac, av2);
avcpy(ac, av2, av);
mips1_proc4.init(ac, av2);
avcpy(ac, av2, av);
mips1_proc5.init(ac, av2);
avcpy(ac, av2, av);
mips1_proc6.init(ac, av2);
avcpy(ac, av2, av);
mips1_proc7.init(ac, av2);
cerr << endl;
sc_start();
mips1_proc0.PrintStat();
mips1_proc1.PrintStat();
mips1_proc2.PrintStat();
mips1_proc3.PrintStat();
mips1_proc4.PrintStat();
mips1_proc5.PrintStat();
mips1_proc6.PrintStat();
mips1_proc7.PrintStat();
cerr << endl;
#ifdef AC_STATS
mips1_proc0.ac_sim_stats.time = sc_simulation_time();
mips1_proc0.ac_sim_stats.print();
mips1_proc1.ac_sim_stats.print();
mips1_proc2.ac_sim_stats.print();
mips1_proc3.ac_sim_stats.print();
mips1_proc4.ac_sim_stats.print();
mips1_proc5.ac_sim_stats.print();
mips1_proc6.ac_sim_stats.print();
mips1_proc7.ac_sim_stats.print();
#endif
#ifdef AC_DEBUG
ac_close_trace();
#endif
return mips1_proc0.ac_exit_status;
}
