static __devinit void __keypad_enable(void) { sci_glb_set(REG_GLB_SOFT_RST, BIT_KPD_RST); mdelay(2); sci_glb_clr(REG_GLB_SOFT_RST, BIT_KPD_RST); sci_glb_set(REG_GLB_GEN0, BIT_KPD_EB | BIT_RTC_KPD_EB); }
void sprd_zipdec_reset(void) { u32 i; sci_glb_set(REG_GLB_SET(REG_AP_AHB_AHB_RST),BIT_ZIPDEC_SOFT_RST); for(i=0; i<0x200; i++); sci_glb_set(REG_GLB_CLR(REG_AP_AHB_AHB_RST),BIT_ZIPDEC_SOFT_RST); }
static void __keypad_enable(void) { sci_glb_set(REG_AON_APB_APB_RST0, BIT_KPD_SOFT_RST); mdelay(2); sci_glb_clr(REG_AON_APB_APB_RST0, BIT_KPD_SOFT_RST); sci_glb_set(REG_AON_APB_APB_EB0, BIT_KPD_EB); sci_glb_set(REG_AON_APB_APB_RTC_EB, BIT_KPD_RTC_EB); }
void dsi_disable(void) { sci_glb_set(REG_AON_APB_PWR_CTRL, BIT_MIPI_DSI_PS_PD_S); sci_glb_set(REG_AON_APB_PWR_CTRL, BIT_MIPI_DSI_PS_PD_L); sci_glb_clr(REG_AP_AHB_MISC_CKG_EN, BIT_DPHY_REF_CKG_EN); sci_glb_clr(REG_AP_AHB_MISC_CKG_EN, BIT_DPHY_CFG_CKG_EN); sci_glb_clr(DSI_REG_EB, DSI_BIT_EB); }
void sprd_usb_phy_rst(void) { sci_glb_set(USB_GUSBCFG_REG, BIT(3));/*usc2s8c SPRD phy width:16 bit*/ sci_glb_clr(AP_TOP_USB_PHY_RST, BIT(0));/*for SPRD phy utmi_PORN*/ sci_glb_set(REG_AP_AHB_AHB_RST, BIT(7));/*for SPRD phy utmi_rst*/ mdelay(5); sci_glb_set(AP_TOP_USB_PHY_RST, BIT(0)); sci_glb_clr(REG_AP_AHB_AHB_RST, BIT(7)); }
int32_t dcam_reset(enum dcam_rst_mode reset_mode) { enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS; uint32_t time_out = 0; if (atomic_read(&s_dcam_users)) { /* firstly, stop AXI writing */ REG_OWR(DCAM_BURST_GAP, BIT_18); } /* then wait for AHB busy cleared */ while (++time_out < DCAM_AXI_STOP_TIMEOUT) { if (0 == (REG_RD(DCAM_AHBM_STS) & BIT_0)) break; } if (time_out >= DCAM_AXI_STOP_TIMEOUT) return DCAM_RTN_TIMEOUT; /* do reset action */ switch (reset_mode) { case DCAM_RST_PATH1: sci_glb_set(DCAM_RST, PATH1_RST_BIT); sci_glb_set(DCAM_RST, CCIR_RST_BIT); sci_glb_clr(DCAM_RST, PATH1_RST_BIT); sci_glb_clr(DCAM_RST, CCIR_RST_BIT); /* REG_OWR(DCAM_RST, DCAM_MOD_RST_BIT); REG_OWR(DCAM_RST, CCIR_RST_BIT); REG_AWR(DCAM_RST, ~DCAM_MOD_RST_BIT); REG_AWR(DCAM_RST, ~CCIR_RST_BIT); */ DCAM_TRACE("DCAM DRV: reset path1 \n"); break; case DCAM_RST_PATH2: sci_glb_set(DCAM_RST, PATH2_RST_BIT); sci_glb_clr(DCAM_RST, PATH2_RST_BIT); DCAM_TRACE("DCAM DRV: reset path2 \n"); break; case DCAM_RST_ALL: sci_glb_set(DCAM_RST, DCAM_MOD_RST_BIT); sci_glb_set(DCAM_RST, CCIR_RST_BIT); sci_glb_clr(DCAM_RST, DCAM_MOD_RST_BIT); sci_glb_clr(DCAM_RST, CCIR_RST_BIT); DCAM_TRACE("DCAM DRV: reset all \n"); break; default: rtn = DCAM_RTN_PARA_ERR; break; } if (atomic_read(&s_dcam_users)) { /* the end, enable AXI writing */ REG_AWR(DCAM_BURST_GAP, ~BIT_18); } return -rtn; }
void dsi_enable(void) { sci_glb_clr(REG_AON_APB_PWR_CTRL, BIT_MIPI_DSI_PS_PD_S); sci_glb_clr(REG_AON_APB_PWR_CTRL, BIT_MIPI_DSI_PS_PD_L); sci_glb_set(REG_AP_AHB_MISC_CKG_EN, BIT_DPHY_REF_CKG_EN); sci_glb_set(REG_AP_AHB_MISC_CKG_EN, BIT_DPHY_CFG_CKG_EN); pr_info("sprdfb: dsi_enable %08x\n", REG_AP_AHB_MISC_CKG_EN); sci_glb_set(DSI_REG_EB, DSI_BIT_EB); }
static void usb_enable_module(int en) { if (en){ sci_glb_clr(REG_AON_APB_PWR_CTRL,BIT(0)); sci_glb_set(REG_AP_AHB_AHB_EB,BIT_USB_EB); }else { sci_glb_set(REG_AON_APB_PWR_CTRL,BIT(0)); sci_glb_clr(REG_AP_AHB_AHB_EB,BIT_USB_EB); } }
void sprd_zipdec_enable(u32 enable) { if(enable) { sci_glb_set(REG_GLB_SET(REG_AP_AHB_AHB_EB),BIT_ZIPDEC_EB); sci_glb_set(REG_GLB_SET(REG_AON_APB_APB_EB1),BIT_ZIP_EMC_EB); } else { sci_glb_set(REG_GLB_CLR(REG_AP_AHB_AHB_EB),BIT_ZIPDEC_EB); //sci_glb_set(REG_GLB_CLR(REG_AON_APB_APB_EB1),BIT_ZIP_EMC_EB); } }
int __init sci_adi_init(void) { /* enable adi in global regs */ sci_glb_set(REG_GLB_GEN0,BIT_ADI_EB); /* reset adi */ sci_glb_set(REG_GLB_SOFT_RST,BIT_ADI_RST); udelay(2); sci_glb_clr(REG_GLB_SOFT_RST,BIT_ADI_RST); __sci_adi_init(); return 0; }
static void aux_clk_config(u32 clk_sel) { u32 reg_val; if(clk_sel < aux_clk_max){ /*select pin function to func 0*/ reg_val = sci_glb_read(clk_cfg_info.aux_pin,-1UL); reg_val &= ~(0x3 << 4); sci_glb_write(clk_cfg_info.aux_pin,reg_val,-1UL); /*enable aux clock*/ sci_glb_set(clk_cfg_info.aux_ena,0x1 << 2); /*select aux clock source*/ sci_glb_set(clk_cfg_info.aux_sel,clk_sel); } }
/* lcdc soft reset */ static void lcdc_reset(void) { #define REG_AHB_SOFT_RST (AHB_SOFT_RST + SPRD_AHB_BASE) sci_glb_set(REG_AHB_SOFT_RST, (1<<LCDC_SOFT_RST)); udelay(10); sci_glb_clr(REG_AHB_SOFT_RST, (1<<LCDC_SOFT_RST) ); }
/* use ana watchdog to wake up */ void pm_debug_set_apwdt(void) { uint32_t cnt = 0; uint32_t ms = 5000; cnt = (ms * WDG_CLK) / 1000; sci_glb_set(INT_IRQ_ENB, BIT(11)); /*enable interface clk*/ sci_adi_set(ANA_AGEN, AGEN_WDG_EN); /*enable work clk*/ sci_adi_set(ANA_RTC_CLK_EN, AGEN_RTC_WDG_EN); sci_adi_raw_write(WDG_LOCK, WDG_UNLOCK_KEY); sci_adi_set(WDG_CTRL, WDG_NEW_VER_EN); WDG_LOAD_TIMER_VALUE(0x80000); WDG_LOAD_TIMER_INT_VALUE(0x40000); sci_adi_set(WDG_CTRL, WDG_CNT_EN_BIT | WDG_INT_EN_BIT| WDG_RST_EN_BIT); sci_adi_raw_write(WDG_LOCK, (uint16_t) (~WDG_UNLOCK_KEY)); sci_adi_set(ANA_REG_INT_EN, BIT(3)); #if 0 do{ udelay(1000); printk("INTC1 mask:0x%08x raw:0x%08x en:0x%08x\n", __raw_readl(INTCV1_IRQ_MSKSTS),__raw_readl(INTCV1_IRQ_RAW), __raw_readl(INTCV1_IRQ_EN)); printk("INT mask:0x%08x raw:0x%08x en:0x%08x ana 0x%08x\n", __raw_readl(INT_IRQ_STS),__raw_readl(INT_IRQ_RAW), __raw_readl(INT_IRQ_ENB), sci_adi_read(ANA_REG_INT_MASK_STATUS)); printk("ANA mask:0x%08x raw:0x%08x en:0x%08x\n", sci_adi_read(ANA_REG_INT_MASK_STATUS), sci_adi_read(ANA_REG_INT_RAW_STATUS), sci_adi_read(ANA_REG_INT_EN)); printk("wdg cnt low 0x%08x high 0x%08x\n", sci_adi_read(WDG_CNT_LOW), sci_adi_read(WDG_CNT_HIGH)); }while(0); #endif }
static int init_reset_vector(void) { /* remap iram to 0x00000000 */ sci_glb_set(REG_AHB_REMAP, BIT(0)); if (!sp_pm_reset_vector) { sp_pm_reset_vector = ioremap(SPRD_RESET_VECTORS, PAGE_SIZE); if (sp_pm_reset_vector == NULL) { printk(KERN_ERR "sp_pm_init: failed to map reset vector\n"); return 0; } } iram_start = (void __iomem *)(SPRD_IRAM_BASE); /* copy sleep code to (IRAM+16K). */ if ((sc8825_standby_iram_end - sc8825_standby_iram + 128) > SLEEP_CODE_SIZE) { panic("##: code size is larger than expected, need more memory!\n"); } memcpy_toio(iram_start, sc8825_standby_iram, SLEEP_CODE_SIZE); /* copy emc re-init code to (IRAM+16k+8K) */; memcpy_toio(iram_start+2*SLEEP_CODE_SIZE, emc_init_repowered, EMC_REINIT_CODE_SIZE); /* just make sure*/ flush_cache_all(); outer_flush_all(); return 0; }
int sprdchg_timer_init(int (*fn_cb) (void *data), void *data) { int ret = -ENODEV; #if !(defined(CONFIG_ARCH_SCX35L64)||defined(CONFIG_ARCH_SCX35LT8)) //mingwei TODO if(sprd_request_timer(1,1,&timer_base)) BUG_ON(1); #else timer_base = ioremap_nocache(0X40320000 + 0x20, 0x80); #endif sci_glb_set(REG_AON_APB_APB_EB1, BIT_AP_TMR1_EB); sprdchg_timer_disable(); sprdchg_tm_cb = fn_cb; ret = request_irq(((struct sprdbat_drivier_data *)data)-> pdata->irq_chg_timer, _sprdchg_timer_interrupt, IRQF_NO_SUSPEND | IRQF_TIMER, "battery_timer", data); if (ret) { printk(KERN_ERR "request battery timer irq %d failed\n", IRQ_AONTMR0_INT); } return 0; }
/*init global regs for pm */ static void init_gr(void) { int val; /* remap iram to 0x00000000*/ sci_glb_set(REG_AHB_REMAP, BIT(0)); #ifdef CONFIG_NKERNEL /*force close cp*/ __raw_writel(0x00000001, REG_AHB_CP_SLEEP_CTRL); #endif /* AHB_PAUSE */ val = sci_glb_read(REG_AHB_AHB_PAUSE, -1UL); val &= ~(MCU_CORE_SLEEP | MCU_DEEP_SLEEP_EN | MCU_SYS_SLEEP_EN); sci_glb_write(REG_AHB_AHB_PAUSE, val, -1UL ); /* AHB_CTL1 */ val = sci_glb_read(REG_AHB_AHB_CTL1, -1UL); val |= (AHB_CTRL1_EMC_CH_AUTO_GATE_EN | AHB_CTRL1_ARM_AUTO_GATE_EN | AHB_CTRL1_AHB_AUTO_GATE_EN | AHB_CTRL1_MCU_AUTO_GATE_EN | AHB_CTRL1_ARM_DAHB_SLEEP_EN | AHB_CTRL1_MSTMTX_AUTO_GATE_EN); val &= ~AHB_CTRL1_EMC_AUTO_GATE_EN; sci_glb_write(REG_AHB_AHB_CTL1, val, -1UL ); /* enable XTL auto power down, set bufon_ctrl[17:16] 0 */ val = sci_glb_read(REG_GLB_CLK_EN, -1UL); val |= MCU_XTLEN_AUTOPD_EN; val |= BUFON_CTRL_HI; sci_glb_write(REG_GLB_CLK_EN, val, -1UL ); }
int32_t dcam_module_en(void) { int ret = 0; DCAM_TRACE("DCAM DRV: dcam_module_en: %d \n", s_dcam_users.counter); if (atomic_inc_return(&s_dcam_users) == 1) { ret = dcam_set_clk(DCA_CLK_256M); /*REG_OWR(DCAM_EB, DCAM_EB_BIT);*/ sci_glb_set(DCAM_RST, DCAM_MOD_RST_BIT); sci_glb_set(DCAM_RST, CCIR_RST_BIT); sci_glb_clr(DCAM_RST, DCAM_MOD_RST_BIT); sci_glb_clr(DCAM_RST, CCIR_RST_BIT); } return ret; }
void sc8825_enable_timer_early(void) { /* enable timer & syscnt in global regs */ sci_glb_set(REG_GLB_GEN0, BIT_RTC_TMR_EB | BIT_RTC_SYST0_EB | BIT_TMR_EB | BIT_SYST0_EB); __sched_clock_init(26000000); }
static void efuse_reset(void) { /* should enable module before soft reset efuse */ WARN_ON(!sci_glb_read(REG_AON_APB_APB_EB0, BIT_EFUSE_EB)); sci_glb_set(REG_AON_APB_APB_RST0, BIT_EFUSE_SOFT_RST); udelay(5); sci_glb_clr(REG_AON_APB_APB_RST0, BIT_EFUSE_SOFT_RST); }
int sprd_charger_is_adapter(struct sprd_battery_data *data) { uint32_t ret; volatile uint32_t i; unsigned long irq_flag = 0; mdelay(300); gpio_request(USB_DM_GPIO, "sprd_charge"); gpio_request(USB_DP_GPIO, "sprd_charge"); gpio_direction_input(USB_DM_GPIO); gpio_direction_input(USB_DP_GPIO); udc_enable(); udc_phy_down(); local_irq_save(irq_flag); sci_glb_clr(REG_AHB_USB_PHY_CTRL, (BIT_DMPULLDOWN | BIT_DPPULLDOWN)); /* Identify USB charger */ sci_glb_set(REG_AHB_USB_PHY_CTRL, BIT_DMPULLUP); mdelay(10); ret = gpio_get_value(USB_DM_GPIO); sci_glb_clr(REG_AHB_USB_PHY_CTRL, (BIT_DMPULLUP)); #if 0 /* normal charger */ if (ret) { /* Identify standard adapter */ sci_glb_set(REG_AHB_USB_PHY_CTRL, BIT_DMPULLDOWN); for (i = 0; i < 1000; i++) {; } if (gpio_get_value(USB_DM_GPIO) == gpio_get_value(USB_DP_GPIO)) { ret = 1; /* adapter */ } else { ret = 1; /* non standard adapter */ } sci_glb_clr(REG_AHB_USB_PHY_CTRL, (BIT_DMPULLDOWN)); } #endif local_irq_restore(irq_flag); udc_disable(); gpio_free(USB_DM_GPIO); gpio_free(USB_DP_GPIO); return ret; }
void __init sci_enable_timer_early(void) { /* enable timer & syscnt in global regs */ int i = 0, j = 0; sci_glb_set(REG_AON_APB_APB_EB0, BIT_AON_TMR_EB | BIT_AP_SYST_EB | BIT_AP_TMR0_EB); #if defined CONFIG_LOCAL_TIMERS && !defined CONFIG_HAVE_ARM_ARCH_TIMER sci_glb_set(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB); for (i = 0; i < 4; i++) { #else sci_glb_clr(REG_AON_APB_APB_EB1, BIT_AP_TMR2_EB | BIT_AP_TMR1_EB); for (i = 0; i < 2; i++) { #endif for (j = 0; j < 3; j++) { __gptimer_ctl(i, j, TIMER_DISABLE, 0); __raw_writel(TIMER_INT_CLR, TIMER_INT(i, j)); } } #if defined(CONFIG_ARCH_SCX30G) || defined(CONFIG_ARCH_SCX35L) /*timer1 fixed 32768 clk */ sched_clock_source_freq = 32768; #else /*timer2 clk source is from apb clk */ val = sci_glb_read(REG_AON_CLK_AON_APB_CFG, -1) & 0x3; if (val == 0x1) sched_clock_source_freq = 76800000; else if (val == 0x2) sched_clock_source_freq = 96000000; else if (val == 0x3) sched_clock_source_freq = 128000000; else sched_clock_source_freq = 26000000; /*default setting */ #endif gptimer_clock_source_freq = sched_clock_source_freq; #if !defined (CONFIG_HAVE_ARM_ARCH_TIMER) __sched_clock_init(sched_clock_source_freq); #endif } u32 get_sys_cnt(void) { u32 val = 0; val = __raw_readl(SYSCNT_SHADOW_CNT); return val; }
static int32_t sprdfb_lcdc_early_init(struct sprdfb_device *dev) { int ret = 0; pr_debug(KERN_INFO "sprdfb:[%s]\n", __FUNCTION__); if(lcdc_ctx.is_inited){ printk(KERN_WARNING "sprdfb: lcdc early init warning!(has been inited)"); return 0; } lcdc_ctx.clk_lcdc = clk_get(NULL, "clk_lcd"); if (IS_ERR(lcdc_ctx.clk_lcdc)) { printk(KERN_WARNING "sprdfb: get clk_lcd fail!\n"); return 0; } else { pr_debug(KERN_INFO "sprdfb: get clk_lcd ok!\n"); } /*usesd to open dipsc matix clock*/ sci_glb_set(REG_AHB_MATRIX_CLOCK, (1<<LCDC_CORE_CLK_EN)); if(!dev->panel_ready){ ret = clk_enable(lcdc_ctx.clk_lcdc); if (ret) { printk(KERN_WARNING "sprdfb: enable clk_lcdc fail!\n"); return 0; } else { pr_debug(KERN_INFO "sprdfb: get clk_lcdc ok!\n"); } /*dispc must be enbale before lcdc enable*/ sprdfb_dispc_ctrl.early_init(dev); dispc_set_bits(BIT(3), DISPC_CTRL); lcdc_reset(); lcdc_module_enable(); lcdc_ctx.is_first_frame = true; }else{ lcdc_ctx.is_first_frame = false; } lcdc_ctx.vsync_done = 1; lcdc_ctx.vsync_waiter = 0; init_waitqueue_head(&(lcdc_ctx.vsync_queue)); lcdc_ctx.is_inited = true; ret = request_irq(IRQ_LCDC_INT, lcdc_isr, IRQF_DISABLED, "LCDC", &lcdc_ctx); if (ret) { printk(KERN_ERR "sprdfb: lcdc failed to request irq!\n"); clk_disable(lcdc_ctx.clk_lcdc); lcdc_ctx.is_inited = false; return -1; } return 0; }
void usb_phy_ahb_rst(void) { #if defined(CONFIG_ARCH_SCX35) #if defined(CONFIG_ARCH_SCX35L) sci_glb_set(REG_AP_AHB_AHB_RST,BIT(6)); mdelay(3); sci_glb_clr(REG_AP_AHB_AHB_RST,BIT(6)); mdelay(3); sci_glb_set(REG_AP_AHB_OTG_PHY_CTRL,BIT(9)); pr_info("Usb_hw.c: [%s]usb phy tune : 0x%x\n", __FUNCTION__, tune_from_uboot); #else sci_glb_set(REG_AP_AHB_AHB_RST,BIT(7)); mdelay(3); sci_glb_clr(REG_AP_AHB_AHB_RST,BIT(7)); mdelay(3); #endif #endif }
void usb_phy_ahb_rst(void) { #if defined(CONFIG_ARCH_SCX35) sci_glb_set(REG_AP_AHB_AHB_RST,BIT(7)); mdelay(3); sci_glb_clr(REG_AP_AHB_AHB_RST,BIT(7)); mdelay(3); #endif }
static void sdhci_module_init(struct sdhci_host* host) { struct sprd_host_platdata *host_pdata; host_pdata = sdhci_get_platdata(host); sci_glb_set(REG_AP_AHB_AHB_EB, host_pdata->enb_bit); sdhci_sdclk_enable(host, 0); sci_glb_set(REG_AP_AHB_AHB_RST, host_pdata->rst_bit); udelay(200); sci_glb_clr(REG_AP_AHB_AHB_RST, host_pdata->rst_bit); sdhci_sprd_set_base_clock(host); host->ops->set_clock(host, true); }
void enable_cpuidle(int enable) { #if defined(CONFIG_LOCAL_TIMERS) if(enable) sci_glb_set(REG_AHB_AHB_CTL1, BIT_ARM_AUTO_GATE_EN); else sci_glb_clr(REG_AHB_AHB_CTL1, BIT_ARM_AUTO_GATE_EN); #endif }
void __init sprd_init_before_irq(void) { iotable_build(); sc_init_chip_id(); /* earlier init request than irq and timer */ __clock_init_early(); /*ipi reg init for sipc*/ sci_glb_set(REG_AON_APB_APB_EB0, BIT_IPI_EB); }
static void __init sc8830_init_early(void) { /* earlier init request than irq and timer */ __clock_init_early(); sci_enable_timer_early(); sci_adi_init(); /*ipi reg init for sipc*/ sci_glb_set(REG_AON_APB_APB_EB0, BIT_IPI_EB); }
u32 wake_source_stop(void) { //emc_earlysuspend_late_resume(0); sci_glb_set(REG_GLB_GEN0, (1 << 19) | (1 << 27)); raw_reg_clr(SPRD_INTC0_BASE + 8, 1 << 9); raw_reg_set(SPRD_SYSCNT_BASE + 8, 1 << 3); raw_reg_clr(SPRD_SYSCNT_BASE + 8, 1 << 0); }
void __efuse_power_on(void) { u32 cfg0; sci_glb_set(REG_AON_APB_APB_EB0, BIT_EFUSE_EB); cfg0 = __raw_readl((void *)REG_EFUSE_CFG0); cfg0 &= ~BIT_EFS_VDDQ_K1_ON; cfg0 |= BIT_EFS_VDD_ON | BIT_EFS_VDDQ_K2_ON; __raw_writel(cfg0, (void *)REG_EFUSE_CFG0); msleep(1); }