phys_size_t initdram(int board_type)
{
#ifdef CONFIG_DDR_HOST_CC
/* SDRAM size was calculated when compiling. */
#ifndef EMC_LOW_SDRAM_SPACE_SIZE
#define EMC_LOW_SDRAM_SPACE_SIZE 0x10000000 /* 256M */
#endif /* EMC_LOW_SDRAM_SPACE_SIZE */
unsigned int ram_size;
ram_size = (unsigned int)(DDR_CHIP_0_SIZE) + (unsigned int)(DDR_CHIP_1_SIZE);
if (ram_size > EMC_LOW_SDRAM_SPACE_SIZE)
ram_size = EMC_LOW_SDRAM_SPACE_SIZE;
return ram_size;
#elif defined (CONFIG_BURNER)
/* SDRAM size was defined in global info. */
ddr_params_p = &gd->arch.gi->ddr_params;
return ddr_params_p->size.chip0 + ddr_params_p->size.chip1;
#else
ddr_params_p->dw32 = CONFIG_DDR_DW32;
ddr_params_p->bank8 = DDR_BANK8;
ddr_params_p->cs0 = CONFIG_DDR_CS0;
ddr_params_p->cs1 = CONFIG_DDR_CS1;
ddr_params_p->row = DDR_ROW;
ddr_params_p->col = DDR_COL;
#ifdef DDR_ROW1
ddr_params_p->row1 = DDR_ROW1;
#endif
#ifdef DDR_COL1
ddr_params_p->col1 = DDR_COL1;
#endif
return sdram_size(0, ddr_params_p) + sdram_size(1, ddr_params_p);
#endif
}
static void init_4GB_mode(void)
{
if (sdram_size() == (size_t)4 * GiB) {
setbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
setbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
} else {
clrbits_le32(&mt8173_pericfg->axi_bus_ctl3, PERISYS_4G_SUPPORT);
clrbits_le32(&mt8173_infracfg->infra_misc, DDR_4GB_SUPPORT_EN);
}
}
void mt8173_mmu_after_dram(void)
{
/* Map DRAM as cached now that it's up and running */
mmu_config_range(_dram, (uintptr_t)sdram_size(), CACHED_MEM);
/* Unmap L2C SRAM so it can be reclaimed by L2 cache */
/* TODO: Implement true unmapping, and also use it for the zero-page! */
mmu_config_range(_sram_l2c, _sram_l2c_size, DEV_MEM);
mmu_config_range(_dram_dma, _dram_dma_size, UNCACHED_MEM);
/* Careful: changing cache geometry while it's active is a bad idea! */
mmu_disable();
/* Return L2C SRAM back to L2 cache. Set it to 512KiB which is the max
* available L2 cache for A53 in MT8173. */
write32(&mt8173_mcucfg->mp0_ca7l_cache_config, 3 << 8);
/* turn off the l2c sram clock */
write32(&mt8173_infracfg->infra_pdn0, L2C_SRAM_PDN);
/* Reenable MMU with now enlarged L2 cache. Page tables still valid. */
mmu_enable();
}
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
}
/*
* When CONFIG_RAM is enabled, the dram_init() function is implemented
* in sdram_common.c.
*/
int dram_init(void)
{
gd->ram_size = sdram_size();
return 0;
}
