void diu_set_pixel_clock(unsigned int pixclock)
{
unsigned long speed_ccb, temp;
u32 pixval;
int ret = 0;
speed_ccb = get_bus_freq(0);
temp = 1000000000 / pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
/* Program HDMI encoder */
/* Switch channel to DIU */
select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
/* Set dispaly encoder */
ret = diu_set_dvi_encoder(temp);
if (ret) {
puts("Failed to set DVI encoder\n");
return;
}
/* Switch channel to default */
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
/* Program pixel clock */
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
((pixval << PXCK_BITS_START) & PXCK_MASK));
/* enable clock*/
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
((pixval << PXCK_BITS_START) & PXCK_MASK));
}
void board_retimer_init(void)
{
u8 reg;
/* Retimer is connected to I2C1_CH7_CH5 */
select_i2c_ch_pca9547(I2C_MUX_CH7);
reg = I2C_MUX_CH5;
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1);
/* Access to Control/Shared register */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
/* Read device revision and ID */
i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
/* Reset Channel Registers */
i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
reg |= 0x4;
i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
/* Enable override divider select and Enable Override Output Mux */
i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1);
reg |= 0x24;
i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1);
/* Select VCO Divider to full rate (000) */
i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
reg &= 0x8f;
i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1);
/* Selects active PFD MUX Input as Re-timed Data (001) */
i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
reg &= 0x3f;
reg |= 0x20;
i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
reg = 0xb2;
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
reg = 0x90;
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
reg = 0xb3;
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
/* Return the default channel */
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
}
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
erratum_a009942_check_cpo();
#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
}
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
config_serdes_mux();
#endif
ls102xa_smmu_stream_id_init();
#ifdef CONFIG_U_QE
u_qe_init();
#endif
return 0;
}
int board_init(void)
{
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#ifdef CONFIG_FSL_MC_ENET
u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
#endif
u32 val;
init_final_memctl_regs();
val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
env_hwconfig = getenv("hwconfig");
if (hwconfig_f("dspi", env_hwconfig) &&
DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
config_board_mux(MUX_TYPE_DSPI);
else
config_board_mux(MUX_TYPE_SDHC);
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
#ifdef CONFIG_FSL_MC_ENET
/* invert AQR405 IRQ pins polarity */
out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
#endif
return 0;
}
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
CONFIG_SYS_CCI400_ADDR;
/* Set CCI-400 control override register to enable barrier
* transaction */
out_le32(&cci->ctrl_ord,
CCI400_CTRLORD_EN_BARRIER);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();
#endif
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
brd_mux_lane_to_slot();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
}
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to
* enable barrier transaction */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
}
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
config_serdes_mux();
#endif
ls1021x_config_caam_stream_id(sec_liodn_tbl,
ARRAY_SIZE(sec_liodn_tbl));
ls102xa_config_smmu_stream_id(dev_stream_id,
ARRAY_SIZE(dev_stream_id));
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_U_QE
u_qe_init();
#endif
return 0;
}
int dram_init(void)
{
/*
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return fsl_initdram();
}
int board_init(void)
{
init_final_memctl_regs();
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
return 0;
}
int board_init(void)
{
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();
#endif
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
return 0;
}
int dram_init(void)
{
/*
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
fsl_initdram();
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* This will break-before-make MMU for DDR */
update_early_mmu_table();
#endif
return 0;
}
int board_init(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();
#endif
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
return 0;
}
int board_early_init_r(void)
{
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
*/
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
brd_mux_lane_to_slot();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
}
int board_init(void)
{
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();
#endif
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
#ifdef CONFIG_FSL_LS_PPA
ppa_init();
#endif
#ifdef CONFIG_SECURE_BOOT
/*
* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
* SMMU must be reset in bypass mode.
* Set the ClientPD bit and Clear the USFCFG Bit
*/
u32 val;
val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_SCR0, val);
val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
out_le32(SMMU_NSCR0, val);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
return 0;
}
int i2c_multiplexer_select_vid_channel(u8 channel)
{
return select_i2c_ch_pca9547(channel);
}
/* Programming of HDMI Chrontel CH7301 connector */
int diu_set_dvi_encoder(unsigned int pixclock)
{
int ret;
u8 temp;
select_i2c_ch_pca9547(I2C_MUX_CH_DIU);
temp = I2C_DVI_TEST_PATTERN_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
&temp, 1);
if (ret) {
puts("I2C: failed to select proper dvi test pattern\n");
return ret;
}
temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi input data format\n");
return ret;
}
/* Set Sync polarity register */
temp = I2C_DVI_SYNC_POLARITY_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
&temp, 1);
if (ret) {
puts("I2C: failed to select dvi syc polarity\n");
return ret;
}
/* Set PLL registers based on pixel clock rate*/
if (pixclock > 65000000) {
temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll charge_cntl\n");
return ret;
}
temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll divider\n");
return ret;
}
temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll filter\n");
return ret;
}
} else {
temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll charge_cntl\n");
return ret;
}
temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll divider\n");
return ret;
}
temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll filter\n");
return ret;
}
}
temp = I2C_DVI_POWER_MGMT_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
&temp, 1);
if (ret) {
puts("I2C: failed to select dvi power mgmt\n");
return ret;
}
udelay(500);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
return 0;
}
