void ps1_write(uint16_t port, uint8_t val, void *p)
{
switch (port)
{
case 0x0092:
ps1_92 = val;
mem_a20_alt = val & 2;
mem_a20_recalc();
break;
case 0x94:
ps1_94 = val;
break;
case 0x102:
lpt1_remove();
if (val & 0x04)
serial1_init(0x3f8, 4);
else
serial1_remove();
if (val & 0x10)
{
switch ((val >> 5) & 3)
{
case 0:
lpt1_init(0x3bc);
break;
case 1:
lpt1_init(0x378);
break;
case 2:
lpt1_init(0x278);
break;
}
}
ps1_102 = val;
break;
case 0x103:
ps1_103 = val;
break;
case 0x104:
ps1_104 = val;
break;
case 0x105:
ps1_105 = val;
break;
case 0x190:
ps1_190 = val;
break;
case 0x322:
ps1_hd.ctrl = val;
if (val & 0x80)
ps1_hd.status |= 0x02;
break;
case 0x324:
ps1_hd.attention = val & 0xf0;
if (ps1_hd.attention)
ps1_hd.status = 0x14;
break;
}
}
void serial1_set(uint16_t addr, int irq)
{
serial1_remove();
io_sethandler(addr, 0x0008, serial_read, NULL, NULL, serial_write, NULL, NULL, &serial1);
serial1.irq = irq;
serial1.addr = addr;
}
void ps1mb_init()
{
io_sethandler(0x0091, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0092, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0094, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0102, 0x0004, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0190, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0320, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0322, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
io_sethandler(0x0324, 0x0001, ps1_read, NULL, NULL, ps1_write, NULL, NULL, NULL);
rom_init(&ps1_high_rom,
"roms/ibmps1es/f80000.bin",
0xf80000,
0x80000,
0x7ffff,
0,
MEM_MAPPING_EXTERNAL);
/* rom_init_interleaved(&ps1_high_rom,
"roms/ibmps1es/ibm_1057757_24-05-90.bin",
"roms/ibmps1es/ibm_1057757_29-15-90.bin",
0xfc0000,
0x40000,
0x3ffff,
0,
MEM_MAPPING_EXTERNAL);*/
ps1_190 = 0;
lpt1_remove();
lpt2_remove();
lpt1_init(0x3bc);
serial1_remove();
serial2_remove();
memset(&ps1_hd, 0, sizeof(ps1_hd));
}
void sis85c471_write(uint16_t port, uint8_t val, void *priv)
{
uint8_t index = (port & 1) ? 0 : 1;
int temp;
uint8_t x;
#ifndef RELEASE_BUILD
pclog("sis85c471_write : port=%04x reg %02X = %02X\n", port, sis85c471_curreg, val);
#endif
if (index)
{
if ((val >= 0x50) && (val <= 0x76)) sis85c471_curreg = val;
return;
}
else
{
if ((sis85c471_curreg < 0x50) || (sis85c471_curreg > 0x76)) return;
x = val ^ sis85c471_regs[sis85c471_curreg - 0x50];
/* Writes to 0x52 are blocked as otherwise, large hard disks don't read correctly. */
if (sis85c471_curreg != 0x52) sis85c471_regs[sis85c471_curreg - 0x50] = val;
goto process_value;
}
return;
process_value:
switch(sis85c471_curreg)
{
case 0x73:
#if 0
if (x & 0x40)
{
if (val & 0x40)
ide_pri_enable();
else
ide_pri_disable();
}
#endif
if (x & 0x20)
{
if (val & 0x20)
{
serial1_init(0x3f8, 4);
serial2_init(0x2f8, 3);
mouse_serial_init();
}
else
{
serial1_remove();
serial2_remove();
}
}
if (x & 0x10)
{
if (val & 0x10)
lpt1_init(0x378);
else
lpt1_remove();
}
break;
}
sis85c471_curreg = 0;
}
