void Config_DSK6713_AIC23(void)
{
/* Handle für Steuerkanal */
MCBSP_Handle hMcbsp0;
unsigned short i;
hMcbsp0 = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); /*************/
MCBSP_config(hMcbsp0, &mcbspforAIC23Cfg); /*************/
MCBSP_start(hMcbsp0, MCBSP_XMIT_START | MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 220);
/* jetzt alle Register konfigurieren */
/* ein Reset am Anfang ist immer gut, Register 15 --> 0 */
/* die 0 haben wir uns gespart, nach AIC23_registers aufzunehmen */
set_aic23_register(hMcbsp0,15,0);
/* power-down Register zuerst */
set_aic23_register(hMcbsp0,6,myAIC23_registers[6]);
/* jetzt die anderen */
for (i = 0; i < 6; i++)
set_aic23_register(hMcbsp0,i,myAIC23_registers[i]);
for (i = 7; i < 10; i++)
set_aic23_register(hMcbsp0,i,myAIC23_registers[i]);
/* fertig, aber MCBSP nicht schließen, sonst kein Takt an Codec!*/
}
void DSK6713_configure_AIC23() {
/* Configure McBSP0 as control interface for aic23 */
MCBSP_Handle MCBSP0_handle;
MCBSP0_handle = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET);
MCBSP_config(MCBSP0_handle, &MCBSP0_config);
MCBSP_start(MCBSP0_handle, MCBSP_XMIT_START | MCBSP_SRGR_START | MCBSP_SRGR_START, 220);
set_aic23_register(MCBSP0_handle, RESET_REGISTER, 0x0000);
set_aic23_register(MCBSP0_handle, POWER_DOWN_CONTROL, 0x0000);
set_aic23_register(MCBSP0_handle, LEFT_LINE_INPUT_CHANNEL_VOLUME, 0x0017);
set_aic23_register(MCBSP0_handle, RIGHT_LINE_INPUT_CHANNEL_VOLUME, 0x0017);
set_aic23_register(MCBSP0_handle, LEFT_CHANNEL_HEADPHONE_VOLUME, 0x00f9);
set_aic23_register(MCBSP0_handle, RIGHT_CHANNEL_HEADPHONE_VOLUME, 0x00f9);
set_aic23_register(MCBSP0_handle, ANALOG_AUDIO_PATH, 0x0011); // 00001 0010
set_aic23_register(MCBSP0_handle, DIGITAL_AUDIO_PATH, 0x0000); // 000000000
set_aic23_register(MCBSP0_handle, DIGITAL_AUDIO_INTERFACE_FORMAT, 0x0043); //0 0100 0001
set_aic23_register(MCBSP0_handle, SAMPLE_RATE_CONTROL, 0x000d); // 01100
set_aic23_register(MCBSP0_handle, DIGITAL_INTERFACE_ACTIVATION, 0x0001);
/* Configure McBSP1 as data interface for aic23 */
MCBSP_Handle MCBSP1_handle;
MCBSP1_handle = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET);
MCBSP_config(MCBSP1_handle, &MCBSP1_config);
MCBSP_start(MCBSP1_handle, MCBSP_XMIT_START|MCBSP_RCV_START|MCBSP_SRGR_FRAMESYNC|MCBSP_SRGR_START, 220);
/* Configure receive EDMA */
EDMA_Handle hEdmaRcv;
EDMA_Handle hEdmaRcvA;
EDMA_Handle hEdmaRcvB;
hEdmaRcv = EDMA_open(EDMA_CHA_REVT1, EDMA_OPEN_RESET);
hEdmaRcvA = EDMA_allocTable(-1);
hEdmaRcvB = EDMA_allocTable(-1);
gEdmaRcvConfig.src = MCBSP_getRcvAddr(MCBSP1_handle); // Get address of DRR
gTccRcvChan = EDMA_intAlloc(-1); // get next free transfer complete code
gEdmaRcvConfig.opt |= EDMA_FMK(OPT, TCC, gTccRcvChan);
EDMA_config(hEdmaRcv, &gEdmaRcvConfig);
EDMA_config(hEdmaRcvA, &gEdmaRcvConfig);
gEdmaRcvConfig.dst = EDMA_DST_OF(gRcvBufferB);
EDMA_config(hEdmaRcvB, &gEdmaRcvConfig);
EDMA_link(hEdmaRcv, hEdmaRcvB);
EDMA_link(hEdmaRcvB, hEdmaRcvA);
EDMA_link(hEdmaRcvA, hEdmaRcvB);
/* Configure transmit EDMA */
EDMA_Handle hEdmaXmt;
EDMA_Handle hEdmaXmtA;
EDMA_Handle hEdmaXmtB;
hEdmaXmt = EDMA_open(EDMA_CHA_XEVT1, EDMA_OPEN_RESET);
hEdmaXmtA = EDMA_allocTable(-1);
hEdmaXmtB = EDMA_allocTable(-1);
gEdmaXmtConfig.dst = MCBSP_getXmtAddr(MCBSP1_handle); // Get address of DXR
gTccXmtChan = EDMA_intAlloc(-1); // get next free transfer complete code
gEdmaXmtConfig.opt |= EDMA_FMK(OPT, TCC, gTccXmtChan);
EDMA_config(hEdmaXmt, &gEdmaXmtConfig);
EDMA_config(hEdmaXmtA, &gEdmaXmtConfig);
gEdmaXmtConfig.src = EDMA_DST_OF(gXmtBufferB); // set source to buffer B
EDMA_config(hEdmaXmtB, &gEdmaXmtConfig);
EDMA_link(hEdmaXmt, hEdmaXmtB);
EDMA_link(hEdmaXmtB, hEdmaXmtA);
EDMA_link(hEdmaXmtA, hEdmaXmtB);
EDMA_intClear(gTccRcvChan);
EDMA_intClear(gTccXmtChan);
EDMA_intEnable(gTccRcvChan);
EDMA_intEnable(gTccXmtChan);
gBufferState.cpuBufferState = StateB; // inittial cpu buffer state
EDMA_enableChannel(hEdmaRcv);
EDMA_enableChannel(hEdmaXmt);
IRQ_clear(IRQ_EVT_EDMAINT);
IRQ_enable(IRQ_EVT_EDMAINT);
MCBSP_write(MCBSP1_handle, 0x00);
}