static int saradc_internal_cal(struct saradc *saradc)
{
int i;
int voltage[] = {CAL_VOLTAGE_1, CAL_VOLTAGE_2, CAL_VOLTAGE_3, CAL_VOLTAGE_4, CAL_VOLTAGE_5};
int nominal[INTERNAL_CAL_NUM] = {0, 256, 512, 768, 1023};
int val[INTERNAL_CAL_NUM];
// set_cal_mux(MUX_CAL);
// enable_cal_res_array();
for (i=0; i<INTERNAL_CAL_NUM; i++) {
set_cal_voltage(voltage[i]);
msleep(20);
val[i] = get_adc_sample(CHAN_7);
if (val[i] < 0) {
return -1;
}
}
saradc->ref_val = val[2];
saradc->ref_nominal = nominal[2];
saradc->coef = (nominal[3] - nominal[1]) << 12;
saradc->coef /= val[3] - val[1];
printk("saradc calibration: ref_val = %d\n", saradc->ref_val);
printk("saradc calibration: ref_nominal = %d\n", saradc->ref_nominal);
printk("saradc calibration: coef = %d\n", saradc->coef);
return 0;
}
static int saradc_internal_cal(struct calibration *cal)
{
return -1;
int i;
int voltage[4] = {CAL_0P55V, CAL_1P10V, CAL_1P65V, CAL_2P20V};
cal->ref = 0;
(cal+1)->ref = 170;
(cal+2)->ref = 341;
(cal+3)->ref = 511;
(cal+4)->ref = 684;
(cal+5)->ref = 1023;
set_cal_mux(MUX_CAL);
enable_cal_res_array();
for (i=1; i<5; i++) {
set_cal_voltage(voltage[i]);
(cal+i)->val = get_adc_sample(-1);
if ((cal+i)->val < 0) {
printk(KERN_INFO "saradc calibration fail\n");
return -1;
}
}
printk(KERN_INFO "saradc calibration ok\n");
return 0;
}
void saradc_enable(void)
{
int i;
enable_bandgap();
set_clock_src(0); //0-xtal, 1-clk81
//set adc clock as 1.28Mhz @sys=27MHz
set_clock_divider(20);
enable_clock();
enable_adc();
set_sample_mode(DIFF_MODE);
set_tempsen(0);
disable_fifo_irq();
disable_continuous_sample();
disable_chan0_delta();
disable_chan1_delta();
set_input_delay(10, INPUT_DELAY_TB_1US);
set_sample_delay(10, SAMPLE_DELAY_TB_1US);
set_block_delay(10, BLOCK_DELAY_TB_1US);
// channels sampling mode setting
for(i=0; i<AML_ADC_SARADC_CHAN_NUM; i++) {
set_sample_sw(i, IDLE_SW);
set_sample_mux(i, g_chan_mux[i]);
}
// idle mode setting
set_idle_sw(IDLE_SW);
set_idle_mux(g_chan_mux[AML_ADC_CHAN_0]);
// detect mode setting
set_detect_sw(DETECT_SW);
set_detect_mux(g_chan_mux[AML_ADC_CHAN_0]);
disable_detect_sw();
disable_detect_pullup();
set_detect_irq_pol(0);
disable_detect_irq();
set_cal_voltage(7);
enable_sample_engine();
#if AML_ADC_SAMPLE_DEBUG
printf("ADCREG reg0 =%x\n", get_reg(PP_SAR_ADC_REG0));
printf("ADCREG ch list =%x\n",get_reg(PP_SAR_ADC_CHAN_LIST));
printf("ADCREG avg =%x\n", get_reg(PP_SAR_ADC_AVG_CNTL));
printf("ADCREG reg3 =%x\n", get_reg(PP_SAR_ADC_REG3));
printf("ADCREG ch72 sw =%x\n",get_reg(PP_SAR_ADC_AUX_SW));
printf("ADCREG ch10 sw =%x\n",get_reg(PP_SAR_ADC_CHAN_10_SW));
printf("ADCREG detect&idle=%x\n",get_reg(PP_SAR_ADC_DETECT_IDLE_SW));
#endif //AML_ADC_SAMPLE_DEBUG
select_temp();
enable_temp();
enable_temp__();
udelay(1000);
}
static void saradc_init(void)
{
int i;
enable_bandgap();
//low speed, set to clk81 without division
set_clock_src(1); //0-xtal, 1-clk81
set_clock_divider(0);
enable_clock();
enable_adc();
set_sample_mode(DIFF_MODE);
set_tempsen(0);
disable_fifo_irq();
disable_continuous_sample();
disable_chan0_delta();
disable_chan1_delta();
set_input_delay(10, INPUT_DELAY_TB_1US);
set_sample_delay(10, SAMPLE_DELAY_TB_1US);
set_block_delay(10, BLOCK_DELAY_TB_1US);
aml_set_reg32_bits(P_AO_SAR_ADC_DELAY, 3, 27, 2);
// channels sampling mode setting
for(i=0; i<AML_ADC_SARADC_CHAN_NUM; i++) {
set_sample_sw(i, IDLE_SW);
set_sample_mux(i, g_chan_mux[i]);
}
// idle mode setting
set_idle_sw(IDLE_SW);
set_idle_mux(g_chan_mux[AML_ADC_CHAN_0]);
// detect mode setting
set_detect_sw(DETECT_SW);
set_detect_mux(g_chan_mux[AML_ADC_CHAN_0]);
disable_detect_sw();
disable_detect_pullup();
set_detect_irq_pol(0);
disable_detect_irq();
set_cal_voltage(7);
set_sc_phase();
enable_sample_engine();
udelay(1000);
while (get_fifo_cnt()) {
i = get_fifo_sample() & 0x3ff;
}
}