/* Driver API */
DRIVER_API_RC soc_i2s_init()
{
int i;
uint32_t reg;
// Prep info struct
for (i = 0; i < I2S_NUM_CHANNELS; i++)
{
i2s_info->en[i] = 0;
i2s_info->cfgd[i] = 0;
i2s_info->cfg[i].cb_done = NULL;
i2s_info->cfg[i].cb_err = NULL;
}
// Enable global clock, use local clock gating per channel instead
set_clock_gate(i2s_info->clk_gate_info, CLK_GATE_ON);
// Setup ISR (and enable)
SET_INTERRUPT_HANDLER(i2s_info->int_vector, i2s_interrupt_handler);
SOC_UNMASK_INTERRUPTS(i2s_info->int_mask);
// Set up control register
reg = MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_CTRL);
reg |= (1 << SOC_I2S_CTRL_TR_CFG_0);
reg &= ~(1 << SOC_I2S_CTRL_TSYNC_LOOP_BACK);
reg &= ~(1 << SOC_I2S_CTRL_RSYNC_LOOP_BACK);
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_CTRL) = reg;
// Set the watermark levels
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_TFIFO_CTRL) &= 0xFFFCFFFF;
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_TFIFO_CTRL) |= (I2S_TFIFO_THR << SOC_I2S_TFIFO_CTRL_TAFULL_THRS);
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_RFIFO_CTRL) &= 0xFFFCFFFF;
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_RFIFO_CTRL) |= (I2S_RFIFO_THR << SOC_I2S_RFIFO_CTRL_RAFULL_THRS);
// Enable global interrupt mask
reg = MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_CID_CTRL);
reg |= (1 << SOC_I2S_CID_CTRL_INTREQ_MASK);
MMIO_REG_VAL_FROM_BASE(SOC_I2S_BASE, SOC_I2S_CID_CTRL) = reg;
// Initially, have all channels disabled
for (i = 0; i < I2S_NUM_CHANNELS; i++)
{
i2s_disable(i);
}
return DRV_RC_OK;
}
static int clk_system_driver_init(struct device *dev)
{
set_clock_gate(dev->priv, CLK_GATE_OFF);
return 0;
}
/*! \fn void qrk_cxxxx_rtc_enable(void)
*
* \brief Function to enable clock gating for the RTC
*/
static void qrk_cxxxx_rtc_enable(struct device *rtc_dev)
{
set_clock_gate(&rtc_clk_gate_info, CLK_GATE_ON);
}
/*! \fn void qrk_cxxxx_rtc_disable(void)
*
* \brief Function to enable clock gating for the RTC
*/
void qrk_cxxxx_rtc_disable(struct device *dev)
{
struct rtc_pm_data *info = dev->priv;
set_clock_gate(info->clk_gate_info, CLK_GATE_OFF);
}
/*! \fn void qrk_cxxxx_rtc_disable(void)
*
* \brief Function to enable clock gating for the RTC
*/
void qrk_cxxxx_rtc_disable(struct device *rtc_dev)
{
MMIO_REG_VAL_FROM_BASE(QRK_RTC_BASE_ADDR,
QRK_RTC_CCR) &= ~QRK_RTC_ENABLE;
set_clock_gate(&rtc_clk_gate_info, CLK_GATE_OFF);
}