static void sensor_reset(void)
{
DBG_INFO("");
set_gpio_level(&g_spinfo.gpio_reset, 1);
mdelay(10);
set_gpio_level(&g_spinfo.gpio_reset, 0);
mdelay(10);
}
static void sensor_power(bool front, bool on)
{
DBG_INFO("%s sensor power %s", front ? "front" : "rear", on ? "on" : "off");
if (front) {
set_gpio_level(&g_spinfo.gpio_front, !on);
sensor_reset();
} else {
set_gpio_level(&g_spinfo.gpio_rear, !on);
}
mdelay(10);
}
static int camera_detect_resume(struct platform_device *pdev)
{
DBG_INFO("");
set_gpio_level(&g_spinfo.gpio_front, 1);
set_gpio_level(&g_spinfo.gpio_rear, 1);
set_gpio_level(&g_spinfo.gpio_reset, 0);
isp_regulator_enable(&g_isp_ir);
if((!g_front_detected || !g_rear_detected) && ( hot_plug_enable))
{
schedule_delayed_work(&g_work, DELAY_INTERVAL);
}
return 0;
}
static int camera_detect_suspend(struct platform_device *pdev, pm_message_t m)
{
DBG_INFO("");
if((!g_front_detected || !g_rear_detected) && ( hot_plug_enable))
{
cancel_delayed_work_sync(&g_work);
}
isp_regulator_disable(&g_isp_ir);
set_gpio_level(&g_spinfo.gpio_front, 0);
set_gpio_level(&g_spinfo.gpio_rear, 0);
set_gpio_level(&g_spinfo.gpio_reset, 1);
return 0;
}
static int gpio_init(struct device_node *fdt_node,
const char *gpio_name, struct dts_gpio *gpio, bool active)
{
enum of_gpio_flags flags;
if (!of_find_property(fdt_node, gpio_name, NULL)) {
DBG_ERR("no config gpios:%s", gpio_name);
goto fail;
}
gpio->num = of_get_named_gpio_flags(fdt_node, gpio_name, 0, &flags);
gpio->active_level = !(flags & OF_GPIO_ACTIVE_LOW);
DBG_INFO("%s: num-%d, active-%s", gpio_name, gpio->num, gpio->active_level ? "high" : "low");
if (gpio_request(gpio->num, gpio_name)) {
DBG_ERR("fail to request gpio [%d]", gpio->num);
gpio->num = -1;
goto fail;
}
set_gpio_level(gpio, active);
DBG_INFO("gpio value: 0x%x", gpio_get_value(gpio->num));
return 0;
fail:
return -1;
}
static void gpio_exit(struct dts_gpio *gpio, bool active)
{
DBG_INFO("gpio free:%d", gpio->num);
if (gpio->num >= 0) {
set_gpio_level(gpio, active);
gpio_free(gpio->num);
}
}
static void isp_regulator_disable(struct isp_regulators *ir)
{
DBG_INFO("");
if (ir->dvdd_use_gpio) {
set_gpio_level(&ir->dvdd_gpio, 0);
}
if (ir->dvdd.regul) {
regulator_disable(ir->dvdd.regul);
}
if (ir->avdd_use_gpio) {
set_gpio_level(&ir->avdd.gpio, 0);
} else {
struct dts_regulator *dr = &ir->avdd.regul;
if (dr->regul) {
regulator_disable(dr->regul);
}
}
}
static void isp_regulator_enable(struct isp_regulators *ir)
{
int ret = 0;
DBG_INFO("");
if (ir->dvdd.regul) {
ret = regulator_enable(ir->dvdd.regul);
mdelay(5);
}
if (ir->avdd_use_gpio) {
set_gpio_level(&ir->avdd.gpio, 1);
} else {
struct dts_regulator *dr = &ir->avdd.regul;
if (dr->regul) {
ret = regulator_enable(dr->regul);
mdelay(5);
}
}
if (ir->dvdd_use_gpio) {
set_gpio_level(&ir->dvdd_gpio, 1);
}
}
uint8_t u8g_com_hw_spi_fn(u8g_t *u8g, uint8_t msg, uint8_t arg_val, void *arg_ptr)
{
switch(msg)
{
case U8G_COM_MSG_STOP:
break;
case U8G_COM_MSG_INIT:
if ( arg_val <= U8G_SPI_CLK_CYCLE_50NS )
{
spi_init(SPI_BAUDRATEPRESCALER_2);
}
else if ( arg_val <= U8G_SPI_CLK_CYCLE_300NS )
{
spi_init(SPI_BAUDRATEPRESCALER_4);
}
else if ( arg_val <= U8G_SPI_CLK_CYCLE_400NS )
{
spi_init(SPI_BAUDRATEPRESCALER_4);
}
else
{
spi_init(SPI_BAUDRATEPRESCALER_8);
}
u8g_MicroDelay();
break;
case U8G_COM_MSG_ADDRESS: /* define cmd (arg_val = 0) or data mode (arg_val = 1) */
u8g_10MicroDelay();
set_gpio_level(LCD_CD_PIN, arg_val);
u8g_10MicroDelay();
break;
case U8G_COM_MSG_CHIP_SELECT:
if ( arg_val == 0 )
{
/* disable */
uint8_t i;
/* this delay is required to avoid that the display is switched off too early --> DOGS102 with LPC1114 */
for( i = 0; i < 5; i++ )u8g_10MicroDelay();
set_gpio_level(LCD_CS_PIN, 1);
}
else
{
/* enable */
set_gpio_level(LCD_CS_PIN, 0);
}
u8g_MicroDelay();
break;
case U8G_COM_MSG_RESET:
set_gpio_level(LCD_RST_PIN, arg_val);
u8g_10MicroDelay();
break;
case U8G_COM_MSG_WRITE_BYTE:
spi_out(arg_val);
u8g_MicroDelay();
break;
case U8G_COM_MSG_WRITE_SEQ:
case U8G_COM_MSG_WRITE_SEQ_P:
{
register uint8_t *ptr = arg_ptr;
while( arg_val > 0 )
{
spi_out(*ptr++);
arg_val--;
}
}
break;
}
return 1;
}
