int s5p_usb_phy_init(struct platform_device *pdev, int type)
{
int ret = -EINVAL;
if (exynos_usb_phy_clock_enable(pdev))
return ret;
mutex_lock(&phy_lock);
if (type == S5P_USB_PHY_HOST) {
if (!strcmp(pdev->name, "s5p-ehci"))
set_bit(HOST_PHY_EHCI, &usb_phy_control.flags);
else if (!strcmp(pdev->name, "s5p-ohci"))
set_bit(HOST_PHY_OHCI, &usb_phy_control.flags);
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \
|| defined(CONFIG_MDM_HSIC_PM)
/* HSIC LPA: Let CP know the slave wakeup from LPA wakeup */
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_PHY_INIT);
#endif
if (soc_is_exynos4210())
ret = exynos4_usb_phy1_init(pdev);
else if (soc_is_exynos4212() || soc_is_exynos4412()) {
ret = exynos4_usb_phy20_init(pdev);
set_exynos_usb_phy_tune(type);
} else
ret = exynos5_usb_phy20_init(pdev);
} else if (type == S5P_USB_PHY_DEVICE) {
if (soc_is_exynos4210())
ret = exynos4_usb_phy0_init(pdev);
else {
ret = exynos_usb_dev_phy20_init(pdev);
set_exynos_usb_phy_tune(type);
}
/* set custom usb phy tune */
if (pdev->dev.platform_data)
ret = s5p_usb_phy0_tune(pdev->dev.platform_data, 0);
} else if (type == S5P_USB_PHY_OTGHOST) {
if (soc_is_exynos4210())
ret = exynos4_usb_phy0_init(pdev);
else
ret = exynos_usb_dev_phy20_init(pdev);
} else if (type == S5P_USB_PHY_DRD)
ret = exynos5_usb_phy30_init(pdev);
mutex_unlock(&phy_lock);
exynos_usb_phy_clock_disable(pdev);
return ret;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
u32 rstcon;
u32 phypwr;
int err;
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: reset-resume, let cp know pda active from LPA */
/* slave wake at lpa wake ??? */
/* 12.04.27 Move start of phy1_resume, If usb cable power on the
* host phy, EHCI resume miss the PDA_ACTVIE, then CP can't send Host
* wakeup Irq */
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
if (usb_phy_control.lpa_entered) {
usb_phy_control.lpa_entered = 0;
err = 1;
} else
err = 0;
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* set to normal of Host */
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
usb_phy_control.lpa_entered = 0;
err = 1;
}
udelay(80);
return err;
}
int exynos4_check_usb_op(void)
{
u32 phypwr;
u32 op = 1;
unsigned long flags;
int ret;
ret = clk_enable(phy_clk);
if (ret)
return 0;
local_irq_save(flags);
phypwr = readl(EXYNOS4_PHYPWR);
/*If USB Device is power on, */
if (exynos_usb_device_phy_is_on()) {
op = 1;
goto done;
} else if (!exynos4_usb_host_phy_is_on()) {
op = 0;
goto done;
}
/*If USB Device & Host is suspended, */
if (soc_is_exynos4210()) {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND)) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: LPA USB phy retention reume call the usb
* reset resume, so we should let CP to HSIC L3 mode. */
set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
#endif
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
writel(PHY_DISABLE, S5P_USBHOST_PHY_CONTROL);
op = 0;
}
} else {
if (phypwr & (PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND)) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB)
/* HSIC LPA: LPA USB phy retention reume call the usb
* reset resume, so we should let CP to HSIC L3 mode. */
set_hsic_lpa_states(STATE_HSIC_LPA_ENTER);
#endif
/* unset to normal of Host */
writel(readl(EXYNOS4_PHYPWR)
| PHY1_STD_ANALOG_POWERDOWN
| EXYNOS4212_HSIC0_ANALOG_POWERDOWN
| EXYNOS4212_HSIC1_ANALOG_POWERDOWN,
EXYNOS4_PHYPWR);
/* unset to normal of Device */
writel((readl(EXYNOS4_PHYPWR) | PHY0_NORMAL_MASK),
EXYNOS4_PHYPWR);
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_DISABLE);
op = 0;
usb_phy_control.lpa_entered = 1;
}
}
done:
local_irq_restore(flags);
clk_disable(phy_clk);
return op;
}
static int exynos4_usb_phy1_resume(struct platform_device *pdev)
{
u32 rstcon;
u32 phypwr;
int err;
if (exynos4_usb_host_phy_is_on()) {
/* set to resume HSIC 0 and 1 and standard of PHY1 */
phypwr = readl(EXYNOS4_PHYPWR);
if (soc_is_exynos4210()) {
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4210_HSIC0_FORCE_SUSPEND
| EXYNOS4210_HSIC1_FORCE_SUSPEND);
} else {
phypwr = readl(EXYNOS4_PHYPWR);
phypwr &= ~(PHY1_STD_FORCE_SUSPEND
| EXYNOS4212_HSIC0_FORCE_SUSPEND
| EXYNOS4212_HSIC1_FORCE_SUSPEND);
}
writel(phypwr, EXYNOS4_PHYPWR);
if (usb_phy_control.lpa_entered) {
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \
|| defined(CONFIG_MDM_HSIC_PM)
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif
usb_phy_control.lpa_entered = 0;
err = 1;
} else {
err = 0;
}
} else {
phypwr = readl(EXYNOS4_PHYPWR);
/* set to normal HSIC 0 and 1 of PHY1 */
if (soc_is_exynos4210()) {
writel(PHY_ENABLE, S5P_USBHOST_PHY_CONTROL);
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4210_HSIC0_NORMAL_MASK
| EXYNOS4210_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4210_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4210_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
} else {
exynos_usb_phy_control(USB_PHY
| USB_PHY_HSIC0
| USB_PHY_HSIC1,
PHY_ENABLE);
/* set to normal of Device */
phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK;
writel(phypwr, EXYNOS4_PHYPWR);
/* reset both PHY and Link of Device */
rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~PHY0_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
/* set to normal of Host */
phypwr &= ~(PHY1_STD_NORMAL_MASK
| EXYNOS4212_HSIC0_NORMAL_MASK
| EXYNOS4212_HSIC1_NORMAL_MASK);
writel(phypwr, EXYNOS4_PHYPWR);
/* reset all ports of both PHY and Link */
rstcon = readl(EXYNOS4_RSTCON)
| EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK;
writel(rstcon, EXYNOS4_RSTCON);
udelay(10);
rstcon &= ~(EXYNOS4212_HOST_LINK_PORT_SWRST_MASK
| EXYNOS4212_PHY1_SWRST_MASK);
writel(rstcon, EXYNOS4_RSTCON);
}
#if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) \
|| defined(CONFIG_MDM_HSIC_PM)
if (!strcmp(pdev->name, "s5p-ehci"))
set_hsic_lpa_states(STATE_HSIC_LPA_WAKE);
#endif
usb_phy_control.lpa_entered = 0;
err = 1;
}
udelay(80);
return err;
}
