static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O)
{
MCOperand *SegReg;
int reg;
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
SegReg = MCInst_getOperand(MI, Op+1);
reg = MCOperand_getReg(SegReg);
// If this has a segment register, print it.
if (reg) {
_printOperand(MI, Op+1, O);
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
}
SStream_concat0(O, ":");
}
SStream_concat0(O, "[");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier)
{
MCOperand *MO;
set_mem_access(MI, true);
printOperand(MI, opNum, O);
// If this is an ADD operand, emit it like normal operands.
if (Modifier && !strcmp(Modifier, "arith")) {
SStream_concat0(O, ", ");
printOperand(MI, opNum + 1, O);
set_mem_access(MI, false);
return;
}
MO = MCInst_getOperand(MI, opNum + 1);
if (MCOperand_isReg(MO) && (MCOperand_getReg(MO) == SP_G0)) {
set_mem_access(MI, false);
return; // don't print "+%g0"
}
if (MCOperand_isImm(MO) && (MCOperand_getImm(MO) == 0)) {
set_mem_access(MI, false);
return; // don't print "+0"
}
SStream_concat0(O, "+"); // qq
printOperand(MI, opNum + 1, O);
set_mem_access(MI, false);
}
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
}
// DI accesses are always ES-based on non-64bit mode
if (MI->csh->mode != CS_MODE_64) {
SStream_concat0(O, "%es:(");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
}
} else
SStream_concat0(O, "(");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
static void printDstIdx(MCInst *MI, unsigned Op, SStream *O)
{
if (MI->csh->detail) {
#ifndef CAPSTONE_DIET
uint8_t access[6];
#endif
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.index = X86_REG_INVALID;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.scale = 1;
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = 0;
#ifndef CAPSTONE_DIET
get_op_access(MI->csh, MCInst_getOpcode(MI), access, &MI->flat_insn->detail->x86.eflags);
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].access = access[MI->flat_insn->detail->x86.op_count];
#endif
}
// DI accesses are always ES-based on non-64bit mode
if (MI->csh->mode != CS_MODE_64) {
SStream_concat(O, "es:[");
if (MI->csh->detail) {
MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = X86_REG_ES;
}
} else
SStream_concat(O, "[");
set_mem_access(MI, true);
printOperand(MI, Op, O);
SStream_concat0(O, "]");
set_mem_access(MI, false);
}
static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
{
set_mem_access(MI, true);
printBranchOperand(MI, OpNo, O);
SStream_concat(O, "(");
printOperand(MI, OpNo + 1, O);
SStream_concat(O, ")");
set_mem_access(MI, false);
}
static void printMemOperand(MCInst *MI, int opNum, SStream *O)
{
// Load/Store memory operands -- imm($reg)
// If PIC target the target is loaded as the
// pattern lw $25,%call16($28)
set_mem_access(MI, true);
printOperand(MI, opNum + 1, O);
SStream_concat(O, "(");
printOperand(MI, opNum, O);
SStream_concat(O, ")");
set_mem_access(MI, false);
}
static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
{
set_mem_access(MI, true);
//printBranchOperand(MI, OpNo, O);
// On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
// come at the _end_ of the expression.
SStream_concat0(O, "(");
printOperand(MI, OpNo + 1, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
{
set_mem_access(MI, true);
printS16ImmOperand_Mem(MI, OpNo, O);
SStream_concat0(O, "(");
if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0)
SStream_concat0(O, "0");
else
printOperand(MI, OpNo + 1, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
/*
* Set access type for a region of gfns.
* If gfn == INVALID_GFN, sets the default access type.
*/
long p2m_set_mem_access(struct domain *d, gfn_t gfn, uint32_t nr,
uint32_t start, uint32_t mask, xenmem_access_t access,
unsigned int altp2m_idx)
{
struct p2m_domain *p2m = p2m_get_hostp2m(d), *ap2m = NULL;
p2m_access_t a;
unsigned long gfn_l;
long rc = 0;
/* altp2m view 0 is treated as the hostp2m */
if ( altp2m_idx )
{
if ( altp2m_idx >= MAX_ALTP2M ||
d->arch.altp2m_eptp[altp2m_idx] == mfn_x(INVALID_MFN) )
return -EINVAL;
ap2m = d->arch.altp2m_p2m[altp2m_idx];
}
if ( !xenmem_access_to_p2m_access(p2m, access, &a) )
return -EINVAL;
/* If request to set default access. */
if ( gfn_eq(gfn, INVALID_GFN) )
{
p2m->default_access = a;
return 0;
}
p2m_lock(p2m);
if ( ap2m )
p2m_lock(ap2m);
for ( gfn_l = gfn_x(gfn) + start; nr > start; ++gfn_l )
{
rc = set_mem_access(d, p2m, ap2m, a, _gfn(gfn_l));
if ( rc )
break;
/* Check for continuation if it's not the last iteration. */
if ( nr > ++start && !(start & mask) && hypercall_preempt_check() )
{
rc = start;
break;
}
}
if ( ap2m )
p2m_unlock(ap2m);
p2m_unlock(p2m);
return rc;
}
void i860_cpu_device::init() {
/* Configurations - keep in sync with i860cfg.h */
static const char* CFGS[8];
for(int i = 0; i < 8; i++) CFGS[i] = "Unknown emulator configuration";
CFGS[CONF_I860_SPEED] = CONF_STR(CONF_I860_SPEED);
CFGS[CONF_I860_DEV] = CONF_STR(CONF_I860_DEV);
CFGS[CONF_I860_NO_THREAD] = CONF_STR(CONF_I860_NO_THREAD);
Log_Printf(LOG_WARN, "[i860] Emulator configured for %s, %d logical cores detected, %s",
CFGS[CONF_I860], host_num_cpus(),
ConfigureParams.Dimension.bI860Thread ? "using seperate thread for i860" : "i860 running on m68k thread. WARNING: expect slow emulation");
m_single_stepping = 0;
m_lastcmd = 0;
m_console_idx = 0;
m_break_on_next_msg = false;
m_dim = DIM_NONE;
m_traceback_idx = 0;
set_mem_access(false);
// some sanity checks for endianess
int err = 0;
{
UINT32 uint32 = 0x01234567;
UINT8* uint8p = (UINT8*)&uint32;
if(uint8p[3] != 0x01) {err = 1; goto error;}
if(uint8p[2] != 0x23) {err = 2; goto error;}
if(uint8p[1] != 0x45) {err = 3; goto error;}
if(uint8p[0] != 0x67) {err = 4; goto error;}
for(int i = 0; i < 32; i++) {
uint8p[3] = i;
set_fregval_s(i, *((float*)uint8p));
}
if(get_fregval_s(0) != 0) {err = 198; goto error;}
if(get_fregval_s(1) != 0) {err = 199; goto error;}
for(int i = 2; i < 32; i++) {
uint8p[3] = i;
if(get_fregval_s(i) != *((float*)uint8p))
{err = 100+i; goto error;}
}
for(int i = 2; i < 32; i++) {
if(m_fregs[i*4+3] != i) {err = 200+i; goto error;}
if(m_fregs[i*4+2] != 0x23) {err = 200+i; goto error;}
if(m_fregs[i*4+1] != 0x45) {err = 200+i; goto error;}
if(m_fregs[i*4+0] != 0x67) {err = 200+i; goto error;}
}
}
{
UINT64 uint64 = 0x0123456789ABCDEFLL;
UINT8* uint8p = (UINT8*)&uint64;
if(uint8p[7] != 0x01) {err = 10001; goto error;}
if(uint8p[6] != 0x23) {err = 10002; goto error;}
if(uint8p[5] != 0x45) {err = 10003; goto error;}
if(uint8p[4] != 0x67) {err = 10004; goto error;}
if(uint8p[3] != 0x89) {err = 10005; goto error;}
if(uint8p[2] != 0xAB) {err = 10006; goto error;}
if(uint8p[1] != 0xCD) {err = 10007; goto error;}
if(uint8p[0] != 0xEF) {err = 10008; goto error;}
for(int i = 0; i < 16; i++) {
uint8p[7] = i;
set_fregval_d(i*2, *((double*)uint8p));
}
if(get_fregval_d(0) != 0)
{err = 10199; goto error;}
for(int i = 1; i < 16; i++) {
uint8p[7] = i;
if(get_fregval_d(i*2) != *((double*)uint8p))
{err = 10100+i; goto error;}
}
for(int i = 2; i < 32; i += 2) {
float hi = get_fregval_s(i+1);
float lo = get_fregval_s(i+0);
if((*(UINT32*)&hi) != (0x00234567 | (i<<23))) {err = 10100+i; goto error;}
if((*(UINT32*)&lo) != 0x89ABCDEF) {err = 10100+i; goto error;}
}
for(int i = 1; i < 16; i++) {
if(m_fregs[i*8+7] != i) {err = 10200+i; goto error;}
if(m_fregs[i*8+6] != 0x23) {err = 10200+i; goto error;}
if(m_fregs[i*8+5] != 0x45) {err = 10200+i; goto error;}
if(m_fregs[i*8+4] != 0x67) {err = 10200+i; goto error;}
if(m_fregs[i*8+3] != 0x89) {err = 10200+i; goto error;}
if(m_fregs[i*8+2] != 0xAB) {err = 10200+i; goto error;}
if(m_fregs[i*8+1] != 0xCD) {err = 10200+i; goto error;}
if(m_fregs[i*8+0] != 0xEF) {err = 10200+i; goto error;}
}
}
err = memtest(true); if(err) goto error;
err = memtest(false); if(err) goto error;
error:
if(err) {
fprintf(stderr, "NeXTdimension i860 emulator requires a little-endian host. This system seems to be big endian. Error %d. Exiting.\n", err);
fflush(stderr);
exit(err);
}
send_msg(MSG_I860_RESET);
if(ConfigureParams.Dimension.bI860Thread)
m_thread = host_thread_create(i860_thread, this);
}
int i860_cpu_device::memtest(bool be) {
const UINT32 P_TEST_ADDR = 0x28000000; // assume ND in slot 2
m_cregs[CR_DIRBASE] = 0; // turn VM off
const UINT8 uint8 = 0x01;
const UINT16 uint16 = 0x0123;
const UINT32 uint32 = 0x01234567;
const UINT64 uint64 = 0x0123456789ABCDEFLL;
UINT8 tmp8;
UINT16 tmp16;
UINT32 tmp32;
int err = be ? 20000 : 30000;
// intel manual example
SET_EPSR_BE(0);
set_mem_access(false);
tmp8 = 'A'; wrmem[1](P_TEST_ADDR+0, (UINT32*)&tmp8);
tmp8 = 'B'; wrmem[1](P_TEST_ADDR+1, (UINT32*)&tmp8);
tmp8 = 'C'; wrmem[1](P_TEST_ADDR+2, (UINT32*)&tmp8);
tmp8 = 'D'; wrmem[1](P_TEST_ADDR+3, (UINT32*)&tmp8);
tmp8 = 'E'; wrmem[1](P_TEST_ADDR+4, (UINT32*)&tmp8);
tmp8 = 'F'; wrmem[1](P_TEST_ADDR+5, (UINT32*)&tmp8);
tmp8 = 'G'; wrmem[1](P_TEST_ADDR+6, (UINT32*)&tmp8);
tmp8 = 'H'; wrmem[1](P_TEST_ADDR+7, (UINT32*)&tmp8);
rdmem[1](P_TEST_ADDR+0, (UINT32*)&tmp8); if(tmp8 != 'A') return err + 100;
rdmem[1](P_TEST_ADDR+1, (UINT32*)&tmp8); if(tmp8 != 'B') return err + 101;
rdmem[1](P_TEST_ADDR+2, (UINT32*)&tmp8); if(tmp8 != 'C') return err + 102;
rdmem[1](P_TEST_ADDR+3, (UINT32*)&tmp8); if(tmp8 != 'D') return err + 103;
rdmem[1](P_TEST_ADDR+4, (UINT32*)&tmp8); if(tmp8 != 'E') return err + 104;
rdmem[1](P_TEST_ADDR+5, (UINT32*)&tmp8); if(tmp8 != 'F') return err + 105;
rdmem[1](P_TEST_ADDR+6, (UINT32*)&tmp8); if(tmp8 != 'G') return err + 106;
rdmem[1](P_TEST_ADDR+7, (UINT32*)&tmp8); if(tmp8 != 'H') return err + 107;
rdmem[2](P_TEST_ADDR+0, (UINT32*)&tmp16); if(tmp16 != (('B'<<8)|('A'))) return err + 110;
rdmem[2](P_TEST_ADDR+2, (UINT32*)&tmp16); if(tmp16 != (('D'<<8)|('C'))) return err + 111;
rdmem[2](P_TEST_ADDR+4, (UINT32*)&tmp16); if(tmp16 != (('F'<<8)|('E'))) return err + 112;
rdmem[2](P_TEST_ADDR+6, (UINT32*)&tmp16); if(tmp16 != (('H'<<8)|('G'))) return err + 113;
rdmem[4](P_TEST_ADDR+0, &tmp32); if(tmp32 != (('D'<<24)|('C'<<16)|('B'<<8)|('A'))) return err + 120;
rdmem[4](P_TEST_ADDR+4, &tmp32); if(tmp32 != (('H'<<24)|('G'<<16)|('F'<<8)|('E'))) return err + 121;
SET_EPSR_BE(1);
set_mem_access(true);
rdmem[1](P_TEST_ADDR+0, (UINT32*)&tmp8); if(tmp8 != 'H') return err + 200;
rdmem[1](P_TEST_ADDR+1, (UINT32*)&tmp8); if(tmp8 != 'G') return err + 201;
rdmem[1](P_TEST_ADDR+2, (UINT32*)&tmp8); if(tmp8 != 'F') return err + 202;
rdmem[1](P_TEST_ADDR+3, (UINT32*)&tmp8); if(tmp8 != 'E') return err + 203;
rdmem[1](P_TEST_ADDR+4, (UINT32*)&tmp8); if(tmp8 != 'D') return err + 204;
rdmem[1](P_TEST_ADDR+5, (UINT32*)&tmp8); if(tmp8 != 'C') return err + 205;
rdmem[1](P_TEST_ADDR+6, (UINT32*)&tmp8); if(tmp8 != 'B') return err + 206;
rdmem[1](P_TEST_ADDR+7, (UINT32*)&tmp8); if(tmp8 != 'A') return err + 207;
rdmem[2](P_TEST_ADDR+0, (UINT32*)&tmp16); if(tmp16 != (('H'<<8)|('G'))) return err + 210;
rdmem[2](P_TEST_ADDR+2, (UINT32*)&tmp16); if(tmp16 != (('F'<<8)|('E'))) return err + 211;
rdmem[2](P_TEST_ADDR+4, (UINT32*)&tmp16); if(tmp16 != (('D'<<8)|('C'))) return err + 212;
rdmem[2](P_TEST_ADDR+6, (UINT32*)&tmp16); if(tmp16 != (('B'<<8)|('A'))) return err + 213;
rdmem[4](P_TEST_ADDR+0, &tmp32); if(tmp32 != (('H'<<24)|('G'<<16)|('F'<<8)|('E'))) return err + 220;
rdmem[4](P_TEST_ADDR+4, &tmp32); if(tmp32 != (('D'<<24)|('C'<<16)|('B'<<8)|('A'))) return err + 221;
// some register and mem r/w tests
SET_EPSR_BE(be);
set_mem_access(be);
wrmem[1](P_TEST_ADDR, (UINT32*)&uint8);
rdmem[1](P_TEST_ADDR, (UINT32*)&tmp8);
if(tmp8 != 0x01) return err;
wrmem[2](P_TEST_ADDR, (UINT32*)&uint16);
rdmem[2](P_TEST_ADDR, (UINT32*)&tmp16);
if(tmp16 != 0x0123) return err+1;
wrmem[4](P_TEST_ADDR, &uint32);
rdmem[4](P_TEST_ADDR, &tmp32); if(tmp32 != 0x01234567) return err+2;
readmem_emu(P_TEST_ADDR, 4, (UINT8*)&uint32);
if(uint32 != 0x01234567) return err+3;
writemem_emu(P_TEST_ADDR, 4, (UINT8*)&uint32, 0xff);
rdmem[4](P_TEST_ADDR+0, &tmp32); if(tmp32 != 0x01234567) return err+4;
UINT8* uint8p = (UINT8*)&uint64;
set_fregval_d(2, *((double*)uint8p));
writemem_emu(P_TEST_ADDR, 8, &m_fregs[8], 0xff);
readmem_emu (P_TEST_ADDR, 8, &m_fregs[8]);
*((double*)&uint64) = get_fregval_d(2);
if(uint64 != 0x0123456789ABCDEFLL) return err+5;
UINT32 lo;
UINT32 hi;
rdmem[4](P_TEST_ADDR+0, &lo);
rdmem[4](P_TEST_ADDR+4, &hi);
if(lo != 0x01234567) return err+6;
if(hi != 0x89ABCDEF) return err+7;
return 0;
}
