/*****************************************************************
* The sr5650 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
* Space to a 256MB range within the first 4GB of addressable memory.
*****************************************************************/
void enable_pcie_bar3(device_t nb_dev)
{
printk(BIOS_DEBUG, "enable_pcie_bar3()\n");
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */
pci_write_config32(nb_dev, 0x20, 0x00000000);
set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
}
/*
* Enable LCLK clock gating
*/
static void EnableLclkGating(device_t dev)
{
u8 port;
u32 reg = 0;
u32 mask = 0;
u32 value = 0;
device_t nb_dev = dev_find_slot(0, 0);
device_t clk_f1= dev_find_slot(0, 1);
port = dev->path.pci.devfn >> 3;
switch (port) {
//PCIE_CORE_INDEX_GPP1
case 2:
case 3:
reg = 0x94;
mask = 1 << 16;
break;
//PCIE_CORE_INDEX_GPP2
case 11:
case 12:
reg = 0xE8;
value = 1 << 28;
break;
//PCIE_CORE_INDEX_GPP3a
case 4 ... 7:
case 9:
case 10:
reg = 0xE8;
value = 1 << 31;
break;
//PCIE_CORE_INDEX_GPP3b;
case 13:
reg = 0xE8;
value = 1 << 25;
break;
//PCIE_CORE_INDEX_SB;
case 8:
reg = 0x94;
mask = 1 << 24;
break;
default:
break;
}
/* enable access func1 */
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 1 << 0);
set_nbcfg_enable_bits(clk_f1, reg, mask, value);
}
/*****************************************************************
* We should disable bar3 when we want to exit sr5650_enable, because bar3 will be
* remapped in set_resource later.
*****************************************************************/
void disable_pcie_bar3(device_t nb_dev)
{
printk(BIOS_DEBUG, "disable_pcie_bar3()\n");
pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */
ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
}
/*
* nb_lock :
* close or hide unsed modules and lock the whole NB registers
*/
static void nb_lock(void)
{
pcitag_t nb_dev = _pci_make_tag(0, 0, 0);
pcitag_t igfx_dev = _pci_make_tag(1, 5, 0);
u32 base;
u32 val;
/* enable 2D optimization as configured */
if(ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)){
if( (!(ati_nb_cfg.ext_config & EXT_DEBUG_GFX32BIT_MODE)) && (ati_nb_cfg.gfx_config & GFX_2D_OPTIMIZATION) ){
base = (_pci_conf_read(igfx_dev, 0x18) & 0xfffffff0) | 0xA0000000;
if(base){
/* open memory access */
set_nbcfg_enable_bits(igfx_dev, 0x04, 1 << 1, 1 << 1);
/* enable 2D accelerator */
val = *(volatile u32 *)(base | 0x4100); // 0x40FC + 4 ???
val |= 1 << 0;
*(volatile u32 *)(base | 0x4100) = val;
DEBUG_INFO("NB POST STAGE : nb_lock : 2D enable : address abnormal?\n");
}
}
}
/* enable decode for debug BAR */
if( (ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)) && (_pci_conf_read(nb_dev, 0x8C) & (1 << 9)) ){
set_nbcfg_enable_bits(nb_dev, 0x8C, 1 << 10, 1 << 10);
}else{
set_nbcfg_enable_bits(nb_dev, 0x8C, 3 << 9, 0 << 9);
}
/* Hide PM2 bar */
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 17, 0 << 17);
/* set proper unused index for inderect space */
/* lock the NB */
set_nbmisc_enable_bits(nb_dev, 0x00, (1 << 0) | (1 << 7), (1 << 0) | (1 << 7));
return;
}
/*******************************************************
* Optimize k8 with UMA.
* See BKDG_NPT_0F guide for details.
* The processor node is addressed by its Node ID on the HT link and can be
* accessed with a device number in the PCI configuration space on Bus0.
* The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped
* to Device 25, and so on.
* The processor implements configuration registers in PCI configuration
* space using the following four headers
* Function0: HT technology configuration
* Function1: Address map configuration
* Function2: DRAM and HT technology Trace mode configuration
* Function3: Miscellaneous configuration
*******************************************************/
static void k8_optimization(void)
{
pci_devfn_t k8_f0, k8_f2, k8_f3;
msr_t msr;
printk(BIOS_INFO, "k8_optimization()\n");
k8_f0 = PCI_DEV(0, 0x18, 0);
k8_f2 = PCI_DEV(0, 0x18, 2);
k8_f3 = PCI_DEV(0, 0x18, 3);
/* 8.6.6 K8 Buffer Allocation Settings */
pci_write_config32(k8_f0, 0x90, 0x01700169); /* CIM NPT_Optimization */
set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28);
set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 26, 3 << 26);
set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11);
/* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */ /* TODO */
pci_write_config32(k8_f3, 0x70, 0x51220111);
pci_write_config32(k8_f3, 0x74, 0x50404021);
pci_write_config32(k8_f3, 0x78, 0x08002A00);
if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12)
pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */
else
pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */
set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25);
set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24);
set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10);
set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2);
set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5);
msr = rdmsr(NB_CFG_MSR);
msr.lo &= ~(1 << 9);
msr.hi &= ~(1 << 4);
wrmsr(NB_CFG_MSR, msr);
}
/*
* rs690_nb_post_init :
* rs690 NorthBridge init after PCI emulation
*/
void nb_post_init(void)
{
pcitag_t igfx_dev = _pci_make_tag(1, 5, 0);
DEBUG_INFO("\n++++++++++++++++++++NB POST STAGE WITH REV(%d)+++++++++++++++++++++++++++++++++\n", get_nb_revision());
#if defined(CFG_UMA_SUPPORT) || defined(CFG_SP_ENABLE)
/* gfx_late_init */
if( (ati_nb_cfg.gfx_config & (GFX_UMA_ENABLE | GFX_SP_ENABLE)) && (ati_nb_cfg.ext_config & EXT_GFX_SVIEW_ENABLE) ){
set_nbcfg_enable_bits(igfx_dev, 0x04, 1 << 1, 1 << 1); // enabel memory access
}
#endif
/* NB misc clock setting, powerdown as needed */
nb_misc_clock();
/* lock the whole NB registers */
nb_lock();
DEBUG_INFO("---------------------------------------------- NB POST STAGE DONE------------------------------\n");
return;
}
void rs780_htinit(void)
{
/*
* About HT, it has been done in enumerate_ht_chain().
*/
pci_devfn_t cpu_f0, rs780_f0, clk_f1;
u32 reg;
u8 cpu_ht_freq, ibias;
cpu_f0 = PCI_DEV(0, 0x18, 0);
/************************
* get cpu's ht freq, in cpu's function 0, offset 0x88
* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
* The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
* value to this reg, and that value takes effect on the next warm reset or
* LDTSTOP_L disconnect sequence.
* please see the table rs780_ibias about the value and its corresponding frequency.
************************/
reg = pci_read_config32(cpu_f0, 0x88);
cpu_ht_freq = (reg & 0xf00) >> 8;
printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
rs780_f0 = PCI_DEV(0, 0, 0);
//set_nbcfg_enable_bits(rs780_f0, 0xC8, 0x7<<24 | 0x7<<28, 1<<24 | 1<<28);
clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */
ibias = rs780_ibias[cpu_ht_freq];
/* If HT freq>1GHz, we assume the CPU is fam10, else it is K8.
* Is it appropriate?
* Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases.
* So we check 6 only, it would be faster. */
if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) ||
(cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) {
printk(BIOS_INFO, "rs780_htinit: HT1 mode\n");
/* HT1 mode, RPR 8.4.2 */
/* set IBIAS code */
set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
/* Optimizes chipset HT transmitter drive strength */
set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
} else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
printk(BIOS_INFO, "rs780_htinit: HT3 mode\n");
#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDFAM10)
/* HT3 mode, RPR 8.4.3 */
set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);
/* set IBIAS code */
set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
/* Optimizes chipset HT transmitter drive strength */
set_htiu_enable_bits(rs780_f0, 0x2A, 0x3, 0x1);
/* Enables error-retry mode */
set_nbcfg_enable_bits(rs780_f0, 0x44, 0x1, 0x1);
/* Enables scrambling and Disables command throttling */
set_nbcfg_enable_bits(rs780_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14));
/* Enables transmitter de-emphasis */
set_nbcfg_enable_bits(rs780_f0, 0xa4, 1 << 31, 1 << 31);
/* Enables transmitter de-emphasis level */
/* Sets training 0 time */
set_nbcfg_enable_bits(rs780_f0, 0xa0, 0x3F, 0x14);
/* Enables strict TM4 detection */
set_htiu_enable_bits(rs780_f0, 0x15, 0x1 << 22, 0x1 << 22);
/* Enables proper DLL reset sequence */
set_htiu_enable_bits(rs780_f0, 0x16, 0x1 << 10, 0x1 << 10);
/* HyperTransport 3 Processor register settings to be done in northbridge */
/* Enables error-retry mode */
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130, 1 << 0, 1 << 0);
/* Enables scrambling */
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170, 1 << 3, 1 << 3);
/* Enables transmitter de-emphasis
* This depends on the PCB design and the trace */
/* TODO: */
/* Disables command throttling */
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10);
/* Sets Training 0 Time. See T0Time table for encodings */
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20);
/* TODO: */
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
}
}
/*****************************************
* Compliant with CIM_33's PCIEGPPInit
* nb_dev:
* root bridge struct
* dev:
* p2p bridge struct
* port:
* p2p bridge number, 4-10
*****************************************/
void sr5650_gpp_sb_init(device_t nb_dev, device_t dev, u32 port)
{
u32 gpp_sb_sel = 0;
struct southbridge_amd_sr5650_config *cfg =
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
printk(BIOS_DEBUG, "gpp_sb_init nb_dev=0x%p, dev=0x%p, port=0x%x\n", nb_dev, dev, port);
switch (port) {
case 2:
case 3:
gpp_sb_sel = PCIE_CORE_INDEX_GPP1;
break;
case 4 ... 7:
case 9:
case 10:
gpp_sb_sel = PCIE_CORE_INDEX_GPP3a;
break;
case 8:
gpp_sb_sel = PCIE_CORE_INDEX_SB;
break;
case 11:
case 12:
gpp_sb_sel = PCIE_CORE_INDEX_GPP2;
break;
case 13:
gpp_sb_sel = PCIE_CORE_INDEX_GPP3b;
break;
}
/* Init common Core registers */
set_pcie_enable_bits(dev, 0xB1, 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19,
1 << 28 | 1 << 23 | 1 << 20 | 1 << 19);
if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a) {
set_pcie_enable_bits(dev, 0xB1, 1 << 22, 1 << 22);
/* 4.3.3.2.3 Step 10: Dynamic Slave CPL Buffer Allocation */
gpp3a_cpl_buf_alloc(nb_dev, dev);
}
if (gpp_sb_sel == PCIE_CORE_INDEX_GPP1 || gpp_sb_sel == PCIE_CORE_INDEX_GPP2) {
gpp12_cpl_buf_alloc(nb_dev, dev);
}
set_pcie_enable_bits(dev, 0xA1, (1 << 26) | (1 << 24) | (1 << 11), 1 << 11);
set_pcie_enable_bits(dev, 0xA0, 0x0000FFF0, 0x6830);
// PCIE should not ignore malformed packet error or ATS request
set_pcie_enable_bits(dev, 0x70, 1 << 12, 0);
//Step 14.1: Advertising Hot Plug Capabilities
set_pcie_enable_bits(dev, 0x10, 1 << 4, 1 << 4); //Enable power fault
set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 0, 1 << 0);
/* init GPP core */
/* 4.4.2.step13.1. Sets RCB completion timeout to be 200ms */
pci_ext_write_config32(nb_dev, dev, 0x80, 0xF << 0, 0x6 << 0);
/* 4.4.2.step13.2. RCB completion timeout on link down to shorten enumeration time. */
set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
/* 4.4.2.step13.3. Enable slave ordering rules */
set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 8, 0 << 8);
/* 4.4.2.step13.4. Sets DMA payload size to 64 bytes. */
set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 7 << 10, 4 << 10);
/* 4.4.2.step13.5. Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs
during L1 so that Tx Clk can be turned off. */
set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 0 | 1 << 8, 1 << 0 | 1 << 8); // add bit 8 from CIMx
/* 4.4.2.step13.6. Set REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to
prevent LC from going to L1 when there are outstanding completions.*/
set_pcie_enable_bits(dev, 0x02, 1 << 15, 1 << 15);
/* 4.4.2.step13.7. Set REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent
lc to go to from L0 to Rcv_L0s if L1 is armed. */
set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
/* 4.4.2.step13.8. CMGOOD_OVERRIDE for all five PCIe cores. */
set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 27, 1 << 27);
/* 4.4.2.step13.9. Prevents Electrical Idle from causing a
transition from Rcv_L0 to Rcv_L0s. */
set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
/* 4.4.2.step13.10. Prevents the LTSSM from going to Rcv_L0s if
it has already acknowledged a request to go
to L1 but it has not transitioned there yet. */
/* seems the same as step13.7 */
set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
/* 4.4.2.step13.11. Transmits FTS before Recovery. */
set_pcie_enable_bits(dev, 0xA3, 1 << 9, 1 << 9);
/* 4.4.2.step13.12. Sets TX arbitration algorithm to round robin
for PCIE-GPP1, PCIE-GPP2, PCIE-GPP3a and PCIE-GPP3b cores only. */
//if (gpp_sb_sel != PCIE_CORE_INDEX_SB) /* RPR NOT set SB_CORE, BTS set SB_CORE, we comply with BTS */
set_pcie_enable_bits(nb_dev, 0x1C | gpp_sb_sel, 0x7FF, 0x109);
/* 4.4.2.step13.13. Sets number of TX Clocks to drain TX Pipe to 0x3.*/
set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4);
/* 4.4.2.step13.14. Lets PI use Electrical Idle from PHY when
turning off PLL in L1 at Gen 2 speed instead of Inferred Electrical
Idle.
NOTE: LC still uses Inferred Electrical Idle. */
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 3 << 14, 2 << 14);
/* 4.4.2.step13.15. Turn on rx_fronten_en for all active lanes upon
exit from Electrical Idle, rather than being tied to PLL_PDNB. */
set_pcie_enable_bits(nb_dev, 0xC2 | gpp_sb_sel, 1 << 25, 1 << 25);
/* 4.4.2.step13.16. Advertises TX L0s and L1 exit latency.
TX L0s exit latency to be 100b: 512ns to less than 1us;
L1 exit latency to be 011b: 4us to less than 8us.
For Hot-Plug Slots: Advertise TX L0s and L1 exit latency.
TX L0s exit latency to be 110b: 2us to 4us.
L1 exit latency to be 111b: more than 64us.*/
//set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for htplg. */
set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for htplg. */
/* 4.4.2.step13.17. Always ACK an ASPM L1 entry DLLP to
workaround credit control issue on PM_NAK
message of SB700 and SB800. */
/* 4.4.4.step13.18. To allow advertising Gen 2 capabilities to Southbridge. */
if (port == 8) {
set_pcie_enable_bits(dev, 0xA0, 1 << 23, 1 << 23);
set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 1, 1 << 1);
}
/* 4.4.2.step13.19. CMOS Option (Gen 2 AUTO-Part 1 - Enabled by Default) */
/* 4.4.2.step13.20. CMOS Option (RC Advertised Gen 2-Part1 - Disabled by Default)*/
set_nbcfg_enable_bits(dev, 0x88, 0xF << 0, 0x2 << 0);
/* Disables GEN2 capability of the device.
* RPR typo- it says enable but the bit setting says disable.
* Disable it here and we enable it later. */
set_pcie_enable_bits(dev, 0xA4, 1 << 0, 1 << 0);
/* 4.4.2.step13.21. */
/* 4.4.2.step13.22 */
/* Enable native PME. */
set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 < 3);
/* This bit when set indicates that the PCIe Link associated with this port
is connected to a slot. */
pci_ext_write_config32(nb_dev, dev, 0x5a, 1 << 8, 1 << 8);
/* This bit when set indicates that this slot is capable of supporting
Hot-Plug operations. */
set_nbcfg_enable_bits(dev, 0x6C, 1 << 6, 1 << 6);
/* Enables flushing of TLPs when Data Link is down. */
set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
/* 4.4.2.step14. Server Class Hot Plug Feature */
/* 4.4.2 step14.1: Advertising Hot Plug Capabilities */
/* 4.4.2.step14.2: Firmware Upload */
/* 4.4.2.Step14.3: SBIOS Acknowledgment to Firmware of Successful Firmware Upload */
/* step14.4 */
/* step14.5 */
/* skip */
/* CIMx LPC Deadlock workaround - Enable Memory Write Map*/
if (gpp_sb_sel == PCIE_CORE_INDEX_SB) {
set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 9, 1 << 9);
set_htiu_enable_bits(nb_dev, 0x06, 1 << 26, 1 << 26);
}
/* This CPL setup requires more than this one register and should be done in gpp_core.
* The additional setup is for the different revisions. */
/* CIMx CommonPortInit settings that are not set above. */
pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */
if ( port == 8 )
set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23);
/* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */
init_gen2(nb_dev, dev, port);
set_pcie_enable_bits(dev, 0xA4, 1 << 29, 1 << 29);
set_pcie_enable_bits(dev, 0xC0, 1 << 15, 0);
set_pcie_enable_bits(dev, 0xA2, 1 << 13, 0);
/* Hotplug Support - bit5 + bit6 capable and surprise */
pci_ext_write_config32(nb_dev, dev, 0x6c, 0x60, 0x60);
/* Set interrupt pin info 0x3d */
pci_ext_write_config32(nb_dev, dev, 0x3c, 1 << 8, 1 << 8);
/* 5.12.9.3 Hotplug step 1 - NB_PCIE_ROOT_CTRL - enable pm irq
The RPR is wrong - this is not a PCIEND_P register */
pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3);
/* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */
if ( port != 8)
set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2);
/* Not sure about this PME setup */
/* Native PME */
set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 << 3); /* Not set in CIMx */
/* PME Enable */
pci_ext_write_config32(nb_dev, dev, 0x54, 1 << 8, 1 << 8); /* Not in CIMx */
/* 4.4.3 Training for GPP devices */
/* init GPP */
switch (port) {
case 2:
case 3:
case 4: /* GPP_SB */
case 5:
case 6:
case 7:
case 9: /*GPP*/
case 10:
case 11:
case 12:
case 13:
/* 4.4.2.step13.5. Blocks DMA traffic during C3 state */
set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
/* Enabels TLP flushing */
set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
/* check port enable */
if (cfg->port_enable & (1 << port)) {
PcieReleasePortTraining(nb_dev, dev, port);
if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
u8 res = PcieTrainPort(nb_dev, dev, port);
printk(BIOS_DEBUG, "PcieTrainPort port=0x%x result=%d\n", port, res);
if (res) {
AtiPcieCfg.PortDetect |= 1 << port;
}
}
}
break;
case 8: /* SB */
break;
default:
break;
}
/* Re-enable RC ordering logic after training (from CIMx)*/
set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 9, 0);
/* Advertising Hot Plug Capabilities */
pci_ext_write_config32(nb_dev, dev, 0x6c, 0x04001B, 0x00001B);
/* PCIE Late Init (CIMx late init - Maybe move somewhere else? Later in the coreboot PCI device enum?) */
/* Set Slot Number */
pci_ext_write_config32(nb_dev, dev, 0x6c, 0x1FFF << 19, port << 19);
/* Set Slot present 0x5A*/
pci_ext_write_config32(nb_dev, dev, 0x58, 1 << 24, 1 << 24);
//PCIE-GPP1 TXCLK Clock Gating In L1 Late Core sttting - Maybe move somewhere else? */
set_pcie_enable_bits(nb_dev, 0x11 | gpp_sb_sel, 0xF << 0, 0x0C << 0);
/* Enable powering down PLLs in L1 or L23 Ready states.
* Turns off PHY`s RX FRONTEND during L1 when PLL power down is enabled */
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 0x1219, 0x1009);
/* 4.4..7.1 TXCLK Gating in L1, Enables powering down TXCLK clock pads on the receive side. */
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6);
/* Step 21: Register Locking PCIE Misc. Late Core sttting - Must move somewhere do PciInitLate FIXME */
/* Lock HWInit Register */
//set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 0, 1 << 0);
/* Step 27: LCLK Gating */
//EnableLclkGating(dev);
/* Set Common Clock */
/* If dev present, set PcieCapPtr+0x10, BIT6);
* set dev 0x68,bit 6
* retrain link, set dev, 0x68 bit 5;
* wait dev 0x6B bit3 clear
*/
if (port == 8){
PciePowerOffGppPorts(nb_dev, dev, port); /* , This should be run for all ports that are not hotplug and don't detect devices */
}
}
/*
* nb_misc_clock :
* rs690 misc clock parameters setting
*/
static void nb_misc_clock(void)
{
pcitag_t clk_dev = _pci_make_tag(0, 0, 1);
pcitag_t nb_dev = _pci_make_tag(0, 0, 0);
pcitag_t gfx_dev2 = _pci_make_tag(0, 2, 0);
u8 rev = get_nb_revision();
u32 val;
/* visible CLK func */
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 1 << 0);
if(ati_nb_cfg.ext_config & EXT_DEBUG_NB_DYNAMIC_CLK){
/* disable NB dynamic clock to htiu rx */
set_nbcfg_enable_bits(clk_dev, 0xE8, 0x07 << 12, 1 << 13);
/* ENABLE : CLKGATE_DIS_GFX_TXCLK & CLKGATE_DIS_GPPSB_CCLK & CLKGATE_DIS_CFG_S1X */
set_nbcfg_enable_bits(clk_dev, 0x94, (1 << 16) | (1 << 24) | (1 << 28), 0);
/* ENABEL : CLKDATE_DIS_IOC_CCLK_MST/SLV, enabel clkdate for C/MCLK goto BIF branch */
set_nbcfg_enable_bits(clk_dev, 0x8C, (1 << 13) | (1 << 14) | (1 << 24) | (1 << 25), 0);
if(rev < REV_RS690_A21){
/* CKLGATE_DIS_IO_CCLK_MST */
set_nbcfg_enable_bits(clk_dev, 0x8C, 1 << 13, 1 << 13);
}
/* Powering Down efuse and strap block clocks in GFX mode as default */
set_nbcfg_enable_bits(clk_dev, 0xCC, 1 << 24, 1 << 24);
/* dynamic clock setting for MC and HTIU */
val = nbmc_read_index(nb_dev, 0x7A);
val &= 0xffffffc0;
val |= 1 << 2;
if(rev >= REV_RS690_A21){
val &= ~(1 << 6);
set_htiu_enable_bits(nb_dev, 0x05, 1 << 11, 1 << 11);
}
nbmc_write_index(nb_dev, 0x7A, val);
if(ati_nb_cfg.gfx_config & (GFX_SP_ENABLE | GFX_UMA_ENABLE)){
/* Powering Down efuse and strap block clocks in GFX mode : PWM???*/
set_nbcfg_enable_bits(clk_dev, 0xCC, (1 << 23) | (1 << 24), 1 << 24);
}else{
/* nb only mode */
/* Powers down reference clock to graphics core PLL */
set_nbcfg_enable_bits(clk_dev, 0x8C, 1 << 21, 1 << 21);
/* Powering Down efuse and strap block clocks after boot-up */
set_nbcfg_enable_bits(clk_dev, 0xCC, (1 << 23) | (1 << 24), (1 << 23) | (1 << 24));
/* powerdown clock to MC */
set_nbcfg_enable_bits(clk_dev, 0xE4, 1 << 0, 1 << 0);
}
if(ati_nb_cfg.pcie_gfx_info == 0){
if(_pci_conf_read(gfx_dev2, 0x00) == 0xffffffff){
/* Powerdown GFX ports clock when no external GFX detected */
set_nbcfg_enable_bits(clk_dev, 0xE8, 1 << 17, 1 << 17);
}
}
}
/* hide CLK func */
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 0 << 0);
if(rev >= REV_RS690_A21){
set_htiu_enable_bits(nb_dev, 0x05, (1 << 8) | (1 << 9), (1 << 8) | (1 << 9));
set_htiu_enable_bits(nb_dev, 0x05, (1 << 10), (1 << 10));
}
DEBUG_INFO("NB POST STAGE : nb_misc_clock function : should we use PWM for efuse and strap powerdown?\n");
return;
}
