/* Single measure from the GYRO */
uint8_t single_measure(){
uint8_t res_adc1;
uint8_t res_adc2;
uint16_t angular_rate_temp = 0x0000;
uint8_t angular_rate = 0x00;
int EOC = 0;
// start command
set_ss(0);
spi_tranceiver(0x94);
spi_tranceiver(0x00);
spi_tranceiver(0x00);
set_ss(1);
// wait until EOC is set ( end of conversion )
while(!EOC){
set_ss(0);
spi_tranceiver(0x80);
res_adc1 = spi_tranceiver(0x00);
res_adc2 = spi_tranceiver(0x00);
set_ss(1);
if((res_adc1 & 0x20) == 0x20){
EOC = 1;
}
}
angular_rate_temp = (res_adc1 << 8) | res_adc2; // angular_rate = res_adc1 & res_adc2
angular_rate_temp >>= 4; // shift four bits right
angular_rate_temp &= 0x00ff; // stores the MSB 8 bits
angular_rate = angular_rate_temp;
return angular_rate;
}
/*SPI initialization*/
void SPI_init()
{
DDRB=(1<<PCINT15)|(1<<PCINT13)|(1<<PORTB4); // set SCK, MOSI and SS as output
SPCR=(1<<SPE)|(1<<MSTR)|(1<<SPR0); // Enable SPI | set as master | SCK freq = mclk/8
set_ss(1);
// enable adc conversion
set_ss(0);
spi_tranceiver(0x94);
spi_tranceiver(0x00);
spi_tranceiver(0x00);
set_ss(1);
}
kern_return_t
pal_efi_call_in_32bit_mode(uint32_t func,
struct pal_efi_registers *efi_reg,
void *stack_contents,
size_t stack_contents_size, /* 16-byte multiple */
uint32_t *efi_status)
{
DBG("pal_efi_call_in_32bit_mode(0x%08x, %p, %p, %lu, %p)\n",
func, efi_reg, stack_contents, stack_contents_size, efi_status);
if (func == 0) {
return KERN_INVALID_ADDRESS;
}
if ((efi_reg == NULL)
|| (stack_contents == NULL)
|| (stack_contents_size % 16 != 0)) {
return KERN_INVALID_ARGUMENT;
}
if (!gPEEFISystemTable || !gPEEFIRuntimeServices) {
return KERN_NOT_SUPPORTED;
}
DBG("pal_efi_call_in_32bit_mode() efi_reg:\n");
DBG(" rcx: 0x%016llx\n", efi_reg->rcx);
DBG(" rdx: 0x%016llx\n", efi_reg->rdx);
DBG(" r8: 0x%016llx\n", efi_reg->r8);
DBG(" r9: 0x%016llx\n", efi_reg->r9);
DBG(" rax: 0x%016llx\n", efi_reg->rax);
DBG("pal_efi_call_in_32bit_mode() stack:\n");
#if PAL_DEBUG
size_t i;
for (i = 0; i < stack_contents_size; i += sizeof(uint32_t)) {
uint32_t *p = (uint32_t *) ((uintptr_t)stack_contents + i);
DBG(" %p: 0x%08x\n", p, *p);
}
#endif
#ifdef __x86_64__
/*
* Ensure no interruptions.
* Taking a spinlock for serialization is technically unnecessary
* because the EFIRuntime kext should serialize.
*/
boolean_t istate = ml_set_interrupts_enabled(FALSE);
simple_lock(&pal_efi_lock);
/*
* Switch to special page tables with the entire high kernel space
* double-mapped into the bottom 4GB.
*
* NB: We assume that all data passed exchanged with RuntimeServices is
* located in the 4GB of KVA based at VM_MIN_ADDRESS. In particular, kexts
* loaded the basement (below VM_MIN_ADDRESS) cannot pass static data.
* Kernel stack and heap space is OK.
*/
MARK_CPU_IDLE(cpu_number());
pal_efi_saved_cr3 = get_cr3_raw();
pal_efi_saved_cr0 = get_cr0();
IDPML4[KERNEL_PML4_INDEX] = IdlePML4[KERNEL_PML4_INDEX];
IDPML4[0] = IdlePML4[KERNEL_PML4_INDEX];
clear_ts();
set_cr3_raw((uint64_t) ID_MAP_VTOP(IDPML4));
swapgs(); /* Save kernel's GS base */
/* Set segment state ready for compatibility mode */
set_gs(NULL_SEG);
set_fs(NULL_SEG);
set_es(KERNEL_DS);
set_ds(KERNEL_DS);
set_ss(KERNEL_DS);
_pal_efi_call_in_32bit_mode_asm(func,
efi_reg,
stack_contents,
stack_contents_size);
/* Restore NULL segment state */
set_ss(NULL_SEG);
set_es(NULL_SEG);
set_ds(NULL_SEG);
swapgs(); /* Restore kernel's GS base */
/* Restore the 64-bit user GS base we just destroyed */
wrmsr64(MSR_IA32_KERNEL_GS_BASE,
current_cpu_datap()->cpu_uber.cu_user_gs_base);
/* End of mapping games */
set_cr3_raw(pal_efi_saved_cr3);
set_cr0(pal_efi_saved_cr0);
MARK_CPU_ACTIVE(cpu_number());
simple_unlock(&pal_efi_lock);
ml_set_interrupts_enabled(istate);
#else
_pal_efi_call_in_32bit_mode_asm(func,
efi_reg,
stack_contents,
stack_contents_size);
#endif
*efi_status = (uint32_t)efi_reg->rax;
DBG("pal_efi_call_in_32bit_mode() efi_status: 0x%x\n", *efi_status);
return KERN_SUCCESS;
}
