static void mira(void)
{
if((tkcom[0]&0x20&&is209)||is211)
{
int x;
if(tkcom[0]&0x40) // Name tables are ROM-only
{
for(x=0;x<4;x++)
setntamem(CHRptr[0]+(((names[x])&CHRmask1[0])<<10),0,x);
}
else // Name tables can be RAM or ROM.
{
for(x=0;x<4;x++)
{
if((tkcom[1]&0x80)==(names[x]&0x80)) // RAM selected.
setntamem(NTARAM+((names[x]&0x1)<<10),1,x);
else
setntamem(CHRptr[0]+(((names[x])&CHRmask1[0])<<10),0,x);
}
}
}
else
{
switch(tkcom[1]&3)
{
case 0: setmirror(MI_V); break;
case 1: setmirror(MI_H); break;
case 2: setmirror(MI_0); break;
case 3: setmirror(MI_1); break;
}
}
}
static void Sync(void)
{
uint8 i;
setprg8r(0x10,0x6000,0);
setprg8(0x8000,prg[0]);
setprg8(0xa000,prg[1]);
setprg8(0xc000,~1);
setprg8(0xe000,~0);
for(i=0; i<8; i++)
{
uint32 chr = chrlo[i]|(chrhi[i]<<8);
if(chrlo[i]==0xc8)
{
vlock = 0;
continue;
}
else if(chrlo[i]==0x88)
{
vlock = 1;
continue;
}
if(((chrlo[i]==4)||(chrlo[i]==5))&&!vlock)
setchr1r(0x10,i<<10,chr&1);
else
setchr1(i<<10,chr);
}
switch(mirr)
{
case 0: setmirror(MI_V); break;
case 1: setmirror(MI_H); break;
case 2: setmirror(MI_0); break;
case 3: setmirror(MI_1); break;
}
}
static void M68NTfix(void)
{
if((!UNIFchrrama)&&(mirr&0x10))
{
PPUNTARAM = 0;
switch(mirr&3)
{
case 0: vnapage[0]=vnapage[2]=CHRptr[0]+(((nt1|128)&CHRmask1[0])<<10);
vnapage[1]=vnapage[3]=CHRptr[0]+(((nt2|128)&CHRmask1[0])<<10);
break;
case 1: vnapage[0]=vnapage[1]=CHRptr[0]+(((nt1|128)&CHRmask1[0])<<10);
vnapage[2]=vnapage[3]=CHRptr[0]+(((nt2|128)&CHRmask1[0])<<10);
break;
case 2: vnapage[0]=vnapage[1]=vnapage[2]=vnapage[3]=CHRptr[0]+(((nt1|128)&CHRmask1[0])<<10);
break;
case 3: vnapage[0]=vnapage[1]=vnapage[2]=vnapage[3]=CHRptr[0]+(((nt2|128)&CHRmask1[0])<<10);
break;
}
}
else
switch(mirr&3)
{
case 0: setmirror(MI_V); break;
case 1: setmirror(MI_H); break;
case 2: setmirror(MI_0); break;
case 3: setmirror(MI_1); break;
}
}
static void BandaiSync(void)
{
if(is153)
{
int base=(reg[0]&1)<<4;
if(!UNIFchrrama) // SD Gundam Gaiden - Knight Gundam Monogatari 2 - Hikari no Kishi (J) uses WRAM but have CHRROM too
{
int i;
for(i=0; i<8; i++) setchr1(i<<10,reg[i]);
}
else
setchr8(0);
setprg16(0x8000,(reg[8]&0x0F)|base);
setprg16(0xC000,0x0F|base);
}
else
{
int i;
for(i=0; i<8; i++) setchr1(i<<10,reg[i]);
setprg16(0x8000,reg[8]);
setprg16(0xC000,~0);
}
switch(reg[9]&3)
{
case 0: setmirror(MI_V); break;
case 1: setmirror(MI_H); break;
case 2: setmirror(MI_0); break;
case 3: setmirror(MI_1); break;
}
}
static void M199MW(uint8 V) {
/* FCEU_printf("%02x\n",V); */
switch (V & 3) {
case 0: setmirror(MI_V); break;
case 1: setmirror(MI_H); break;
case 2: setmirror(MI_0); break;
case 3: setmirror(MI_1); break;
}
}
static void MMC1MIRROR(void)
{
switch(DRegs[0]&3)
{
case 2: setmirror(MI_V);break;
case 3: setmirror(MI_H);break;
case 0: setmirror(MI_0);break;
case 1: setmirror(MI_1);break;
}
}
void SyncMirror()
{
switch (mode & 3)
{
case 0: setmirror(MI_0); break;
case 1: setmirror(MI_1); break;
case 2: setmirror(MI_V); break;
case 3: setmirror(MI_H); break;
}
}
static void SyncMirroring(void)
{
switch(Mirroring&3)
{
case 0:setmirror(MI_V);break;
case 1:setmirror(MI_H);break;
case 2:setmirror(MI_0);break;
case 3:setmirror(MI_1);break;
}
}
static void Sync(void) {
uint32 i;
for (i = 0; i < 8; i++)
setchr1(i << 10, chrlo[i] | (chrhi[i] << 8));
setprg8r(0x10, 0x6000, 0);
setprg16(0x8000, prg);
setprg16(0xC000, ~0);
if (mirrisused)
setmirror(mirr ^ 1);
else
setmirror(MI_0);
}
static void Sync(void) {
int i;
for (i = 0; i < 8; i++) setchr1(i << 10, creg[i]);
setprg8r(0x10, 0x6000, 0);
setprg8(0x8000, preg[0]);
setprg8(0xA000, preg[1]);
setprg8(0xC000, preg[2]);
setprg8(0xE000, ~0);
if (mirr & 2)
setmirror(MI_0);
else
setmirror(mirr & 1);
}
static DECLFW(Mapper97_write)
{
latch = V;
switch(V>>6)
{
case 0:break;
case 1:setmirror(MI_H);break;
case 2:setmirror(MI_V);break;
case 3:break;
}
Sync();
}
static void Sync(void) {
uint8 i;
setprg8(0x8000, prg[0]);
setprg8(0xa000, prg[1]);
setprg8(0xc000, prg[2]);
setprg8(0xe000, ~0);
for (i = 0; i < 8; i++)
setchr1(i << 10, chr[i]);
switch (mirr & 3) {
case 0: setmirror(MI_V); break;
case 1: setmirror(MI_H); break;
case 2: setmirror(MI_0); break;
case 3: setmirror(MI_1); break;
}
}
static void Sync(void)
{
int i;
for(i=0; i<8; i++) setchr1(i<<10,creg[i]);
setprg8(0x8000,preg[0]);
setprg8(0xA000,preg[1]);
setprg8(0xC000,preg[2]);
setprg8(0xE000,preg[3]);
switch(mirr) {
case 0: setmirror(MI_0); break;
case 1: setmirror(MI_1); break;
case 2: setmirror(MI_H); break;
case 3: setmirror(MI_V); break;
}
}
static void Sync(void)
{
setmirror(MI_0);
setprg32(0x8000,reg & 3);
setchr4(0x0000,(reg & 4) | ppulatch);
setchr4(0x1000,(reg & 4) | 3);
}
static void Sync(void)
{
setmirror(reg[0]);
setprg8r(0x10,0x6000,0);
setchr8(0);
setprg32(0x8000,(reg[1]+reg[2])&0xf);
}
static void Sync(void)
{
setchr8(0);
setprg8r(0x10,0x6000,0);
setprg32(0x8000,reg[1]>>1);
setmirror((reg[0]&1)^1);
}
static DECLFW(CommonWrite)
{
switch(A&0xF000)
{
case 0xB000:
CHRBanks[0] = V & 0x1F;
CHRSync();
break;
case 0xC000:
CHRBanks[1] = V & 0x1F;
CHRSync();
break;
case 0xD000:
CHRBanks[2] = V & 0x1F;
CHRSync();
break;
case 0xE000:
CHRBanks[3] = V & 0x1F;
CHRSync();
break;
case 0xF000:
setmirror((V & 1) ^ 1);
Mirroring = V & 1;
break;
}
}
static void UNLYOKOSync(void)
{
setmirror((mode & 1)^1);
setchr2(0x0000,reg[3]);
setchr2(0x0800,reg[4]);
setchr2(0x1000,reg[5]);
setchr2(0x1800,reg[6]);
if(mode & 0x10)
{
uint32 base = (bank & 8) << 1;
setprg8(0x8000,(reg[0]&0x0f)|base);
setprg8(0xA000,(reg[1]&0x0f)|base);
setprg8(0xC000,(reg[2]&0x0f)|base);
setprg8(0xE000,0x0f|base);
}
else
{
if(mode & 8)
setprg32(0x8000,bank >> 1);
else
{
setprg16(0x8000,bank);
setprg16(0xC000,~0);
}
}
void GenMMC3Power(void) {
if (UNIFchrrama) setchr8(0);
SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite);
SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite);
SetReadHandler(0x8000, 0xFFFF, CartBR);
A001B = A000B = 0;
setmirror(1);
if (mmc3opts & 1) {
if (WRAMSIZE == 1024) {
FCEU_CheatAddRAM(1, 0x7000, WRAM);
SetReadHandler(0x7000, 0x7FFF, MAWRAMMMC6);
SetWriteHandler(0x7000, 0x7FFF, MBWRAMMMC6);
} else {
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
SetWriteHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBW);
SetReadHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBR);
setprg8r(0x10, 0x6000, 0);
}
if (!(mmc3opts & 2))
FCEU_dwmemset(WRAM, 0, WRAMSIZE);
}
MMC3RegReset();
if (CHRRAM)
FCEU_dwmemset(CHRRAM, 0, CHRRAMSIZE);
}
static void FDSInit(void)
{
memset(FDSRegs,0,sizeof(FDSRegs));
writeskip=DiskPtr=DiskSeekIRQ=0;
setmirror(1);
setprg8r(0,0xe000,0); // BIOS
setprg32r(1,0x6000,0); // 32KB RAM
setchr8(0); // 8KB CHR RAM
MapIRQHook=FDSFix;
GameStateRestore=FDSStateRestore;
SetReadHandler(0x4030,0x4030,FDSRead4030);
SetReadHandler(0x4031,0x4031,FDSRead4031);
SetReadHandler(0x4032,0x4032,FDSRead4032);
SetReadHandler(0x4033,0x4033,FDSRead4033);
SetWriteHandler(0x4020,0x4025,FDSWrite);
SetWriteHandler(0x6000,0xdfff,FDSRAMWrite);
SetReadHandler(0x6000,0xdfff,FDSRAMRead);
SetReadHandler(0xE000,0xFFFF,FDSBIOSRead);
IRQCount=IRQLatch=IRQa=0;
FDSSoundReset();
InDisk=0;
SelectDisk=0;
}
static int StateAction(StateMem *sm, int load, int data_only)
{
SFORMAT StateRegs[]={
{&cmd, 1, "CMD"},
{&mir, 1, "MIR"},
{&rmode, 1, "RMOD"},
{&IRQmode, 1, "IRQM"},
{&IRQCount, 1, "IRQC"},
{&IRQa, 1, "IRQA"},
{&IRQLatch, 1, "IRQL"},
{DRegs, 11, "DREG"},
SFEND
};
int ret = MDFNSS_StateAction(sm, load, data_only, StateRegs, "MAPR");
if(load)
{
Synco();
if(!nomirror)
setmirror(mir^1);
}
return(ret);
}
static void Sync(void) {
setprg16(0x8000, preg);
setprg16(0xC000, ~0);
setchr8(0);
if (mirr)
setmirror(mirr);
}
static DECLFW(RAMBO1_write)
{
switch(A&0xF001)
{
case 0xa000: mir=V&1;
// if(!nomirror)
setmirror(mir^1);
break;
case 0x8000: cmd = V;
break;
case 0x8001: if((cmd&0xF)<10)
DRegs[cmd&0xF]=V;
else if((cmd&0xF)==0xF)
DRegs[10]=V;
Synco();
break;
case 0xc000: IRQLatch=V;
if(rmode==1)
IRQCount=IRQLatch;
break;
case 0xc001: rmode=1;
IRQCount=IRQLatch;
IRQmode=V&1;
break;
case 0xE000: IRQa=0;
X6502_IRQEnd(FCEU_IQEXT);
if(rmode==1)
IRQCount=IRQLatch;
break;
case 0xE001: IRQa=1;
if(rmode==1)
IRQCount=IRQLatch;
break;
}
}
void GenMMC3Power(void) {
if (UNIFchrrama) setchr8(0);
SetWriteHandler(0x8000, 0xBFFF, MMC3_CMDWrite);
SetWriteHandler(0xC000, 0xFFFF, MMC3_IRQWrite);
SetReadHandler(0x8000, 0xFFFF, CartBR);
// KT-008 boards hack 2-in-1, TODO assign to new ines mapper, most dump of KT-boards on the net are mapper 4, so need database or goodnes fix support
SetWriteHandler(0x5000,0x5FFF, KT008HackWrite);
A001B = A000B = 0;
setmirror(1);
if (mmc3opts & 1) {
if (WRAMSIZE == 1024) {
FCEU_CheatAddRAM(1, 0x7000, WRAM);
SetReadHandler(0x7000, 0x7FFF, MAWRAMMMC6);
SetWriteHandler(0x7000, 0x7FFF, MBWRAMMMC6);
} else {
FCEU_CheatAddRAM(WRAMSIZE >> 10, 0x6000, WRAM);
SetWriteHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBW);
SetReadHandler(0x6000, 0x6000 + ((WRAMSIZE - 1) & 0x1fff), CartBR);
setprg8r(0x10, 0x6000, 0);
}
if (!(mmc3opts & 2))
FCEU_dwmemset(WRAM, 0, WRAMSIZE);
}
MMC3RegReset();
if (CHRRAM)
FCEU_dwmemset(CHRRAM, 0, CHRRAMSIZE);
}
static void Sync(void)
{
setprg8(0x6000, reg);
setprg32r(1, 0x8000, 0);
setchr8(0);
setmirror(mirr);
}
static void Sync(void) {
setprg8(0x8000, prg_reg[0]);
setprg8(0xA000, prg_reg[1]);
int i;
for (i = 0; i < 8; i++)
setchr1(i << 10, chr_reg[i]);
setmirror(mirr ^ 1);
}
static void Sync(void) {
if (mode) {
setprg16(0x8000, prg);
setprg16(0xC000, prg);
} else
setprg32(0x8000, prg >> 1);
setchr8(chr);
setmirror(mirr);
}
static void SyncLH10(void) {
setprg8(0x6000, ~1);
setprg8(0x8000, reg[6]);
setprg8(0xA000, reg[7]);
setprg8r(0x10, 0xC000, 0);
setprg8(0xE000, ~0);
setchr8(0);
setmirror(0);
}
static void UNLEDU2000Power(void)
{
setmirror(MI_0);
SetReadHandler(0x6000,0xFFFF,CartBR);
SetWriteHandler(0x6000,0xFFFF,CartBW);
SetWriteHandler(0x8000,0xFFFF,UNLEDU2000HiWrite);
reg=0;
Sync();
}
static void Sync(void) {
int i;
setprg8(0x8000, reg[0]);
setprg8(0xA000, reg[1]);
setprg8(0xC000, reg[2]);
for (i = 0; i < 8; i++)
setchr1(i << 10, chr[i]);
setmirror(reg[3] ^ 1);
}