void
smod2(int32 c, int v, Node *l, Node *n)
{
Node nod;
if(c == 1) {
zeroregm(n);
return;
}
sext(&nod, n, l);
if(v == 0) {
zeroregm(n);
gins(AXORL, &nod, n);
gins(ASUBL, &nod, n);
}
else if(v > 1) {
gins(AANDL, nodconst((1 << v) - 1), &nod);
gins(AADDL, &nod, n);
gins(AANDL, nodconst((1 << v) - 1), n);
gins(ASUBL, &nod, n);
}
else {
gins(AANDL, nodconst(1), n);
gins(AXORL, &nod, n);
gins(ASUBL, &nod, n);
}
regfree(&nod);
}
int pt_last_ip_update_ip(struct pt_last_ip *last_ip,
const struct pt_packet_ip *packet,
const struct pt_config *config)
{
(void) config;
if (!last_ip || !packet)
return -pte_internal;
switch (packet->ipc) {
case pt_ipc_suppressed:
last_ip->suppressed = 1;
return 0;
case pt_ipc_sext_48:
last_ip->ip = sext(packet->ip, 48);
last_ip->have_ip = 1;
last_ip->suppressed = 0;
return 0;
case pt_ipc_update_16:
last_ip->ip = (last_ip->ip & ~0xffffull)
| (packet->ip & 0xffffull);
last_ip->have_ip = 1;
last_ip->suppressed = 0;
return 0;
case pt_ipc_update_32:
last_ip->ip = (last_ip->ip & ~0xffffffffull)
| (packet->ip & 0xffffffffull);
last_ip->have_ip = 1;
last_ip->suppressed = 0;
return 0;
case pt_ipc_update_48:
last_ip->ip = (last_ip->ip & ~0xffffffffffffull)
| (packet->ip & 0xffffffffffffull);
last_ip->have_ip = 1;
last_ip->suppressed = 0;
return 0;
case pt_ipc_full:
last_ip->ip = packet->ip;
last_ip->have_ip = 1;
last_ip->suppressed = 0;
return 0;
}
return -pte_bad_packet;
}
void
sdiv2(int32 c, int v, Node *l, Node *n)
{
Node nod;
if(v > 0) {
if(v > 1) {
sext(&nod, n, l);
gins(AANDL, nodconst((1 << v) - 1), &nod);
gins(AADDL, &nod, n);
regfree(&nod);
}
else {
gins(ACMPL, n, nodconst(0x80000000));
gins(ASBBL, nodconst(-1), n);
}
gins(ASARL, nodconst(v), n);
}
if(c < 0)
gins(ANEGL, Z, n);
}
int Data_path (void)
{
register struct mem_wrd *memaddr;
register struct IR_FIELDS *ir;
register struct SIM_FLAGS *f;
int retval,retval_cmmu; /* return value */
unsigned int issue_latency = 0; /* max time to issue instr(s) */
if (ckbrkpts(IP, BRK_EXEC)) /* Check for breakpoint */
{
retval = -1;
return(retval);
}
retval_cmmu = 0;
if(usecmmu && (retval = cmmu_function1()))
return(retval);
if ((memaddr = getmemptr (IP, M_INSTR)) == 0)
return (exception(E_TCACC, "Code Access Bus Error"));
ir = &memaddr -> opcode;
f = ((ir->p) ? &ir->p->flgs: &simdata.flgs);
/* see if we can issue the instruction in this clock */
if ( (retval = test_issue( ir, f )) == -1 )
{
return ( retval );
}
else
{
Statistics (ir);
/* Issue the instruction to the appropriate FU */
do_issue();
issue_latency = f->is_latency;
issue_latency += retval;
prev_extime = issue_latency;
if(debugflag)
PPrintf(" after chk_SB : Dcmmutime = %d \n", Dcmmutime);
if (usecmmu)
cmmu_function2(ir);
/*
* The data from the source 1 register is put onto the
* source 1 bus, as an input to the ALU.
*/
m88000.S1bus = m88000.Regs[ir -> src1];
/*
* The data from the source 2 register, or an immediate
* value, is put on the source 2 bus, which is also an
* input to the ALU.
*/
if (!f -> imm_flags) /* if not immediate */
m88000.S2bus = m88000.Regs[ir -> src2];
else if (f -> imm_flags == i26bit)
m88000.S2bus = sext (opword (IP), 0, 26);
else if ((f -> imm_flags == i16bit) &&
((ir -> op < (unsigned)JSR) || (ir -> op > (unsigned)BCND)))
m88000.S2bus = uext (opword (IP), 0, 16);
else if ((f -> imm_flags == i16bit) &&
((ir -> op >= (unsigned)JSR) && (ir -> op <= (unsigned)BCND)))
m88000.S2bus = sext (opword (IP), 0, 16);
else if (f -> imm_flags == i10bit)
m88000.S2bus = uext (opword (IP), 0, 10);
else
{
Eprintf ("SYSTEM ERROR in dpath, funky sized immediate\n");
return(-1);
}
/*
* The instruction has been issued and the busses have
* been driven. Now execute the instruction.
*/
if( retval = execute(ir, f, memaddr) ) return(retval);
if (usecmmu && debugflag)
PPrintf(" Dcmmutime (total after store) = %d \n",Dcmmutime);
/*
* Adjust the program counter
*/
killtime ( issue_latency );
if ( retval = Pc(memaddr, ir, f) )
return ( retval );
}
return ( retval );
}
