/* Packet transmit function */ static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) { struct sh_eth_private *mdp = netdev_priv(ndev); struct sh_eth_txdesc *txdesc; u32 entry; unsigned long flags; spin_lock_irqsave(&mdp->lock, flags); if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) { if (!sh_eth_txfree(ndev)) { if (netif_msg_tx_queued(mdp)) dev_warn(&ndev->dev, "TxFD exhausted.\n"); netif_stop_queue(ndev); spin_unlock_irqrestore(&mdp->lock, flags); return NETDEV_TX_BUSY; } } spin_unlock_irqrestore(&mdp->lock, flags); entry = mdp->cur_tx % TX_RING_SIZE; mdp->tx_skbuff[entry] = skb; txdesc = &mdp->tx_ring[entry]; /* soft swap. */ if (!mdp->cd->hw_swap) sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), skb->len + 2); txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, DMA_TO_DEVICE); if (skb->len < ETHERSMALL) txdesc->buffer_length = ETHERSMALL; else txdesc->buffer_length = skb->len; if (entry >= TX_RING_SIZE - 1) txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); else txdesc->status |= cpu_to_edmac(mdp, TD_TACT); mdp->cur_tx++; if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); return NETDEV_TX_OK; }
static irqreturn_t sh_eth_interrupt(int irq, void *netdev) { struct net_device *ndev = netdev; struct sh_eth_private *mdp = netdev_priv(ndev); struct sh_eth_cpu_data *cd = mdp->cd; irqreturn_t ret = IRQ_NONE; u32 intr_status = 0; spin_lock(&mdp->lock); /* Get interrpt stat */ intr_status = sh_eth_read(ndev, EESR); /* Clear interrupt */ if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | cd->tx_check | cd->eesr_err_check)) { sh_eth_write(ndev, intr_status, EESR); ret = IRQ_HANDLED; } else goto other_irq; if (intr_status & (EESR_FRC | /* Frame recv*/ EESR_RMAF | /* Multi cast address recv*/ EESR_RRF | /* Bit frame recv */ EESR_RTLF | /* Long frame recv*/ EESR_RTSF | /* short frame recv */ EESR_PRE | /* PHY-LSI recv error */ EESR_CERF)){ /* recv frame CRC error */ sh_eth_rx(ndev); } /* Tx Check */ if (intr_status & cd->tx_check) { sh_eth_txfree(ndev); netif_wake_queue(ndev); } if (intr_status & cd->eesr_err_check) sh_eth_error(ndev, intr_status); other_irq: spin_unlock(&mdp->lock); return ret; }
int sh_eth_recv(struct eth_device *dev) { struct sh_eth_dev *eth = dev->priv; int port = eth->port, len = 0; struct sh_eth_info *port_info = ð->port_info[port]; uchar *packet; /* Check if the rx descriptor is ready */ invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); if (!(port_info->rx_desc_cur->rd0 & RD_RACT)) { /* Check for errors */ if (!(port_info->rx_desc_cur->rd0 & RD_RFE)) { len = port_info->rx_desc_cur->rd1 & 0xffff; packet = (uchar *) ADDR_TO_P2(port_info->rx_desc_cur->rd2); invalidate_cache(packet, len); net_process_received_packet(packet, len); } /* Make current descriptor available again */ if (port_info->rx_desc_cur->rd0 & RD_RDLE) port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; else port_info->rx_desc_cur->rd0 = RD_RACT; flush_cache_wback(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); /* Point to the next descriptor */ port_info->rx_desc_cur++; if (port_info->rx_desc_cur >= port_info->rx_desc_base + NUM_RX_DESC) port_info->rx_desc_cur = port_info->rx_desc_base; } /* Restart the receiver if disabled */ if (!(sh_eth_read(eth, EDRRR) & EDRRR_R)) sh_eth_write(eth, EDRRR_R, EDRRR); return len; }
/* Timeout function */ static void sh_eth_tx_timeout(struct net_device *ndev) { struct sh_eth_private *mdp = netdev_priv(ndev); struct sh_eth_rxdesc *rxdesc; int i; netif_stop_queue(ndev); if (netif_msg_timer(mdp)) dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x," " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR)); /* tx_errors count up */ mdp->stats.tx_errors++; /* timer off */ del_timer_sync(&mdp->timer); /* Free all the skbuffs in the Rx queue. */ for (i = 0; i < RX_RING_SIZE; i++) { rxdesc = &mdp->rx_ring[i]; rxdesc->status = 0; rxdesc->addr = 0xBADF00D0; if (mdp->rx_skbuff[i]) dev_kfree_skb(mdp->rx_skbuff[i]); mdp->rx_skbuff[i] = NULL; } for (i = 0; i < TX_RING_SIZE; i++) { if (mdp->tx_skbuff[i]) dev_kfree_skb(mdp->tx_skbuff[i]); mdp->tx_skbuff[i] = NULL; } /* device init */ sh_eth_dev_init(ndev); /* timer on */ mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */ add_timer(&mdp->timer); }
/* PHY state control function */ static void sh_eth_adjust_link(struct net_device *ndev) { struct sh_eth_private *mdp = netdev_priv(ndev); struct phy_device *phydev = mdp->phydev; int new_state = 0; if (phydev->link != PHY_DOWN) { if (phydev->duplex != mdp->duplex) { new_state = 1; mdp->duplex = phydev->duplex; if (mdp->cd->set_duplex) mdp->cd->set_duplex(ndev); } if (phydev->speed != mdp->speed) { new_state = 1; mdp->speed = phydev->speed; if (mdp->cd->set_rate) mdp->cd->set_rate(ndev); } if (mdp->link == PHY_DOWN) { sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR); new_state = 1; mdp->link = phydev->link; } } else if (mdp->link) { new_state = 1; mdp->link = PHY_DOWN; mdp->speed = 0; mdp->duplex = -1; } if (new_state && netif_msg_link(mdp)) phy_print_status(phydev); }
static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) { int port = eth->port, ret = 0; u32 val; struct sh_eth_info *port_info = ð->port_info[port]; struct eth_device *dev = port_info->dev; struct phy_device *phy; /* Configure e-dmac registers */ sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | EDMR_EL, EDMR); sh_eth_write(eth, 0, EESIPR); sh_eth_write(eth, 0, TRSCER); sh_eth_write(eth, 0, TFTR); sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR); sh_eth_write(eth, RMCR_RST, RMCR); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, 0, RPADIR); #endif sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR); /* Configure e-mac registers */ sh_eth_write(eth, 0, ECSIPR); /* Set Mac address */ val = dev->enetaddr[0] << 24 | dev->enetaddr[1] << 16 | dev->enetaddr[2] << 8 | dev->enetaddr[3]; sh_eth_write(eth, val, MAHR); val = dev->enetaddr[4] << 8 | dev->enetaddr[5]; sh_eth_write(eth, val, MALR); sh_eth_write(eth, RFLR_RFL_MIN, RFLR); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, 0, PIPR); sh_eth_write(eth, APR_AP, APR); sh_eth_write(eth, MPR_MP, MPR); sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER); #endif #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); #endif /* Configure phy */ ret = sh_eth_phy_config(eth); if (ret) { printf(SHETHER_NAME ": phy config timeout\n"); goto err_phy_cfg; } phy = port_info->phydev; ret = phy_startup(phy); if (ret) { printf(SHETHER_NAME ": phy startup failure\n"); return ret; } val = 0; /* Set the transfer speed */ if (phy->speed == 100) { printf(SHETHER_NAME ": 100Base/"); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, GECMR_100B, GECMR); #elif defined(CONFIG_CPU_SH7757) sh_eth_write(eth, 1, RTRATE); #elif defined(CONFIG_CPU_SH7724) val = ECMR_RTM; #endif } else if (phy->speed == 10) { printf(SHETHER_NAME ": 10Base/"); #if defined(SH_ETH_TYPE_GETHER) sh_eth_write(eth, GECMR_10B, GECMR); #elif defined(CONFIG_CPU_SH7757) sh_eth_write(eth, 0, RTRATE); #endif } #if defined(SH_ETH_TYPE_GETHER) else if (phy->speed == 1000) { printf(SHETHER_NAME ": 1000Base/"); sh_eth_write(eth, GECMR_1000B, GECMR); } #endif /* Check if full duplex mode is supported by the phy */ if (phy->duplex) { printf("Full\n"); sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR); } else { printf("Half\n"); sh_eth_write(eth, val | (ECMR_CHG_DM|ECMR_RE|ECMR_TE), ECMR); } return ret; err_phy_cfg: return ret; }
/* error control function */ static void sh_eth_error(struct net_device *ndev, int intr_status) { struct sh_eth_private *mdp = netdev_priv(ndev); u32 felic_stat; u32 link_stat; u32 mask; if (intr_status & EESR_ECI) { felic_stat = sh_eth_read(ndev, ECSR); sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ if (felic_stat & ECSR_ICD) mdp->stats.tx_carrier_errors++; if (felic_stat & ECSR_LCHNG) { /* Link Changed */ if (mdp->cd->no_psr || mdp->no_ether_link) { if (mdp->link == PHY_DOWN) link_stat = 0; else link_stat = PHY_ST_LINK; } else { link_stat = (sh_eth_read(ndev, PSR)); if (mdp->ether_link_active_low) link_stat = ~link_stat; } if (!(link_stat & PHY_ST_LINK)) sh_eth_rcv_snd_disable(ndev); else { /* Link Up */ sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & ~DMAC_M_ECI, EESIPR); /*clear int */ sh_eth_write(ndev, sh_eth_read(ndev, ECSR), ECSR); sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | DMAC_M_ECI, EESIPR); /* enable tx and rx */ sh_eth_rcv_snd_enable(ndev); } } } if (intr_status & EESR_TWB) { /* Write buck end. unused write back interrupt */ if (intr_status & EESR_TABT) /* Transmit Abort int */ mdp->stats.tx_aborted_errors++; if (netif_msg_tx_err(mdp)) dev_err(&ndev->dev, "Transmit Abort\n"); } if (intr_status & EESR_RABT) { /* Receive Abort int */ if (intr_status & EESR_RFRMER) { /* Receive Frame Overflow int */ mdp->stats.rx_frame_errors++; if (netif_msg_rx_err(mdp)) dev_err(&ndev->dev, "Receive Abort\n"); } } if (intr_status & EESR_TDE) { /* Transmit Descriptor Empty int */ mdp->stats.tx_fifo_errors++; if (netif_msg_tx_err(mdp)) dev_err(&ndev->dev, "Transmit Descriptor Empty\n"); } if (intr_status & EESR_TFE) { /* FIFO under flow */ mdp->stats.tx_fifo_errors++; if (netif_msg_tx_err(mdp)) dev_err(&ndev->dev, "Transmit FIFO Under flow\n"); } if (intr_status & EESR_RDE) { /* Receive Descriptor Empty int */ mdp->stats.rx_over_errors++; if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R) sh_eth_write(ndev, EDRRR_R, EDRRR); if (netif_msg_rx_err(mdp)) dev_err(&ndev->dev, "Receive Descriptor Empty\n"); } if (intr_status & EESR_RFE) { /* Receive FIFO Overflow int */ mdp->stats.rx_fifo_errors++; if (netif_msg_rx_err(mdp)) dev_err(&ndev->dev, "Receive FIFO Overflow\n"); } if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { /* Address Error */ mdp->stats.tx_fifo_errors++; if (netif_msg_tx_err(mdp)) dev_err(&ndev->dev, "Address Error\n"); } mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; if (mdp->cd->no_ade) mask &= ~EESR_ADE; if (intr_status & mask) { /* Tx error */ u32 edtrr = sh_eth_read(ndev, EDTRR); /* dmesg */ dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ", intr_status, mdp->cur_tx); dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", mdp->dirty_tx, (u32) ndev->state, edtrr); /* dirty buffer free */ sh_eth_txfree(ndev); /* SH7712 BUG */ if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { /* tx dma start */ sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); } /* wakeup */ netif_wake_queue(ndev); } }
static void sh_eth_rcv_snd_enable(struct net_device *ndev) { /* enable tx and rx */ sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | (ECMR_RE | ECMR_TE), ECMR); }
/* Packet receive function */ static int sh_eth_rx(struct net_device *ndev) { struct sh_eth_private *mdp = netdev_priv(ndev); struct sh_eth_rxdesc *rxdesc; int entry = mdp->cur_rx % RX_RING_SIZE; int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx; struct sk_buff *skb; u16 pkt_len = 0; u32 desc_status; rxdesc = &mdp->rx_ring[entry]; while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { desc_status = edmac_to_cpu(mdp, rxdesc->status); pkt_len = rxdesc->frame_length; if (--boguscnt < 0) break; if (!(desc_status & RDFEND)) mdp->stats.rx_length_errors++; if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | RD_RFS5 | RD_RFS6 | RD_RFS10)) { mdp->stats.rx_errors++; if (desc_status & RD_RFS1) mdp->stats.rx_crc_errors++; if (desc_status & RD_RFS2) mdp->stats.rx_frame_errors++; if (desc_status & RD_RFS3) mdp->stats.rx_length_errors++; if (desc_status & RD_RFS4) mdp->stats.rx_length_errors++; if (desc_status & RD_RFS6) mdp->stats.rx_missed_errors++; if (desc_status & RD_RFS10) mdp->stats.rx_over_errors++; } else { if (!mdp->cd->hw_swap) sh_eth_soft_swap( phys_to_virt(ALIGN(rxdesc->addr, 4)), pkt_len + 2); skb = mdp->rx_skbuff[entry]; mdp->rx_skbuff[entry] = NULL; if (mdp->cd->rpadir) skb_reserve(skb, NET_IP_ALIGN); skb_put(skb, pkt_len); skb->protocol = eth_type_trans(skb, ndev); netif_rx(skb); mdp->stats.rx_packets++; mdp->stats.rx_bytes += pkt_len; } rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); entry = (++mdp->cur_rx) % RX_RING_SIZE; rxdesc = &mdp->rx_ring[entry]; } /* Refill the Rx ring buffers. */ for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { entry = mdp->dirty_rx % RX_RING_SIZE; rxdesc = &mdp->rx_ring[entry]; /* The size of the buffer is 16 byte boundary. */ rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); if (mdp->rx_skbuff[entry] == NULL) { skb = dev_alloc_skb(mdp->rx_buf_sz); mdp->rx_skbuff[entry] = skb; if (skb == NULL) break; /* Better luck next round. */ dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz, DMA_FROM_DEVICE); skb->dev = ndev; sh_eth_set_receive_align(skb); skb_checksum_none_assert(skb); rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); } if (entry >= RX_RING_SIZE - 1) rxdesc->status |= cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); else rxdesc->status |= cpu_to_edmac(mdp, RD_RACT | RD_RFP); } /* Restart Rx engine if stopped. */ /* If we don't need to check status, don't. -KDU */ if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) sh_eth_write(ndev, EDRRR_R, EDRRR); return 0; }
static int sh_eth_dev_init(struct net_device *ndev) { int ret = 0; struct sh_eth_private *mdp = netdev_priv(ndev); u_int32_t rx_int_var, tx_int_var; u32 val; /* Soft Reset */ sh_eth_reset(ndev); /* Descriptor format */ sh_eth_ring_format(ndev); if (mdp->cd->rpadir) sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); /* all sh_eth int mask */ sh_eth_write(ndev, 0, EESIPR); #if defined(__LITTLE_ENDIAN__) if (mdp->cd->hw_swap) sh_eth_write(ndev, EDMR_EL, EDMR); else #endif sh_eth_write(ndev, 0, EDMR); /* FIFO size set */ sh_eth_write(ndev, mdp->cd->fdr_value, FDR); sh_eth_write(ndev, 0, TFTR); /* Frame recv control */ sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR); rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5; tx_int_var = mdp->tx_int_var = DESC_I_TINT2; sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER); if (mdp->cd->bculr) sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); if (!mdp->cd->no_trimd) sh_eth_write(ndev, 0, TRIMD); /* Recv frame limit set register */ sh_eth_write(ndev, RFLR_VALUE, RFLR); sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); /* PAUSE Prohibition */ val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; sh_eth_write(ndev, val, ECMR); if (mdp->cd->set_rate) mdp->cd->set_rate(ndev); /* E-MAC Status Register clear */ sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); /* E-MAC Interrupt Enable register */ sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); /* Set MAC address */ update_mac_address(ndev); /* mask reset */ if (mdp->cd->apr) sh_eth_write(ndev, APR_AP, APR); if (mdp->cd->mpr) sh_eth_write(ndev, MPR_MP, MPR); if (mdp->cd->tpauser) sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); /* Setting the Rx mode will start the Rx process. */ sh_eth_write(ndev, EDRRR_R, EDRRR); netif_start_queue(ndev); return ret; }
/* Chip Reset */ static void sh_eth_reset(struct net_device *ndev) { sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR); mdelay(3); sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR); }