//# MENU spectrum
void spectrum_menu()
{
lcdClear();
lcdDisplay();
getInputWaitRelease();
// RF initialization from ppack.c:
dac_init(false);
cpu_clock_set(204); // WARP SPEED! :-)
hackrf_clock_init();
rf_path_pin_setup();
/* Configure external clock in */
scu_pinmux(SCU_PINMUX_GP_CLKIN, SCU_CLK_IN | SCU_CONF_FUNCTION1);
sgpio_configure_pin_functions();
ON(EN_VDD);
ON(EN_1V8);
OFF(MIC_AMP_DIS);
delayms(500); // doesn't work without
cpu_clock_set(204); // WARP SPEED! :-)
si5351_init();
portapack_init();
while(1)
{
switch(getInput())
{
case BTN_UP:
displayMode=MODE_WATERFALL;
break;
case BTN_DOWN:
displayMode=MODE_SPECTRUM;
break;
case BTN_LEFT:
freq -= 2000000;
ssp1_set_mode_max2837();
set_freq(freq);
break;
case BTN_RIGHT:
freq += 2000000;
ssp1_set_mode_max2837();
set_freq(freq);
break;
case BTN_ENTER:
//FIXME: unset the callback, reset the clockspeed, tidy up
nvic_disable_irq(NVIC_DMA_IRQ);
OFF(EN_VDD);
OFF(EN_1V8);
ON(MIC_AMP_DIS);
systick_set_clocksource(0);
systick_set_reload(12e6/SYSTICKSPEED/1000);
return;
}
}
}
//# MENU Apack
void ppack_menu() {
lcdClear();
lcdPrintln("PPack port");
lcdPrintln("");
lcdPrintln("up=enable");
lcdDisplay();
dac_init(false);
cpu_clock_set(204); // WARP SPEED! :-)
hackrf_clock_init();
rf_path_pin_setup();
/* Configure external clock in */
scu_pinmux(SCU_PINMUX_GP_CLKIN, SCU_CLK_IN | SCU_CONF_FUNCTION1);
sgpio_configure_pin_functions();
ON(EN_VDD);
ON(EN_1V8);
OFF(MIC_AMP_DIS);
complex_s8_t * samples;
while(1){
switch(getInputRaw()){
case BTN_UP:
// ON(MIXER_EN); // hackrf does this
cpu_clock_set(204); // WARP SPEED! :-)
si5351_init();
portapack_init();
getInputWaitRelease();
break;
case BTN_DOWN:
lcdPrintln("file");
writeFile("samples.8", (char*)0x20000000,(uintptr_t)s8ram-0x20000000);
break;
case BTN_LEFT:
lcdPrintln("reset");
s8ram=(complex_s8_t*)0x20000000;
break;
case BTN_RIGHT:
break;
case BTN_ENTER:
return;
};
TOGGLE(LED2);
delayms(40);
lcdPrint(IntToStr((uintptr_t)s8ram,8,F_HEX));
lcdPrint(" ");
lcdPrintln(IntToStr(sctr,7,F_LONG));
lcdDisplay();
};
};
int main(void) {
// setup t10 internal clock speed
CCP = 0xD8;
CLKMSR = 0x00; // internal 8MHz
CCP = 0xD8;
CLKPSR = 0x03; // 1/8 prescaler -> 1MHz
si5351_init();
CLOCK_DISABLE(); // Power down all output drivers
SETUP_XTAL_CAP(CAP_10PF); // Set the load capacitance for the XTAL
PLL_SOURCE_XTAL(); // input source of PLAA PLLB to xtal
// PLLA
// VCO Frequency (MHz) = 696.204000000
SETUP_PLLA(26UL, 5051UL, 6500UL); // Input Frequency (MHz) = 26.000000000, Feedback Divider = 26 5051/6500
// PLLB
// VCO Frequency (MHz) = 832.000000000
SETUP_PLLB(32UL, 0UL, 1UL); // Input Frequency (MHz) = 26.000000000, Feedback Divider = 32
// Channel 0
// Output Frequency (MHz) = 4.194000000
SETUP_DIV0(166UL, 0UL, 1UL, OD_PARAM(1)); // Multisynth Output Frequency (MHz) = 4.194000000, Multisynth Divider = 166, R Divider = 1
CLOCK0_CONTROL(SOURCE_PLLA, MODE_INT); // PLL source = PLLA
// Channel 1
// Output Frequency (MHz) = 12.80000000
SETUP_DIV1(65UL, 0UL, 1UL, OD_PARAM(1)); // Multisynth Output Frequency (MHz) = 12.800000000, Multisynth Divider = 65, R Divider = 1
CLOCK1_CONTROL(SOURCE_PLLB, MODE_INT); // PLL source = PLLB
// Channel 2
// Output Frequency (MHz) = 0.010000000
SETUP_DIV2(1300UL, 0UL, 1UL, OD_PARAM(64)); // Multisynth Output Frequency (MHz) = 0.640000000, Multisynth Divider = 1300, R Divider = 64
CLOCK2_CONTROL(SOURCE_PLLB, MODE_INT); // PLL source = PLLB
PLL_SOFTRESET(); // Apply PLLA and PLLB soft reset
ENABLE_OUTPUT(); // Enable all outputs
while(1) {
sleep_cpu();
}
}