void si_en(){
// i2c0_init(255); // is default here
si5351c_disable_all_outputs();
si5351c_disable_oeb_pin_control();
si5351c_power_down_all_clocks();
si5351c_set_crystal_configuration();
si5351c_enable_xo_and_ms_fanout();
si5351c_configure_pll_sources();
si5351c_configure_pll_multisynth();
/* MS3/CLK3 is the source for the external clock output. */
si5351c_configure_multisynth(3, 80*128-512, 0, 1, 0); /* 800/80 = 10MHz */
/* MS4/CLK4 is the source for the RFFC5071 mixer. */
si5351c_configure_multisynth(4, 16*128-512, 0, 1, 0); /* 800/16 = 50MHz */
/* MS5/CLK5 is the source for the MAX2837 clock input. */
si5351c_configure_multisynth(5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS6/CLK6 is unused. */
/* MS7/CLK7 is the source for the LPC43xx microcontroller. */
uint8_t ms7data[] = { 90, 255, 20, 0 };
si5351c_write(ms7data, sizeof(ms7data));
si5351c_set_clock_source(PLL_SOURCE_XTAL);
// soft reset
uint8_t resetdata[] = { 177, 0xac };
si5351c_write(resetdata, sizeof(resetdata));
si5351c_enable_clock_outputs();
};
extern "C" int main() {
turn_on_crystal_oscillator();
start_system_pll();
start_usb_pll();
set_main_clock_to_system_pll();
enable_peripheral_clocks();
serial_init();
configure_pins();
delay(1000000);
//enable_clock_output();
NVIC.enable_interrupts();
//serial_write_string("main():loop");
//serial_write_line();
// Power for FPGA
v1p2_enable(); // FPGA VCCINT
v2p5_enable(); // FPGA PLLs?
v1p8_enable(); // FPGA VCCIOs, DDR2.
v1p1_enable(); // USB internal voltage
delay(1000000);
// Power for the clock generator.
// V3P3A must be turned on *after* V1P8 to satisfy
// Si5351C requirement.
v3p3a_enable();
delay(1000000);
// I2C configuration
i2c0_init(500);
// Give Si5351C time to power up?
delay(100000);
si5351c_disable_all_outputs();
//si5351c_disable_oeb_pin_control();
si5351c_power_down_all_clocks();
si5351c_set_crystal_configuration();
si5351c_enable_xo_and_ms_fanout();
si5351c_configure_pll_sources_for_xtal();
si5351c_configure_pll1_multisynth();
si5351c_configure_multisynth(4, 1536, 0, 1, 0); // 50MHz
si5351c_configure_multisynth(5, 1536, 0, 1, 0); // 50MHz
si5351c_configure_multisynths_6_and_7();
si5351c_configure_clock_control();
si5351c_enable_clock_outputs();
clockgen_output_enable();
fe_enable();
while(true) {
//write_led_status(read_fpga_conf_done());
write_led_status(1);
delay(1000000);
write_led_status(0);
delay(1000000);
}
return 0;
}
/*
Configure PLL1 to min speed (48MHz) => see cpu_clock_pll1_low_speed() .
Configure PLL0USB @480MHz for USB0.
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1, APB3.
*/
void sys_clock_init(const airspy_sys_clock_t* const pt_airspy_sys_conf)
{
/* After boot the CPU runs at 96 MHz */
/* cpu runs from: IRC (12MHz) >> PLL M = 24, FCCO @ 288 MHz direct mode >> IDIVC = 4 >> 96 MHz */
/*
* 12MHz clock is entering LPC XTAL1/OSC input now.
*/
/* set xtal oscillator to low frequency mode */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF;
/* power on the oscillator and wait until stable */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE;
/* Wait at least 250us after Crystal Power ON (Wait for crystal to stabilize)
defined in User Manual 10503.pdf Rev1.8 See Fig 30. BASE_M4_CLK ramp-up procedure
*/
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* Use CGU_SRC_XTAL as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK);
/* Use CGU_SRC_XTAL as clock source for Peripheral */
CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_XTAL);
/* Use CGU_SRC_XTAL as clock source for APB1 */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
/* Use CGU_SRC_XTAL as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
/* ********************** */
/* SI5351c configuration */
/* ********************** */
/*
* xxMHz clock is entering LPC GP_CLKIN (from SI5351C) input now.
* AirSpy clocks:
* CLK0 -> R820T xxMHz (XTAL_I)
* CLK1 -> LPC4370 RTC 32KHz
* CLK2 -> SGPIO Clock (not used for future)
* CLK3 -> NC
* CLK4 -> NC
* CLK5 -> NC
* CLK6 -> NC
* CLK7 -> LPC4370 Main Clock xxMHz.
*/
/* Configure I2C0 (for SI5351C) to about 375kHz (12MHz/(2*16)=0.375MHz) when we switch over to APB1 clock = 12MHz */
i2c0_init(16);
si5351c_disable_oeb_pin_control();
/* Programming the Si5351 via I2C http://community.silabs.com/t5/Silicon-Labs-Knowledge-Base/Programming-the-Si5351-via-I2C/ta-p/112251
*/
si5351c_disable_all_outputs();
si5351c_init_fanout();
si5351c_power_down_all_clocks();
si5351c_init_xtal();
si5351c_read[0] = si5351c_read_single(0);
/* Configure and enable SI5351C clocks */
si5351c_read[1] = (si5351c_read_single(0) & SI5351C_REG0_CLKIN_LOS);
/* CLKIN Loss Of Signal (LOS) ? */
if(si5351c_read[1] == SI5351C_REG0_CLKIN_LOS)
si5351c_airspy_config(AIRSPY_SI5351C_CONFIG_XTAL);
else
si5351c_airspy_config(AIRSPY_SI5351C_CONFIG_CLKIN);
si5351c_read[2] = si5351c_read_single(0);
si5351c_init_pll_soft_reset();
si5351c_enable_clock_outputs();
/* Wait at least 300us after SI5351C Clock Enable */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
si5351c_read[3] = si5351c_read_single(0);
/* ********************************************************************* */
/* M4/M0 core, Peripheral, APB1, APB3 Configuration (PLL1 clock source) */
/* ********************************************************************* */
/* Configure PLL1 with CGU_SRC_GP_CLKIN as source clock */
cpu_clock_pll1_low_speed(&pt_airspy_sys_conf->pll1_ls);
/* Configure I2C0 (for SI5351C) to 400kHz when we switch over to APB1 clock = PLL1 */
i2c0_init(AIRSPY_I2C0_PLL1_LS_HS_CONF_VAL);
/* Configure I2C1 (for R820T) to 400kHz when we switch over to APB3 clock = PLL1 */
i2c1_init(AIRSPY_I2C1_PLL1_LS_CONF_VAL);
/* ************************************************** */
/* Connect PLL1 to M4/M0 core, Peripheral, APB1, APB3 */
/* ************************************************** */
/* Use PLL1 as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK);
/* Switch peripheral clock over to use PLL1 */
CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK
| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB1 clock over to use PLL1 */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB3 clock over to use PLL1 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
/* **************************************************** */
/* PLL0USB & USB0 Configuration (GP_CLKIN clock source) */
/* **************************************************** */
/* Use CGU_SRC_GP_CLKIN as clock source for PLL0USB */
CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD
| CGU_PLL0USB_CTRL_AUTOBLOCK
| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_GP_CLKIN);
while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK);
/* configure PLL0USB to produce 480 MHz clock from CGU_SRC_GP_CLKIN */
CGU_PLL0USB_MDIV = pt_airspy_sys_conf->pll0_usb_mdiv;
CGU_PLL0USB_NP_DIV = pt_airspy_sys_conf->pll0_usb_npdiv;
CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD
| pt_airspy_sys_conf->pll0usb_ctrl_flags
| CGU_PLL0USB_CTRL_CLKEN);
/* Power on PLL0USB and wait until stable */
CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD;
while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK));
/* Use PLL0USB as clock source for USB0 */
CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK
| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
/* ****************************************** */
/* Disable/PowerDown unused clock/peripherals */
/* ****************************************** */
CREG_CREG6 |= (1<<17); // PowerDown RNG
/* Disable XTAL because GP_CLKIN is used from SI5351C instead */
/* Switch off the oscillator */
CGU_XTAL_OSC_CTRL = CGU_XTAL_OSC_CTRL_ENABLE;
CGU_BASE_SAFE_CLK = CGU_BASE_USB1_CLK_PD;
// CGU_BASE_USB0_CLK is used for USB0 HS
// CGU_BASE_M0_CLK is used
/* Switch off USB1 clock */
CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_PD;
// CGU_BASE_M4_CLK is used
CGU_BASE_SPIFI_CLK = CGU_BASE_SPIFI_CLK_PD;
/* Switch off SPI clock */
CGU_BASE_SPI_CLK = CGU_BASE_SPI_CLK_PD;
/* Switch off PHY RX & TX clock */
CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD;
CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD;
// CGU_BASE_APB1_CLK is used for I2C0
// CGU_BASE_APB3_CLK is used for I2C1
/* Switch off LCD clock */
CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD;
// CGU_BASE_ADCHS_CLK is used
/* Switch off SDIO clock */
CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD;
CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_PD;
#ifdef AIRSPY_NOS
/* Switch off SSP1 clock */
CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_PD;
#else /* AIRSPY One/Demo */
//CGU_BASE_SSP1_CLK is used for LED
#endif
/* Switch off UART0 to 3 clock */
CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD;
CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD;
CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD;
CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD;
/* Switch off OUT clocks */
CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD;
/* Reserved/Undocumented clocks power down */
CGU_OUTCLK_21_CTRL = 1;
CGU_OUTCLK_22_CTRL = 1;
CGU_OUTCLK_23_CTRL = 1;
CGU_OUTCLK_24_CTRL = 1;
/* Switch off AUDIO clock */
CGU_BASE_APLL_CLK = CGU_BASE_APLL_CLK_PD;
CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD;
CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD;
/* Switch off IDIV C,D,E disabled */
CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD;
CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD;
CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD;
/*
// Power down M4 branches, but not BUS, GPIO, CREG and M0 & M4 CORE clock
*/
//CCU1_CLK_M4_BUS_CFG &= ~(1);
CCU1_CLK_M4_SPIFI_CFG &= ~(1);
//CCU1_CLK_M4_GPIO_CFG &= ~(1);
CCU1_CLK_M4_LCD_CFG &= ~(1);
CCU1_CLK_M4_ETHERNET_CFG &= ~(1);
//CCU1_CLK_M4_USB0_CFG &= ~(1);
CCU1_CLK_M4_EMC_CFG &= ~(1);
CCU1_CLK_M4_SDIO_CFG &= ~(1);
//CCU1_CLK_M4_DMA_CFG &= ~(1);
//CCU1_CLK_M4_M4CORE_CFG &= ~(1);
CCU1_CLK_M4_SCT_CFG &= ~(1);
CCU1_CLK_M4_USB1_CFG &= ~(1);
CCU1_CLK_M4_EMCDIV_CFG &= ~(1);
//CCU1_CLK_M4_M0APP_CFG &= ~(1);
//CCU1_CLK_M4_VADC_CFG &= ~(1);
CCU1_CLK_M4_WWDT_CFG &= ~(1);
CCU1_CLK_M4_USART0_CFG &= ~(1);
CCU1_CLK_M4_UART1_CFG &= ~(1);
CCU1_CLK_M4_SSP0_CFG &= ~(1);
#ifdef AIRSPY_NOS
CCU1_CLK_M4_SSP1_CFG &= ~(1);
#else /* AIRSPY One/Demo */
//CCU1_CLK_M4_SSP1_CFG is used for LED
#endif
CCU1_CLK_M4_TIMER0_CFG &= ~(1);
CCU1_CLK_M4_TIMER1_CFG &= ~(1);
//CCU1_CLK_M4_SCU_CFG &= ~(1);
//CCU1_CLK_M4_CREG_CFG &= ~(1);
CCU1_CLK_M4_RITIMER_CFG &= ~(1);
CCU1_CLK_M4_USART2_CFG &= ~(1);
CCU1_CLK_M4_USART3_CFG &= ~(1);
CCU1_CLK_M4_TIMER2_CFG &= ~(1);
CCU1_CLK_M4_TIMER3_CFG &= ~(1);
CCU1_CLK_M4_QEI_CFG &= ~(1);
CCU1_CLK_PERIPH_SGPIO_CFG &= ~(1);
/* ******************************************** */
/* ADCHS Configuration (GP_CLKIN clock source) */
/* ******************************************** */
sys_clock_samplerate(&airspy_m4_conf[0]);
}
/* clock startup for LPC4320 configure PLL1 to max speed (204MHz).
Note: PLL1 clock is used by M4/M0 core, Peripheral, APB1. */
void cpu_clock_init(void)
{
/* use IRC as clock source for APB1 (including I2C0) */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_IRC);
/* use IRC as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_IRC);
i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_slow_clock);
si5351c_disable_all_outputs(&clock_gen);
si5351c_disable_oeb_pin_control(&clock_gen);
si5351c_power_down_all_clocks(&clock_gen);
si5351c_set_crystal_configuration(&clock_gen);
si5351c_enable_xo_and_ms_fanout(&clock_gen);
si5351c_configure_pll_sources(&clock_gen);
si5351c_configure_pll_multisynth(&clock_gen);
/*
* Clocks:
* CLK0 -> MAX5864/CPLD
* CLK1 -> CPLD
* CLK2 -> SGPIO
* CLK3 -> External Clock Output (power down at boot)
* CLK4 -> RFFC5072 (MAX2837 on rad1o)
* CLK5 -> MAX2837 (MAX2871 on rad1o)
* CLK6 -> none
* CLK7 -> LPC43xx (uses a 12MHz crystal by default)
*/
/* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
si5351c_configure_multisynth(&clock_gen, 4, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
si5351c_configure_multisynth(&clock_gen, 5, 20*128-512, 0, 1, 0); /* 800/20 = 40MHz */
/* MS6/CLK6 is unused. */
/* MS7/CLK7 is unused. */
/* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
sample_rate_set(10000000);
si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL);
// soft reset
// uint8_t resetdata[] = { 177, 0xac };
// si5351c_write(&clock_gen, resetdata, sizeof(resetdata));
si5351c_reset_pll(&clock_gen);
si5351c_enable_clock_outputs(&clock_gen);
//FIXME disable I2C
/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);
/*
* 12MHz clock is entering LPC XTAL1/OSC input now.
* On HackRF One and Jawbreaker, there is a 12 MHz crystal at the LPC.
* Set up PLL1 to run from XTAL1 input.
*/
//FIXME a lot of the details here should be in a CGU driver
/* set xtal oscillator to low frequency mode */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_HF_MASK;
/* power on the oscillator and wait until stable */
CGU_XTAL_OSC_CTRL &= ~CGU_XTAL_OSC_CTRL_ENABLE_MASK;
/* Wait about 100us after Crystal Power ON */
delay(WAIT_CPU_CLOCK_INIT_DELAY);
/* use XTAL_OSC as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_XTAL) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
/* use XTAL_OSC as clock source for APB1 */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_XTAL);
/* use XTAL_OSC as clock source for APB3 */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_XTAL);
cpu_clock_pll1_low_speed();
/* use PLL1 as clock source for BASE_M4_CLK (CPU) */
CGU_BASE_M4_CLK = (CGU_BASE_M4_CLK_CLK_SEL(CGU_SRC_PLL1) | CGU_BASE_M4_CLK_AUTOBLOCK(1));
/* use XTAL_OSC as clock source for PLL0USB */
CGU_PLL0USB_CTRL = CGU_PLL0USB_CTRL_PD(1)
| CGU_PLL0USB_CTRL_AUTOBLOCK(1)
| CGU_PLL0USB_CTRL_CLK_SEL(CGU_SRC_XTAL);
while (CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK);
/* configure PLL0USB to produce 480 MHz clock from 12 MHz XTAL_OSC */
/* Values from User Manual v1.4 Table 94, for 12MHz oscillator. */
CGU_PLL0USB_MDIV = 0x06167FFA;
CGU_PLL0USB_NP_DIV = 0x00302062;
CGU_PLL0USB_CTRL |= (CGU_PLL0USB_CTRL_PD(1)
| CGU_PLL0USB_CTRL_DIRECTI(1)
| CGU_PLL0USB_CTRL_DIRECTO(1)
| CGU_PLL0USB_CTRL_CLKEN(1));
/* power on PLL0USB and wait until stable */
CGU_PLL0USB_CTRL &= ~CGU_PLL0USB_CTRL_PD_MASK;
while (!(CGU_PLL0USB_STAT & CGU_PLL0USB_STAT_LOCK_MASK));
/* use PLL0USB as clock source for USB0 */
CGU_BASE_USB0_CLK = CGU_BASE_USB0_CLK_AUTOBLOCK(1)
| CGU_BASE_USB0_CLK_CLK_SEL(CGU_SRC_PLL0USB);
/* Switch peripheral clock over to use PLL1 (204MHz) */
CGU_BASE_PERIPH_CLK = CGU_BASE_PERIPH_CLK_AUTOBLOCK(1)
| CGU_BASE_PERIPH_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB1 clock over to use PLL1 (204MHz) */
CGU_BASE_APB1_CLK = CGU_BASE_APB1_CLK_AUTOBLOCK(1)
| CGU_BASE_APB1_CLK_CLK_SEL(CGU_SRC_PLL1);
/* Switch APB3 clock over to use PLL1 (204MHz) */
CGU_BASE_APB3_CLK = CGU_BASE_APB3_CLK_AUTOBLOCK(1)
| CGU_BASE_APB3_CLK_CLK_SEL(CGU_SRC_PLL1);
CGU_BASE_SSP0_CLK = CGU_BASE_SSP0_CLK_AUTOBLOCK(1)
| CGU_BASE_SSP0_CLK_CLK_SEL(CGU_SRC_PLL1);
CGU_BASE_SSP1_CLK = CGU_BASE_SSP1_CLK_AUTOBLOCK(1)
| CGU_BASE_SSP1_CLK_CLK_SEL(CGU_SRC_PLL1);
#if (defined JAWBREAKER || defined HACKRF_ONE)
/* Disable unused clocks */
/* Start with PLLs */
CGU_PLL0AUDIO_CTRL = CGU_PLL0AUDIO_CTRL_PD(1);
/* Dividers */
CGU_IDIVA_CTRL = CGU_IDIVA_CTRL_PD(1);
CGU_IDIVB_CTRL = CGU_IDIVB_CTRL_PD(1);
CGU_IDIVC_CTRL = CGU_IDIVC_CTRL_PD(1);
CGU_IDIVD_CTRL = CGU_IDIVD_CTRL_PD(1);
CGU_IDIVE_CTRL = CGU_IDIVE_CTRL_PD(1);
/* Base clocks */
CGU_BASE_SPIFI_CLK = CGU_BASE_SPIFI_CLK_PD(1); /* SPIFI is only used at boot */
CGU_BASE_USB1_CLK = CGU_BASE_USB1_CLK_PD(1); /* USB1 is not exposed on HackRF */
CGU_BASE_PHY_RX_CLK = CGU_BASE_PHY_RX_CLK_PD(1);
CGU_BASE_PHY_TX_CLK = CGU_BASE_PHY_TX_CLK_PD(1);
CGU_BASE_LCD_CLK = CGU_BASE_LCD_CLK_PD(1);
CGU_BASE_VADC_CLK = CGU_BASE_VADC_CLK_PD(1);
CGU_BASE_SDIO_CLK = CGU_BASE_SDIO_CLK_PD(1);
CGU_BASE_UART0_CLK = CGU_BASE_UART0_CLK_PD(1);
CGU_BASE_UART1_CLK = CGU_BASE_UART1_CLK_PD(1);
CGU_BASE_UART2_CLK = CGU_BASE_UART2_CLK_PD(1);
CGU_BASE_UART3_CLK = CGU_BASE_UART3_CLK_PD(1);
CGU_BASE_OUT_CLK = CGU_BASE_OUT_CLK_PD(1);
CGU_BASE_AUDIO_CLK = CGU_BASE_AUDIO_CLK_PD(1);
CGU_BASE_CGU_OUT0_CLK = CGU_BASE_CGU_OUT0_CLK_PD(1);
CGU_BASE_CGU_OUT1_CLK = CGU_BASE_CGU_OUT1_CLK_PD(1);
/* Disable unused peripheral clocks */
CCU1_CLK_APB1_CAN1_CFG = 0;
CCU1_CLK_APB1_I2S_CFG = 0;
CCU1_CLK_APB1_MOTOCONPWM_CFG = 0;
CCU1_CLK_APB3_ADC0_CFG = 0;
CCU1_CLK_APB3_ADC1_CFG = 0;
CCU1_CLK_APB3_CAN0_CFG = 0;
CCU1_CLK_APB3_DAC_CFG = 0;
CCU1_CLK_M4_DMA_CFG = 0;
CCU1_CLK_M4_EMC_CFG = 0;
CCU1_CLK_M4_EMCDIV_CFG = 0;
CCU1_CLK_M4_ETHERNET_CFG = 0;
CCU1_CLK_M4_LCD_CFG = 0;
CCU1_CLK_M4_QEI_CFG = 0;
CCU1_CLK_M4_RITIMER_CFG = 0;
CCU1_CLK_M4_SCT_CFG = 0;
CCU1_CLK_M4_SDIO_CFG = 0;
CCU1_CLK_M4_SPIFI_CFG = 0;
CCU1_CLK_M4_TIMER0_CFG = 0;
CCU1_CLK_M4_TIMER1_CFG = 0;
CCU1_CLK_M4_TIMER2_CFG = 0;
CCU1_CLK_M4_TIMER3_CFG = 0;
CCU1_CLK_M4_UART1_CFG = 0;
CCU1_CLK_M4_USART0_CFG = 0;
CCU1_CLK_M4_USART2_CFG = 0;
CCU1_CLK_M4_USART3_CFG = 0;
CCU1_CLK_M4_USB1_CFG = 0;
CCU1_CLK_M4_VADC_CFG = 0;
// CCU1_CLK_SPIFI_CFG = 0;
// CCU1_CLK_USB1_CFG = 0;
// CCU1_CLK_VADC_CFG = 0;
// CCU2_CLK_APB0_UART1_CFG = 0;
// CCU2_CLK_APB0_USART0_CFG = 0;
// CCU2_CLK_APB2_USART2_CFG = 0;
// CCU2_CLK_APB2_USART3_CFG = 0;
// CCU2_CLK_APLL_CFG = 0;
// CCU2_CLK_SDIO_CFG = 0;
#endif
#ifdef RAD1O
/* Disable unused clock outputs. They generate noise. */
scu_pinmux(CLK0, SCU_CLK_IN | SCU_CONF_FUNCTION7);
scu_pinmux(CLK2, SCU_CLK_IN | SCU_CONF_FUNCTION7);
#endif
}