void si_pmu_res_init(struct si_pub *sih)
{
struct bcma_device *core;
u32 min_mask = 0, max_mask = 0;
/* */
core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
/* */
si_pmu_res_masks(sih, &min_mask, &max_mask);
/* */
/* */
if (max_mask)
bcma_write32(core, CHIPCREGOFFS(max_res_mask), max_mask);
/* */
if (min_mask)
bcma_write32(core, CHIPCREGOFFS(min_res_mask), min_mask);
/* */
mdelay(2);
}
/* initialize PMU resources */
void si_pmu_res_init(struct si_pub *sih)
{
chipcregs_t *cc;
uint origidx;
u32 min_mask = 0, max_mask = 0;
/* Remember original core before switch to chipc */
origidx = ai_coreidx(sih);
cc = ai_setcoreidx(sih, SI_CC_IDX);
/* Determine min/max rsrc masks */
si_pmu_res_masks(sih, &min_mask, &max_mask);
/* It is required to program max_mask first and then min_mask */
/* Program max resource mask */
if (max_mask)
W_REG(&cc->max_res_mask, max_mask);
/* Program min resource mask */
if (min_mask)
W_REG(&cc->min_res_mask, min_mask);
/* Add some delay; allow resources to come up and settle. */
mdelay(2);
/* Return to original core */
ai_setcoreidx(sih, origidx);
}
