t_stat i8274_svc (UNIT *uptr)
{
int32 temp;
sim_activate (&i8274_unit, i8274_unit.wait); /* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG)
return temp; /* no char or error? */
i8274_unit.buf = temp & 0xFF; /* Save char */
rr0a |= 0x01; /* Set rx char ready */
/* Do any special character handling here */
i8274_unit.pos++;
return SCPE_OK;
}
t_stat ptr_svc (UNIT *uptr)
{
int32 temp;
if ((uptr->flags & UNIT_ATT) == 0) { /* attached? */
if (ptr_wait) /* if wait, clr ioh */
ptr_wait = ioh = 0;
if ((cpls & CPLS_PTR) || ptr_stopioe)
return SCPE_UNATT;
return SCPE_OK;
}
if ((uptr->flags & UNIT_ASCII) && (ptr_state == 0)) /* ASCII mode, alpha read? */
temp = ptr_get_ascii (uptr); /* get processed char */
else if ((temp = getc (uptr->fileref)) != EOF) /* no, get raw char */
uptr->pos = uptr->pos + 1; /* if not eof, count */
if (temp == EOF) { /* end of file? */
if (ptr_wait) /* if wait, clr ioh */
ptr_wait = ioh = 0;
if (feof (uptr->fileref)) {
if ((cpls & CPLS_PTR) || ptr_stopioe)
printf ("PTR end of file\n");
else return SCPE_OK;
}
else perror ("PTR I/O error");
clearerr (uptr->fileref);
return SCPE_IOERR;
}
if (ptr_state == 0) /* alpha */
uptr->buf = temp & 0377;
else if (temp & 0200) { /* binary */
ptr_state = ptr_state - 6;
uptr->buf = uptr->buf | ((temp & 077) << ptr_state);
}
if (ptr_state == 0) { /* done? */
if (cpls & CPLS_PTR) { /* completion pulse? */
iosta = iosta & ~IOS_PTR; /* clear flag */
IO = uptr->buf; /* fill IO */
ios = 1; /* restart */
cpls = cpls & ~CPLS_PTR;
}
else { /* no, interrupt */
iosta = iosta | IOS_PTR; /* set flag */
dev_req_int (ptr_sbs); /* req interrupt */
}
}
else sim_activate (uptr, uptr->wait); /* get next char */
return SCPE_OK;
}
t_stat tto_svc (UNIT *uptr)
{
int32 c;
t_stat r;
c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags) | TTUF_KSR);
if (c >= 0) {
if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
sim_activate (uptr, uptr->wait); /* try again */
return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
}
}
dev_done = dev_done | INT_TTO; /* set ready */
uptr->pos = uptr->pos + 1;
return SCPE_OK;
}
t_stat ttp_reset (DEVICE *dptr)
{
if (dptr->flags & DEV_DIS)
sim_cancel (&ttp_unit[TTI]);
else sim_activate (&ttp_unit[TTI], KBD_WAIT (ttp_unit[TTI].wait, lfc_poll));
sim_cancel (&ttp_unit[TTO]);
CLR_INT (v_TTP); /* clear int */
CLR_ENB (v_TTP);
CLR_INT (v_TTP + 1); /* disable int */
CLR_ENB (v_TTP + 1);
ttp_karm = ttp_tarm = 0; /* disarm int */
ttp_cmd = 0;
ttp_sta = 0;
ttp_kchp = 0;
return SCPE_OK;
}
t_stat
clk_reset(DEVICE * dptr)
{
if (CPUT(HAS_LTCR)) /* reg there? */
clk_fie = clk_fnxm = 0;
else
clk_fie = clk_fnxm = 1; /* no, BEVENT */
clk_tps = clk_default; /* set default tps */
clk_csr = CSR_DONE; /* set done */
CLR_INT(CLK);
sim_rtcn_init(clk_unit.wait, TMR_CLK); /* init line clock */
sim_activate(&clk_unit, clk_unit.wait); /* activate unit */
tmr_poll = clk_unit.wait; /* set timer poll */
tmxr_poll = clk_unit.wait; /* set mux poll */
return SCPE_OK;
}
t_stat fe_reset (DEVICE *dptr)
{
tmxr_set_console_units (&fe_unit[0], &fe_unit[1]);
fei_unit.buf = feo_unit.buf = 0;
M[FE_CTYIN] = M[FE_CTYOUT] = 0;
M[FE_KLININ] = M[FE_KLINOUT] = 0;
M[FE_KEEPA] = INT64_C(0003740000000); /* PARITY STOP, CRM, DP PAREN, CACHE EN, 1MSTMR, TRAPEN */
kaf_unit.u3 = 0;
kaf_unit.u4 = 0;
apr_flg = apr_flg & ~(APRF_ITC | APRF_CON);
sim_activate (&fei_unit, KBD_WAIT (fei_unit.wait, tmxr_poll));
sim_activate_after (&kaf_unit, kaf_unit.wait);
return SCPE_OK;
}
t_stat rx_reset (DEVICE *dptr)
{
rx_csr = rx_dbr = 0; /* clear regs */
rx_esr = rx_ecode = 0; /* clear error */
rx_track = rx_sector = 0; /* clear addr */
rx_state = IDLE; /* ctrl idle */
CLR_INT (RX); /* clear int req */
sim_cancel (&rx_unit[1]); /* cancel drive 1 */
if (dptr->flags & DEV_DIS) sim_cancel (&rx_unit[0]); /* disabled? */
else if (rx_unit[0].flags & UNIT_BUF) { /* attached? */
rx_state = INIT_COMPLETE; /* yes, sched init */
sim_activate (&rx_unit[0], rx_swait * abs (1 - rx_unit[0].TRACK));
}
else rx_done (0, 0010); /* no, error */
return auto_config (0, 0); /* run autoconfig */
}
t_stat tti_svc (UNIT *uptr)
{
int32 c;
sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
return c;
if (c & SCPE_BREAK) /* break? */
tti_buf = RXDB_ERR | RXDB_FRM;
else tti_buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));
uptr->pos = uptr->pos + 1;
tti_csr = tti_csr | CSR_DONE;
if (tti_csr & CSR_IE)
tti_int = 1;
return SCPE_OK;
}
static t_stat set_if3_connect(UNIT *uptr, int32 val, char *cptr, void *desc)
{
if(uptr->flags & UNIT_DISABLE) {
TRACE_PRINT(ERROR_MSG, ("IF3[%d]: not enabled." NLP, uptr->u3));
return SCPE_OK;
}
if(val & UNIT_IF3_CONNECT) {
TRACE_PRINT((RXIRQ_MSG|TXIRQ_MSG), ("IF3[%d]: IRQ polling started..." NLP, uptr->u3));
sim_activate(uptr, 100000);
} else {
TRACE_PRINT((RXIRQ_MSG|TXIRQ_MSG), ("IF3[%d]: IRQ polling stopped." NLP, uptr->u3));
sim_cancel(uptr);
}
return (SCPE_OK);
}
t_stat fei_svc (UNIT *uptr)
{
int32 temp;
sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmxr_poll)));
/* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
return temp;
if (temp & SCPE_BREAK) /* ignore break */
return SCPE_OK;
uptr->buf = temp & 0177;
uptr->pos = uptr->pos + 1;
M[FE_CTYIN] = uptr->buf | FE_CVALID; /* put char in mem */
apr_flg = apr_flg | APRF_CON; /* interrupt KS10 */
return SCPE_OK;
}
int32 clkio (int32 inst, int32 fnc, int32 dat, int32 dev)
{
switch (inst) { /* case on opcode */
case ioOCP: /* OCP */
if (fnc & 015) /* only fnc 0,2 */
return IOBADFNC (dat);
CLR_INT (INT_CLK); /* reset ready */
if (fnc) /* fnc = 2? stop */
sim_cancel (&clk_unit);
else { /* fnc = 0? */
if (!sim_is_active (&clk_unit))
sim_activate (&clk_unit, /* activate */
sim_rtc_init (clk_unit.wait)); /* init calibr */
}
break;
case ioSKS: /* SKS */
if (fnc == 000) { /* clock skip !int */
if (!TST_INTREQ (INT_CLK))
return IOSKIP (dat);
}
else if ((fnc & 007) == 002) { /* mem parity? */
if (((fnc == 002) && !TST_INT (INT_MPE)) ||
((fnc == 012) && TST_INT (INT_MPE)))
return IOSKIP (dat);
}
else return IOBADFNC (dat); /* invalid fnc */
break;
case ioOTA: /* OTA */
if (fnc == 000) /* SMK */
dev_enb = dat;
else if (fnc == 010) { /* OTK */
C = (dat >> 15) & 1; /* set C */
if (cpu_unit.flags & UNIT_HSA) /* HSA included? */
dp = (dat >> 14) & 1; /* set dp */
if (cpu_unit.flags & UNIT_EXT) { /* ext opt? */
if (dat & 020000) { /* ext set? */
ext = 1; /* yes, set */
extoff_pending = 0;
}
else extoff_pending = 1; /* no, clr later */
}
sc = dat & 037; /* set sc */
}
else return IOBADFNC (dat);
t_stat read_card (int32 ilnt, int32 mod)
{
int32 i, cbn, c1, c2, cbufsz;
t_stat r;
if (sim_is_active (&cdr_unit)) { /* busy? */
sim_cancel (&cdr_unit); /* cancel */
if ((r = cdr_svc (&cdr_unit))) /* process */
return r;
}
ind[IN_READ] = ind[IN_LST] = s1sel = s2sel = 0; /* default stacker */
cbn = ((ilnt == 2) || (ilnt == 5)) && (mod == BCD_C); /* col binary? */
cbufsz = (cbn)? 2 * CBUFSIZE: CBUFSIZE; /* buffer size */
for (i = 0; i < (2 * CBUFSIZE) + 1; i++) /* clear extended buf */
cdr_buf[i] = 0;
if ((cdr_unit.flags & UNIT_ATT) != 0) /* attached? */
r = cdr_read_file (cdr_buf, cbufsz); /* read from file */
else if ((cdr_unit.flags & UNIT_CONS) != 0) /* default to console? */
r = cdr_read_cons (cdr_buf, cbufsz); /* read from console */
else return SCPE_UNATT; /* else can't read */
if (r != SCPE_OK) /* read error? */
return r; /* can't read */
if (cbn) { /* column binary? */
for (i = 0; i < CDR_WIDTH; i++) {
if (conv_old) {
c1 = ascii2bcd (cdr_buf[i]);
c2 = ascii2bcd (cdr_buf[CDR_WIDTH + i]);
}
else {
c1 = ascii2bcd (cdr_buf[2 * i]);
c2 = ascii2bcd (cdr_buf[(2 * i) + 1]);
}
M[CD_CBUF1 + i] = (M[CD_CBUF1 + i] & WM) | c1;
M[CD_CBUF2 + i] = (M[CD_CBUF2 + i] & WM) | c2;
M[CDR_BUF + i] = colbin_to_bcd ((c1 << 6) | c2);
}
} /* end if col bin */
else { /* normal read */
for (i = 0; i < CDR_WIDTH; i++) { /* cvt to BCD */
c1 = ascii2bcd (cdr_buf[i]);
M[CDR_BUF + i] = (M[CDR_BUF + i] & WM) | c1;
}
}
M[CDR_BUF - 1] = 060; /* mem mark */
sim_activate (&cdr_unit, cdr_unit.wait); /* activate */
return SCPE_OK;
}
/*
* Command codes
*
* xxxx01 Start punch.
* xxxx10 Stop punch.
* xx1xxx Start in Previous shift, else alpha.
* x1xxxx Graphics mode.
* 1xxxxx Punch blanks.
*/
void ptp_nsi_cmd(int dev, uint32 cmd) {
int i;
UNIT *uptr = NULL;
/* Find the unit from dev */
for (i = 0; i < ptp_dev.numunits; i++) {
if (GET_UADDR(ptp_unit[i].flags) == dev) {
uptr = &ptp_unit[i];
break;
}
}
/* Should not happen, but just in case */
if (uptr == NULL)
return;
/* Ignore this command if not a SI device */
if (SI_TYPE(uptr->flags))
return;
if (cmd & 02) {
if (uptr->CMD & BUSY)
uptr->CMD |= DISC;
return;
}
if (cmd & 01) {
if (uptr->CMD & BUSY || (uptr->flags & UNIT_ATT) == 0) {
uptr->STATUS |= OPAT;
chan_set_done(dev);
return;
}
if (cmd & 010)
uptr->CMD &= ALPHA_MODE;
else
uptr->CMD = ALPHA_MODE;
if (cmd & 020)
uptr->CMD |= BIN_MODE;
if ((cmd & 040) == 0)
uptr->CMD |= PUN_BLNK;
uptr->CMD |= BUSY;
uptr->STATUS = 0;
sim_activate(uptr, uptr->wait);
chan_clr_done(dev);
}
}
/* Start off a terminal controller command */
t_stat dtc_cmd(uint16 cmd, uint16 dev, uint8 chan, uint16 *wc)
{
UNIT *uptr;
int ttu;
int buf;
uptr = &dtc_unit[0];
/* If unit disabled return error */
if (uptr->flags & UNIT_DIS)
return SCPE_NODEV;
if ((uptr->flags & UNIT_ATT) == 0)
return SCPE_UNATT;
/* Check if drive is ready to recieve a command */
if ((uptr->CMD & DTC_RDY) == 0)
return SCPE_BUSY;
uptr->CMD = chan;
ttu = (*wc & DTCSTA_TTU) >> 5;
buf = (*wc & DTCSTA_BUF);
/* Set the Terminal unit. */
if (ttu == 0)
uptr->LINE = -1;
else {
uptr->LINE = buf + ((ttu-1) * 15);
}
if (*wc & DTCSTA_GM)
uptr->CMD |= DTC_IGNGM;
if (cmd & DTCSTA_READ)
uptr->CMD |= DTC_RD;
else if (cmd & DTCSTA_INHIBIT)
uptr->CMD |= DTC_INQ;
else
uptr->CMD |= DTC_WR;
if (cmd & DTCSTA_BINARY)
uptr->CMD |= DTC_BIN;
sim_debug(DEBUG_CMD, &dtc_dev, "Datacomm access %s %06o %d %04o\n",
(uptr->CMD & DTC_RD) ? "read" : ((uptr->CMD & DTC_INQ) ? "inq" :
((uptr->CMD & DTC_WR) ? "write" : "unknown")),
uptr->CMD, uptr->LINE, *wc);
sim_activate(uptr, 5000);
return SCPE_OK;
}
t_stat ttix_reset (DEVICE *dptr)
{
int32 ln, itto;
ttx_enbdis (dptr->flags & DEV_DIS); /* sync enables */
if (ttix_unit.flags & UNIT_ATT) /* if attached, */
sim_activate (&ttix_unit, tmxr_poll); /* activate */
else sim_cancel (&ttix_unit); /* else stop */
for (ln = 0; ln < TTX_LINES; ln++) { /* for all lines */
ttix_buf[ln] = 0; /* clear buf, */
itto = (INT_TTI1 << ln); /* interrupt */
dev_done = dev_done & ~itto; /* clr done, int */
int_req = int_req & ~itto;
int_enable = int_enable | itto; /* set enable */
}
return SCPE_OK;
}
t_stat tto_svc (UNIT *uptr)
{
int32 c;
t_stat r;
c = tty_buf; /* get char */
tty_buf = tty_shin; /* shift in */
tty_shin = 0377; /* line inactive */
if ((r = tto_out (c)) != SCPE_OK) { /* output; error? */
sim_activate (uptr, uptr->wait); /* retry */
return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
}
ttyio (&tty_dib, ioENF, 0); /* set flag */
return ttp_out (c); /* punch if enabled */
}
t_stat tti_svc (UNIT *uptr)
{
int32 c;
sim_activate (uptr, KBD_WAIT (uptr->wait, clk_cosched (tmr_poll)));
/* continue poll */
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) /* no char or error? */
return c;
if (c & SCPE_BREAK) /* break? */
uptr->buf = 0;
else uptr->buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));
uptr->pos = uptr->pos + 1;
tti_csr = tti_csr | CSR_DONE;
if (tti_csr & CSR_IE)
SET_INT (TTI);
return SCPE_OK;
}
t_stat tti_svc (UNIT *uptr)
{
int32 temp;
sim_activate (&tti_unit, tti_unit.wait); /* continue poll */
if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp; /* no char or error? */
tti_unit.buf = temp & 0177;
/* --- BEGIN MODIFIED CODE --- */
if (tti_unit.flags & UNIT_DASHER) /* translate input */
translate_in();
/* --- END MODIFIED CODE --- */
dev_busy = dev_busy & ~INT_TTI; /* clear busy */
dev_done = dev_done | INT_TTI; /* set done */
int_req = (int_req & ~INT_DEV) | (dev_done & ~dev_disable);
tti_unit.pos = tti_unit.pos + 1;
return SCPE_OK;
}
t_stat tto_svc (UNIT *uptr)
{
int32 c;
t_stat r;
c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags));
if (c >= 0) {
if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
sim_activate (uptr, uptr->wait); /* try again */
return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
}
}
tto_csr = tto_csr | CSR_DONE;
if (tto_csr & CSR_IE) SET_INT (TTO);
uptr->pos = uptr->pos + 1;
return SCPE_OK;
}
void ports_sysgen(uint8 cid)
{
cio_entry cqe = {0};
uint8 app_data[4] = {0};
ports_crc = 0;
cqe.opcode = 3; /* Sysgen success! */
/* It's not clear why we put a response in both the express
* and the full queue. */
cio_cexpress(cid, PPQESIZE, &cqe, app_data);
cio_cqueue(cid, CIO_STAT, PPQESIZE, &cqe, app_data);
ports_int_cid = cid;
sim_activate(&ports_unit[2], DELAY_STD);
}
uint32 ttp (uint32 dev, uint32 op, uint32 dat)
{
int32 xmt = dev & 1;
int32 t, old_cmd;
switch (op) { /* case IO op */
case IO_ADR: /* select */
return BY; /* byte only */
case IO_RD: /* read */
ttp_kchp = 0; /* clr chr pend */
ttp_sta = ttp_sta & ~STA_OVR; /* clr overrun */
return ttp_unit[TTI].buf; /* return buf */
case IO_WD: /* write */
ttp_unit[TTO].buf = dat & 0xFF; /* store char */
ttp_sta = ttp_sta | STA_BSY; /* set busy */
sim_activate (&ttp_unit[TTO], ttp_unit[TTO].wait);
break;
case IO_SS: /* status */
if (xmt) t = ttp_sta & STA_XMT; /* xmt? just busy */
else { /* rcv */
t = ttp_sta & STA_RCV; /* get static */
if (!ttp_kchp) /* no char? busy */
t = t | STA_BSY;
if (t & SET_EX) /* test for ex */
t = t | STA_EX;
}
return t;
case IO_OC: /* command */
old_cmd = ttp_cmd; /* old cmd */
if (dat & CMD_TYP) { /* type 1? */
ttp_cmd = (ttp_cmd & 0xFF) | (dat << 8);
if (ttp_cmd & CMD_WRT) /* write? */
ttp_tarm = int_chg (v_TTP + 1, dat, ttp_tarm);
else ttp_karm = int_chg (v_TTP, dat, ttp_karm);
}
else ttp_cmd = (ttp_cmd & ~0xFF) | dat;
break;
}
return 0;
}
t_stat lpt_end_line (UNIT *uptr)
{
uint32 i, col, row, bufw, colbin;
const char *pch;
char bcd, lpt_cbuf[LPT_CHRLNT + 1];
t_uint64 dat;
pch = pch_table[GET_PCHAIN (lpt_unit.flags)]; /* get print chain */
for (col = 0; col < (LPT_CHRLNT + 1); col++) /* clear ascii buf */
lpt_cbuf[col] = ' ';
for (col = 0; col < 72; col++) { /* proc 72 columns */
colbin = 0;
dat = bit_masks[35 - (col % 36)]; /* mask for column */
for (row = 0; row < 12; row++) { /* proc 12 rows */
bufw = (row * 2) + (col / 36); /* index to buffer */
if (lpt_bbuf[bufw] & dat)
colbin |= col_masks[row];
}
bcd = colbin_to_bcd (colbin); /* column bin -> BCD */
lpt_cbuf[col] = pch[bcd]; /* -> ASCII */
}
for (i = LPT_CHRLNT; (i > 0) &&
(lpt_cbuf[i - 1] == ' '); --i) ; /* trim spaces */
lpt_cbuf[i] = 0; /* append nul */
if (uptr->flags & UNIT_ATT) { /* file? */
fputs (lpt_cbuf, uptr->fileref); /* write line */
fputc ('\n', uptr->fileref); /* append nl */
uptr->pos = ftell (uptr->fileref); /* update position */
if (ferror (uptr->fileref)) { /* error? */
sim_perror ("LPT I/O error");
clearerr (uptr->fileref);
return SCPE_IOERR;
}
}
else if (uptr->flags & UNIT_CONS) { /* print to console? */
for (i = 0; lpt_cbuf[i] != 0; i++)
sim_putchar (lpt_cbuf[i]);
sim_putchar ('\r');
sim_putchar ('\n');
}
else return SCPE_UNATT; /* otherwise error */
lpt_sta = LPS_END; /* end line state */
sim_cancel (uptr); /* cancel current */
sim_activate (uptr, lpt_tstop); /* long timer */
return SCPE_OK;
}
t_stat rx_rd (int32 *data, int32 PA, int32 access)
{
switch ((PA >> 1) & 1) { /* decode PA<1> */
case 0: /* RXCS */
rx_csr = rx_csr & RXCS_IMP; /* clear junk */
*data = rx_csr & RXCS_ROUT;
return SCPE_OK;
case 1: /* RXDB */
if (rx_state == EMPTY) { /* empty? */
sim_activate (&rx_unit[0], rx_xwait);
rx_csr = rx_csr & ~RXCS_TR; } /* clear xfer */
*data = rx_dbr; /* return data */
return SCPE_OK; } /* end switch PA */
#ifdef GAMEBOY
return SCPE_ARG;
#endif
}
/* Attach master unit */
t_stat
dtc_attach(UNIT * uptr, CONST char *cptr)
{
int i;
t_stat r;
r = tmxr_attach(&dtc_desc, uptr, cptr); /* attach */
if (r != SCPE_OK)
return r; /* error */
sim_activate(&dtc_unit[1], 100); /* quick poll */
for (i = 0; i < DTC_MLINES; i++) {
dtc_lstatus[i] = BufNotReady; /* Device not connected */
}
uptr->CMD = DTC_RDY;
iostatus |= DTC_FLAG;
return SCPE_OK;
}
t_stat muxi_put_char (uint32 c, uint32 ln)
{
uint32 st;
st = chan_WrMemB (mux_dib.dva, c); /* write char */
if (CHS_IFERR (st)) /* channel error? */
return mux_chan_err (st);
st = chan_WrMemB (mux_dib.dva, ln); /* write line */
if (CHS_IFERR (st)) /* channel error? */
return mux_chan_err (st);
if (st == CHS_ZBC) { /* bc == 0? */
muxc_cmd = MUXC_END; /* end state */
sim_activate (&mux_unit[MUXC], chan_ctl_time); /* quick schedule */
}
io_sclr_req (mux_rint, 1); /* req ext intr */
return SCPE_OK;
}
t_stat tto_svc (UNIT *uptr)
{
int32 c;
t_stat r;
c = tto_unit.buf & 0177;
if ((tto_unit.flags & UNIT_DASHER) && (c == 031))
c = '\b';
if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
sim_activate (uptr, uptr->wait); /* try again */
return ((r == SCPE_STALL)? SCPE_OK : r); /* !stall? report */
}
DEV_CLR_BUSY( INT_TTO ) ;
DEV_SET_DONE( INT_TTO ) ;
DEV_UPDATE_INTR ;
++(tto_unit.pos);
return SCPE_OK;
}
int32 ttox (int32 dev, int32 pulse, int32 dat)
{
int32 ln = ttx_getln (dev, pulse); /* line # */
if (ln > ttx_lines)
return dat;
if (pulse & 001) { /* TSF */
if (ttox_test_done (ln))
dat = dat | IOT_SKP;
}
if (pulse & 002) /* clear flag */
ttox_clr_done (ln);
if (pulse & 004) { /* load buffer */
sim_activate (&ttox_unit[ln], ttox_unit[ln].wait); /* activate unit */
ttox_buf[ln] = dat & 0377; /* load buffer */
}
return dat;
}
t_stat clk_reset (DEVICE *dptr)
{
sim_register_clock_unit (&clk_unit); /* declare clock unit */
if (CPUT (HAS_LTCR)) /* reg there? */
clk_fie = clk_fnxm = 0;
else {
clk_fnxm = 1; /* no LTCR, set nxm */
clk_fie = CPUO (OPT_BVT); /* ie = 1 unless no BEVENT */
}
clk_tps = clk_default; /* set default tps */
clk_csr = CSR_DONE; /* set done */
CLR_INT (CLK);
sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init line clock */
sim_activate (&clk_unit, clk_unit.wait); /* activate unit */
tmr_poll = clk_unit.wait; /* set timer poll */
tmxr_poll = clk_unit.wait; /* set mux poll */
return SCPE_OK;
}
void dq_goc (int32 fnc, int32 drv, int32 time)
{
int32 t;
t = sim_is_active (&dqc_unit[drv]);
if (t) { /* still seeking? */
sim_cancel (&dqc_unit[drv]); /* cancel */
time = time + t; /* include seek time */
}
dqc_sta[drv] = 0; /* clear status */
dq_ptr = 0; /* init buf ptr */
dqc_busy = drv + 1; /* set busy */
dqd_xfer = 1; /* xfer in prog */
dqc_unit[drv].FNC = fnc; /* save function */
sim_activate (&dqc_unit[drv], time); /* activate unit */
return;
}
t_stat ry_reset (DEVICE *dptr)
{
ry_csr = ry_dbr = 0; /* clear registers */
ry_esr = ry_ecode = 0; /* clear error */
ry_ba = ry_wc = 0; /* clear wc, ba */
ry_track = ry_sector = 0; /* clear trk, sector */
ry_state = IDLE; /* ctrl idle */
CLR_INT (RY); /* clear int req */
sim_cancel (&ry_unit[1]); /* cancel drive 1 */
if (dptr->flags & UNIT_DIS) /* disabled? */
sim_cancel (&ry_unit[0]);
else if (ry_unit[0].flags & UNIT_BUF) { /* attached? */
ry_state = INIT_COMPLETE; /* yes, sched init */
sim_activate (&ry_unit[0], ry_swait * abs (1 - ry_unit[0].TRACK));
}
else ry_done (RYES_ID, 0010); /* no, error */
return auto_config (0, 0); /* run autoconfig */
}
