static void write_txb (struct hw *me, struct mn103ser *serial, unsigned_word serial_reg, const void *source, unsigned nr_bytes) { if ( nr_bytes == 1 ) { SIM_DESC sd = hw_system (me); int status; serial->device[serial_reg].txb = *(unsigned8 *)source; status = dv_sockser_status (sd); if (!(status & DV_SOCKSER_DISCONNECTED)) { dv_sockser_write(sd, * (char*) source); } else { sim_io_write_stdout(sd, (char *)source, 1); sim_io_flush_stdout(sd); } hw_port_event (me, serial_reg+SERIAL0_SEND, 1); } else { hw_abort (me, "bad write size of %d bytes to SC%dTXB.", nr_bytes, serial_reg); } }
static void write_txb (struct hw *me, struct mn103ser *serial, unsigned_word serial_reg, const void *source, unsigned nr_bytes) { if ( nr_bytes == 1 ) { serial->device[serial_reg].txb = *(unsigned8 *)source; if(USE_SOCKSER_P) { dv_sockser_write(hw_system (me), * (char*) source); } else { sim_io_write_stdout(hw_system (me), (char *)source, 1); sim_io_flush_stdout(hw_system (me)); } hw_port_event (me, serial_reg+SERIAL0_SEND, 1); } else { hw_abort (me, "bad write size of %d bytes to SC%dTXB.", nr_bytes, serial_reg); } }
void m68hc11sio_tx_poll (struct hw *me, void *data) { SIM_DESC sd; struct m68hc11sio *controller; sim_cpu *cpu; controller = hw_data (me); sd = hw_system (me); cpu = STATE_CPU (sd, 0); cpu->ios[M6811_SCSR] |= M6811_TDRE; cpu->ios[M6811_SCSR] |= M6811_TC; /* Transmitter is enabled and we have something to send. */ if ((cpu->ios[M6811_SCCR2] & M6811_TE) && controller->tx_has_char) { cpu->ios[M6811_SCSR] &= ~M6811_TDRE; cpu->ios[M6811_SCSR] &= ~M6811_TC; controller->tx_has_char = 0; switch (controller->backend) { case sio_tcp: dv_sockser_write (sd, controller->tx_char); break; case sio_stdio: sim_io_write_stdout (sd, &controller->tx_char, 1); sim_io_flush_stdout (sd); break; default: break; } } if (controller->tx_poll_event) { hw_event_queue_deschedule (me, controller->tx_poll_event); controller->tx_poll_event = 0; } if ((cpu->ios[M6811_SCCR2] & M6811_TE) && ((cpu->ios[M6811_SCSR] & M6811_TC) == 0)) { unsigned long clock_cycle; /* Compute CPU clock cycles to wait for the next character. */ clock_cycle = controller->data_length * controller->baud_cycle; controller->tx_poll_event = hw_event_queue_schedule (me, clock_cycle, m68hc11sio_tx_poll, NULL); } interrupts_update_pending (&cpu->cpu_interrupts); }
unsigned bfin_uart_write_buffer (struct hw *me, const unsigned char *buffer, unsigned nr_bytes) { SIM_DESC sd = hw_system (me); int status = dv_sockser_status (sd); if (status & DV_SOCKSER_DISCONNECTED) { sim_io_write_stdout (sd, (const char *) buffer, nr_bytes); sim_io_flush_stdout (sd); } else { /* Normalize errors to a value of 0. */ int ret = dv_sockser_write_buffer (sd, buffer, nr_bytes); nr_bytes = CLAMP (ret, 0, nr_bytes); } return nr_bytes; }
/* Send enqueued characters from tx_fifo and trigger TX interrupt. Receive characters into rx_fifo and trigger RX interrupt. */ void tx3904sio_tickle(struct hw *me) { struct tx3904sio* controller = hw_data(me); int c; char cc; unsigned_4 last_int, next_int; /* HW_TRACE ((me, "tickle backend: %02x", controller->backend)); */ switch(controller->backend) { case sio_tcp: while(tx3904sio_fifo_nonempty(me, & controller->tx_fifo)) { cc = tx3904sio_fifo_pop(me, & controller->tx_fifo); dv_sockser_write(hw_system(me), cc); HW_TRACE ((me, "tcp output: %02x", cc)); } c = dv_sockser_read(hw_system(me)); while(c != -1) { cc = (char) c; HW_TRACE ((me, "tcp input: %02x", cc)); tx3904sio_fifo_push(me, & controller->rx_fifo, cc); c = dv_sockser_read(hw_system(me)); } break; case sio_stdio: while(tx3904sio_fifo_nonempty(me, & controller->tx_fifo)) { cc = tx3904sio_fifo_pop(me, & controller->tx_fifo); sim_io_write_stdout(hw_system(me), & cc, 1); sim_io_flush_stdout(hw_system(me)); HW_TRACE ((me, "stdio output: %02x", cc)); } c = sim_io_poll_read(hw_system(me), 0 /* stdin */, & cc, 1); while(c == 1) { HW_TRACE ((me, "stdio input: %02x", cc)); tx3904sio_fifo_push(me, & controller->rx_fifo, cc); c = sim_io_poll_read(hw_system(me), 0 /* stdin */, & cc, 1); } break; default: hw_abort(me, "Illegal backend mode: %d", controller->backend); } /* Update RDIS / TDIS flags */ last_int = controller->sdisr & controller->sdicr; /* HW_TRACE ((me, "tickle - sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */ if(tx3904sio_fifo_nonempty(me, & controller->rx_fifo)) SDISR_SET_RDIS(controller); if(! tx3904sio_fifo_nonempty(me, & controller->tx_fifo)) SDISR_SET_TDIS(controller); next_int = controller->sdisr & controller->sdicr; /* HW_TRACE ((me, "tickle + sdisr %08x sdicr %08x", controller->sdisr, controller->sdicr)); */ if(~last_int & next_int) /* any bits set? */ hw_port_event(me, INT_PORT, 1); if(last_int & ~next_int) /* any bits cleared? */ hw_port_event(me, INT_PORT, 0); /* Add periodic polling for this port, if it's not already going. */ if(controller->poll_event == NULL) { controller->poll_event = hw_event_queue_schedule (me, 1000, tx3904sio_poll, NULL); } }