static struct cphy *mv88e1xxx_phy_create(struct net_device *dev, int phy_addr, const struct mdio_ops *mdio_ops) { struct adapter *adapter = netdev_priv(dev); struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL); if (!cphy) return NULL; cphy_init(cphy, dev, phy_addr, &mv88e1xxx_ops, mdio_ops); if ((board_info(adapter)->caps & SUPPORTED_TP) && board_info(adapter)->chip_phy == CHBT_PHY_88E1111) { (void) simple_mdio_write(cphy, MV88E1XXX_EXTENDED_ADDR_REGISTER, 0xB); (void) simple_mdio_write(cphy, MV88E1XXX_EXTENDED_REGISTER, 0x8004); } (void) mv88e1xxx_downshift_set(cphy, 1); if (is_T2(adapter)) { (void) simple_mdio_write(cphy, MV88E1XXX_LED_CONTROL_REGISTER, 0x1); } return cphy; }
static struct cphy *mv88e1xxx_phy_create(adapter_t *adapter, int phy_addr, struct mdio_ops *mdio_ops) { struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL); if (!cphy) return NULL; cphy_init(cphy, adapter, phy_addr, &mv88e1xxx_ops, mdio_ops); /* Configure particular PHY's to run in a different mode. */ if ((board_info(adapter)->caps & SUPPORTED_TP) && board_info(adapter)->chip_phy == CHBT_PHY_88E1111) { /* * Configure the PHY transmitter as class A to reduce EMI. */ (void) simple_mdio_write(cphy, MV88E1XXX_EXTENDED_ADDR_REGISTER, 0xB); (void) simple_mdio_write(cphy, MV88E1XXX_EXTENDED_REGISTER, 0x8004); } (void) mv88e1xxx_downshift_set(cphy, 1); /* Enable downshift */ /* LED */ if (is_T2(adapter)) { (void) simple_mdio_write(cphy, MV88E1XXX_LED_CONTROL_REGISTER, 0x1); } return cphy; }
static int mv88e1xxx_advertise(struct cphy *phy, unsigned int advertise_map) { u32 val = 0; if (advertise_map & (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) { (void) simple_mdio_read(phy, MII_GBCR, &val); val &= ~(GBCR_ADV_1000HALF | GBCR_ADV_1000FULL); if (advertise_map & ADVERTISED_1000baseT_Half) val |= GBCR_ADV_1000HALF; if (advertise_map & ADVERTISED_1000baseT_Full) val |= GBCR_ADV_1000FULL; } (void) simple_mdio_write(phy, MII_GBCR, val); val = 1; if (advertise_map & ADVERTISED_10baseT_Half) val |= ADVERTISE_10HALF; if (advertise_map & ADVERTISED_10baseT_Full) val |= ADVERTISE_10FULL; if (advertise_map & ADVERTISED_100baseT_Half) val |= ADVERTISE_100HALF; if (advertise_map & ADVERTISED_100baseT_Full) val |= ADVERTISE_100FULL; if (advertise_map & ADVERTISED_PAUSE) val |= ADVERTISE_PAUSE; if (advertise_map & ADVERTISED_ASYM_PAUSE) val |= ADVERTISE_PAUSE_ASYM; (void) simple_mdio_write(phy, MII_ADVERTISE, val); return 0; }
/* * Clear the bits given by 'bitval' in PHY register 'reg'. */ static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval) { u32 val; (void) simple_mdio_read(cphy, reg, &val); (void) simple_mdio_write(cphy, reg, val & ~bitval); }
static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover) { u32 data32; (void) simple_mdio_read(cphy, MV88E1XXX_SPECIFIC_CNTRL_REGISTER, &data32); data32 &= ~V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE); data32 |= V_PSCR_MDI_XOVER_MODE(crossover); (void) simple_mdio_write(cphy, MV88E1XXX_SPECIFIC_CNTRL_REGISTER, data32); return 0; }
static int mv88e1xxx_autoneg_enable(struct cphy *cphy) { u32 ctl; (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO); (void) simple_mdio_read(cphy, MII_BMCR, &ctl); /* restart autoneg for change to take effect */ ctl |= BMCR_ANENABLE | BMCR_ANRESTART; (void) simple_mdio_write(cphy, MII_BMCR, ctl); return 0; }
static int mv88e1xxx_autoneg_disable(struct cphy *cphy) { u32 ctl; (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_MDI); (void) simple_mdio_read(cphy, MII_BMCR, &ctl); ctl &= ~BMCR_ANENABLE; (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART); return 0; }
static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable) { u32 val; (void) simple_mdio_read(cphy, MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val); val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT)); if (downshift_enable) val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2); (void) simple_mdio_write(cphy, MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val); return 0; }
static int mv88e1xxx_interrupt_disable(struct cphy *cphy) { /* Disable all phy interrupts. */ (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0); /* Disable Marvell interrupts through Elmer0. */ if (t1_is_asic(cphy->adapter)) { u32 elmer; t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); elmer &= ~ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4); t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); } return 0; }
static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable) { u32 val; (void) simple_mdio_read(cphy, MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val); /* * Set the downshift counter to 2 so we try to establish Gb link * twice before downshifting. */ val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT)); if (downshift_enable) val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2); (void) simple_mdio_write(cphy, MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val); return 0; }
static int mv88e1xxx_interrupt_enable(struct cphy *cphy) { (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, INTR_ENABLE_MASK); if (t1_is_asic(cphy->adapter)) { u32 elmer; t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); elmer |= ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) elmer |= ELMER0_GP_BIT2 | ELMER0_GP_BIT3 | ELMER0_GP_BIT4; t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); } return 0; }
static int mv88e1xxx_autoneg_disable(struct cphy *cphy) { u32 ctl; /* * Crossover *must* be set to manual in order to disable auto-neg. * The Alaska FAQs document highlights this point. */ (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_MDI); /* * Must include autoneg reset when disabling auto-neg. This * is described in the Alaska FAQ document. */ (void) simple_mdio_read(cphy, MII_BMCR, &ctl); ctl &= ~BMCR_ANENABLE; (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART); return 0; }
static int mv88e1xxx_interrupt_enable(struct cphy *cphy) { /* Enable PHY interrupts. */ (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, INTR_ENABLE_MASK); /* Enable Marvell interrupts through Elmer0. */ if (t1_is_asic(cphy->adapter)) { u32 elmer; (void) t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer); elmer |= ELMER0_GP_BIT1; if (is_T2(cphy->adapter)) { elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4; } (void) t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer); } return 0; }
/* * Set the PHY speed and duplex. This also disables auto-negotiation, except * for 1Gb/s, where auto-negotiation is mandatory. */ static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex) { u32 ctl; (void) simple_mdio_read(phy, MII_BMCR, &ctl); if (speed >= 0) { ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); if (speed == SPEED_100) ctl |= BMCR_SPEED100; else if (speed == SPEED_1000) ctl |= BMCR_SPEED1000; } if (duplex >= 0) { ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE); if (duplex == DUPLEX_FULL) ctl |= BMCR_FULLDPLX; } if (ctl & BMCR_SPEED1000) /* auto-negotiation required for 1Gb/s */ ctl |= BMCR_ANENABLE; (void) simple_mdio_write(phy, MII_BMCR, ctl); return 0; }