void
pci_alphabook1_pickintr(struct lca_config *lcp)
{
bus_space_tag_t iot = &lcp->lc_iot;
pci_chipset_tag_t pc = &lcp->lc_pc;
pcireg_t sioclass;
int sioII;
/* XXX MAGIC NUMBER */
sioclass = pci_conf_read(pc, pci_make_tag(pc, 0, LCA_SIO_DEVICE, 0),
PCI_CLASS_REG);
sioII = (sioclass & 0xff) >= 3;
if (!sioII)
printf("WARNING: SIO NOT SIO II... NO BETS...\n");
pc->pc_intr_v = lcp;
pc->pc_intr_map = dec_alphabook1_intr_map;
pc->pc_intr_string = dec_alphabook1_intr_string;
pc->pc_intr_line = dec_alphabook1_intr_line;
pc->pc_intr_establish = dec_alphabook1_intr_establish;
pc->pc_intr_disestablish = dec_alphabook1_intr_disestablish;
/* Not supported on AlphaBook. */
pc->pc_pciide_compat_intr_establish = NULL;
#if NSIO
sio_intr_setup(pc, iot);
#else
panic("pci_alphabook1_pickintr: no I/O interrupt handler (no sio)");
#endif
}
void
pci_eb164_pickintr(struct cia_config *ccp)
{
bus_space_tag_t iot = &ccp->cc_iot;
pci_chipset_tag_t pc = &ccp->cc_pc;
char *cp;
int i;
pc->pc_intr_v = ccp;
pc->pc_intr_map = dec_eb164_intr_map;
pc->pc_intr_string = dec_eb164_intr_string;
pc->pc_intr_evcnt = dec_eb164_intr_evcnt;
pc->pc_intr_establish = dec_eb164_intr_establish;
pc->pc_intr_disestablish = dec_eb164_intr_disestablish;
pc->pc_pciide_compat_intr_establish =
dec_eb164_pciide_compat_intr_establish;
eb164_intrgate_iot = iot;
if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0,
&eb164_intrgate_ioh) != 0)
panic("pci_eb164_pickintr: couldn't map interrupt PLD");
for (i = 0; i < EB164_MAX_IRQ; i++)
eb164_intr_disable(i);
#define PCI_EB164_IRQ_STR 8
eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ,
PCI_EB164_IRQ_STR);
for (i = 0; i < EB164_MAX_IRQ; i++) {
/*
* Systems with a Pyxis seem to have problems with
* stray interrupts, so just ignore them. Sigh,
* I hate buggy hardware.
*/
alpha_shared_intr_set_maxstrays(eb164_pci_intr, i,
(ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX);
cp = alpha_shared_intr_string(eb164_pci_intr, i);
snprintf(cp, PCI_EB164_IRQ_STR, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(
eb164_pci_intr, i), EVCNT_TYPE_INTR, NULL,
"eb164", cp);
}
#if NSIO
sio_intr_setup(pc, iot);
eb164_intr_enable(EB164_SIO_IRQ);
#endif
}
void
pci_eb64plus_pickintr(struct apecs_config *acp)
{
bus_space_tag_t iot = &acp->ac_iot;
pci_chipset_tag_t pc = &acp->ac_pc;
char *cp;
int i;
pc->pc_intr_v = acp;
pc->pc_intr_map = dec_eb64plus_intr_map;
pc->pc_intr_string = dec_eb64plus_intr_string;
pc->pc_intr_evcnt = dec_eb64plus_intr_evcnt;
pc->pc_intr_establish = dec_eb64plus_intr_establish;
pc->pc_intr_disestablish = dec_eb64plus_intr_disestablish;
/* Not supported on the EB64+. */
pc->pc_pciide_compat_intr_establish = NULL;
eb64plus_intrgate_iot = iot;
if (bus_space_map(eb64plus_intrgate_iot, 0x804, 3, 0,
&eb64plus_intrgate_ioh) != 0)
panic("pci_eb64plus_pickintr: couldn't map interrupt PLD");
for (i = 0; i < EB64PLUS_MAX_IRQ; i++)
eb64plus_intr_disable(i);
#define PCI_EB64PLUS_IRQ_STR 8
eb64plus_pci_intr = alpha_shared_intr_alloc(EB64PLUS_MAX_IRQ,
PCI_EB64PLUS_IRQ_STR);
for (i = 0; i < EB64PLUS_MAX_IRQ; i++) {
alpha_shared_intr_set_maxstrays(eb64plus_pci_intr, i,
PCI_STRAY_MAX);
cp = alpha_shared_intr_string(eb64plus_pci_intr, i);
snprintf(cp, PCI_EB64PLUS_IRQ_STR, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(
eb64plus_pci_intr, i), EVCNT_TYPE_INTR, NULL,
"eb64+", cp);
}
#if NSIO
sio_intr_setup(pc, iot);
#endif
}
void
pci_550_pickintr(struct cia_config *ccp)
{
bus_space_tag_t iot = &ccp->cc_iot;
pci_chipset_tag_t pc = &ccp->cc_pc;
char *cp;
int i;
pc->pc_intr_v = ccp;
pc->pc_intr_map = dec_550_intr_map;
pc->pc_intr_string = dec_550_intr_string;
pc->pc_intr_evcnt = dec_550_intr_evcnt;
pc->pc_intr_establish = dec_550_intr_establish;
pc->pc_intr_disestablish = dec_550_intr_disestablish;
pc->pc_pciide_compat_intr_establish =
dec_550_pciide_compat_intr_establish;
/*
* DEC 550's interrupts are enabled via the Pyxis interrupt
* mask register. Nothing to map.
*/
for (i = 0; i < DEC_550_MAX_IRQ; i++)
dec_550_intr_disable(i);
dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ, 8);
for (i = 0; i < DEC_550_MAX_IRQ; i++) {
alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i,
PCI_STRAY_MAX);
alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp);
cp = alpha_shared_intr_string(dec_550_pci_intr, i);
sprintf(cp, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(
dec_550_pci_intr, i), EVCNT_TYPE_INTR, NULL,
"dec_550", cp);
}
#if NSIO
sio_intr_setup(pc, iot);
#endif
}
void
pci_1000a_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, pci_chipset_tag_t pc)
{
char *cp;
int i;
mystery_icu_iot = iot;
pc_tag = pc;
if (bus_space_map(iot, 0x54a, 2, 0, mystery_icu_ioh + 0)
|| bus_space_map(iot, 0x54c, 2, 0, mystery_icu_ioh + 1))
panic("pci_1000a_pickintr");
pc->pc_intr_v = core;
pc->pc_intr_map = dec_1000a_intr_map;
pc->pc_intr_string = dec_1000a_intr_string;
pc->pc_intr_evcnt = dec_1000a_intr_evcnt;
pc->pc_intr_establish = dec_1000a_intr_establish;
pc->pc_intr_disestablish = dec_1000a_intr_disestablish;
pc->pc_pciide_compat_intr_establish = NULL;
dec_1000a_pci_intr = alpha_shared_intr_alloc(PCI_NIRQ, 8);
for (i = 0; i < PCI_NIRQ; i++) {
alpha_shared_intr_set_maxstrays(dec_1000a_pci_intr, i,
PCI_STRAY_MAX);
cp = alpha_shared_intr_string(dec_1000a_pci_intr, i);
sprintf(cp, "irq %d", i);
evcnt_attach_dynamic(alpha_shared_intr_evcnt(
dec_1000a_pci_intr, i), EVCNT_TYPE_INTR, NULL,
"dec_1000a", cp);
}
pci_1000a_imi();
#if NSIO > 0 || NPCEB > 0
sio_intr_setup(pc, iot);
#endif
}
void
pci_up1000_pickintr(struct irongate_config *icp)
{
bus_space_tag_t iot = &icp->ic_iot;
pci_chipset_tag_t pc = &icp->ic_pc;
pc->pc_intr_v = icp;
pc->pc_intr_map = api_up1000_intr_map;
pc->pc_intr_string = api_up1000_intr_string;
pc->pc_intr_line = api_up1000_intr_line;
pc->pc_intr_establish = api_up1000_intr_establish;
pc->pc_intr_disestablish = api_up1000_intr_disestablish;
pc->pc_pciide_compat_intr_establish =
api_up1000_pciide_compat_intr_establish;
pc->pc_pciide_compat_intr_disestablish =
api_up1000_pciide_compat_intr_disestablish;
#if NSIO
sio_intr_setup(pc, iot);
#else
panic("pci_up1000_pickintr: no I/O interrupt handler (no sio)");
#endif
}
