static uint32_t
mpc8572_io_read_halfword (void *state, uint32_t offset)
{
PPC_CPU_State* cpu = get_current_cpu();
e500_core_t *current_core = get_current_core();
mpc8572_io_t *io = &mpc8572_io;
//int offset = p - GET_CCSR_BASE (io->ccsr.ccsr);
//printf("DBG:read CCSR,offset=0x%x,pc=0x%x\n", offset, current_core->pc);
if (offset >= 0x919C0 && offset <= 0x919E0) {
switch (offset) {
default:
/*
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
*/
skyeye_exit (-1);
}
}
if (offset >= 0xE0000 && offset <= 0xE0020) {
switch (offset) {
case 0xE0000:
return io->por_conf.porpllsr;
default:
/*
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
*/
skyeye_exit (-1);
}
}
switch (offset) {
case 0x0:
return cpu->ccsr;
case 0x90C80:
return io->sccr;
case 0x8004:
return io->pci_cfg.cfg_data;
case 0x8006:
return io->pci_cfg.cfg_data;
default:
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
return 0;
//skyeye_exit(-1);
}
}
static void per_cpu_step(e500_core_t * running_core){
uint32 real_addr;
e500_core_t *core = running_core;
/* sometimes, core->npc will changed by another core */
if(core->ipi_flag){
core->pc = core->npc;
core->ipi_flag = 0;
}
core->step++;
core->npc = core->pc + 4;
switch( ppc_effective_to_physical(core, core->pc, PPC_MMU_CODE, &real_addr))
{
case PPC_MMU_OK:
break;
/* we had TLB miss and need to jump to its handler */
case PPC_MMU_EXC:
goto exec_npc;
case PPC_MMU_FATAL:
/* TLB miss */
fprintf(stderr, "TLB missed at 0x%x\n", core->pc);
skyeye_exit(-1);
default:
/* TLB miss */
fprintf(stderr, "Something wrong during address translation at 0x%x\n", core->pc);
skyeye_exit(-1);
};
uint32 instr;
if(bus_read(32, real_addr, &instr) != 0){
/* some error handler */
}
//core->current_opc = ppc_word_from_BE(instr);
core->current_opc = instr;
ppc_exec_opc(core);
//debug_log(core);
exec_npc:
if(!ppc_divisor){
core->dec_io_do_cycle(core);
ppc_divisor = 0;
}
else
ppc_divisor--;
//core->pc = core->npc;
core->pc = gCPU.core[core->pir].npc;
core->pc = core->npc;
}
void mips_dyncom_run(cpu_t *cpu)
{
mips_core_t *core = (mips_core_t*)cpu->cpu_data;
addr_t phys_pc = core->pc;
int rc = cpu_run(cpu);
switch (rc) {
case JIT_RETURN_NOERR:
break;
case JIT_RETURN_SINGLESTEP:
case JIT_RETURN_FUNCNOTFOUND:
cpu_tag(cpu, core->gpr[15]);
cpu->dyncom_engine->cur_tagging_pos ++;
cpu_translate(cpu, core->gpr[15]);
/*
* IF singlestep, we run it here, otherwise, break.
*/
if(cpu->dyncom_engine->flags_debug & CPU_DEBUG_SINGLESTEP)
{
rc = cpu_run(cpu);
if(rc != JIT_RETURN_TRAP)
break;
}
else
break;
case JIT_RETURN_TRAP:
break;
default:
fprintf(stderr, "unknown return code:%d\n", rc);
skyeye_exit(-1);
}
return;
}
int
do_cpu_option (skyeye_option_t * this_option, int num_params,
const char *params[])
{
int ret;
if (skyeye_config.arch == NULL) {
/* If we don't set arch, we use "arm" as default. */
char *default_arch = "arm";
int i;
for (i = 0; i < MAX_SUPP_ARCH; i++) {
if (skyeye_archs[i] == NULL)
continue;
if (!strncmp
(default_arch, skyeye_archs[i]->arch_name,
MAX_PARAM_NAME)) {
skyeye_config.arch = skyeye_archs[i];
SKYEYE_INFO ("arch: %s\n",
skyeye_archs[i]->arch_name);
}
}
if (skyeye_config.arch == NULL) {
SKYEYE_ERR
("ERROR: No arch option found! Maybe you use low version of skyeye?\n");
skyeye_exit (-1);
}
}
ret = skyeye_config.arch->parse_cpu (params);
if (ret < 0)
SKYEYE_ERR ("Error: Unkonw cpu name \"%s\"\n", params[0]);
return ret;
}
static bool arm_cpu_init()
{
skyeye_config_t* config = get_current_config();
machine_config_t *mach = config->mach;
ARM_CPU_State* cpu = (ARM_CPU_State*)skyeye_mm_zero(sizeof(ARM_CPU_State));
if(!cpu){
skyeye_log(Critical_log, __FUNCTION__, "Can not allocate the enough memory for cpu.\n");
skyeye_exit(-1);
}
mach->cpu_data = get_conf_obj_by_cast(cpu, "ARM_CPU_State");
cpu->core_num = 1;
if(!cpu->core_num){
skyeye_log(Critical_log, __FUNCTION__, "Can not get the core number or set wrong mach name?\n");
skyeye_exit(-1);
}
else
cpu->core = (arm_core_t*)skyeye_mm(sizeof(arm_core_t) * cpu->core_num);
/* TODO: zero the memory by malloc */
if(!cpu->core){
skyeye_log(Critical_log, __FUNCTION__, "Can not allocate memory for ppc core.\n");
skyeye_exit(-1);
}
else
skyeye_log(Info_log, __FUNCTION__, "Initilization for %d core\n", cpu->core_num);
int i;
for(i = 0; i < cpu->core_num; i++){
arm_core_t* core = &cpu->core[i];
arm_core_init(core, i);
arm_dyncom_init(core);
skyeye_exec_t* exec = create_exec();
//exec->priv_data = get_conf_obj_by_cast(core, "arm_core_t");
exec->priv_data = (conf_object_t*)core;
exec->run = (void (*)(conf_object_t*))per_cpu_step;
exec->stop = (void (*)(conf_object_t*))per_cpu_stop;
add_to_default_cell(exec);
}
cpu->boot_core_id = 0;
return true;
}
int
mmu_init (ARMul_State * state)
{
int ret;
state->mmu.control = 0x70;
state->mmu.translation_table_base = 0xDEADC0DE;
state->mmu.domain_access_control = 0xDEADC0DE;
state->mmu.fault_status = 0;
state->mmu.fault_address = 0;
state->mmu.process_id = 0;
switch (state->cpu->cpu_val & state->cpu->cpu_mask) {
case SA1100:
case SA1110:
fprintf (stderr, "SKYEYE: use sa11xx mmu ops\n");
state->mmu.ops = sa_mmu_ops;
break;
case PXA250:
case PXA270: //xscale
fprintf (stderr, "SKYEYE: use xscale mmu ops\n");
state->mmu.ops = xscale_mmu_ops;
break;
case 0x41807200: //arm720t
case 0x41007700: //arm7tdmi
case 0x41007100: //arm7100
fprintf (stderr, "SKYEYE: use arm7100 mmu ops\n");
state->mmu.ops = arm7100_mmu_ops;
break;
case 0x41009200:
fprintf (stderr, "SKYEYE: use arm920t mmu ops\n");
state->mmu.ops = arm920t_mmu_ops;
break;
case 0x41069260:
fprintf (stderr, "SKYEYE: use arm926ejs mmu ops\n");
state->mmu.ops = arm926ejs_mmu_ops;
break;
/* case 0x560f5810: */
case 0x0007b000:
fprintf (stderr, "SKYEYE: use arm11jzf-s mmu ops\n");
state->mmu.ops = arm1176jzf_s_mmu_ops;
break;
default:
fprintf (stderr,
"SKYEYE: armmmu.c : mmu_init: unknown cpu_val&cpu_mask 0x%x\n",
state->cpu->cpu_val & state->cpu->cpu_mask);
skyeye_exit (-1);
break;
};
ret = state->mmu.ops.init (state);
state->mmu_inited = (ret == 0);
return ret;
}
ARMword
lh79520_io_read_halfword (ARMul_State * state, ARMword addr)
{
//some parts of kernel use it
if (addr >= UART1_PHYS + UARTDR && addr <= UART1_PHYS + UARTICR)
return lh79520_io_read_word (state, addr);
else {
printf ("SKYEYE: %s error %x\n", __func__, addr);
system ("stty sane");
skyeye_exit (-1);
}
}
void
lh79520_io_write_byte (ARMul_State * state, ARMword addr, ARMword data)
{
//some parts of kernel such as printascii use byte operation
if (addr >= UART1_PHYS + UARTDR && addr <= UART1_PHYS + UARTICR)
return lh79520_io_write_word (state, addr, data);
else {
printf ("SKYEYE: %s(%x %x) error\n", __func__, addr, data);
SKYEYE_OUTREGS (stderr);
system ("stty sane");
skyeye_exit (-1);
}
}
static bool ppc_cpu_init()
{
skyeye_config_t* config = get_current_config();
machine_config_t *mach = config->mach;
if(!strcmp(mach->machine_name, "mpc8560")){
gCPU.core_num = 1;
}
else if(!strcmp(mach->machine_name, "mpc8572"))
gCPU.core_num = 2;
else if(!strcmp(mach->machine_name, "mpc8641d"))
gCPU.core_num = 2;
else
gCPU.core_num = 0;
if(!gCPU.core_num){
fprintf(stderr, "ERROR:you need to set numbers of core in mach_init.\n");
skyeye_exit(-1);
}
else
gCPU.core = malloc(sizeof(e500_core_t) * gCPU.core_num);
/* TODO: zero the memory by malloc */
if(!gCPU.core){
fprintf(stderr, "Can not allocate memory for ppc core.\n");
skyeye_exit(-1);
}
else
printf("%d core is initialized.\n", gCPU.core_num);
int i;
for(i = 0; i < gCPU.core_num; i++){
ppc_core_init(&gCPU.core[i], i);
}
current_core = &gCPU.core[0];
/* initialize decoder */
ppc_dec_init();
return true;
}
bool ppc_cpu_init()
{
//memset(¤t_core-> 0, sizeof current_core->;
memset(&gCPU[0], 0, sizeof gCPU[0]);
memset(&gCPU[1], 0, sizeof gCPU[1]);
//current_core->pvr = gConfig->getConfigInt(CPU_KEY_PVR);
current_core->cpm_reg.dpram = (void *)malloc(MPC8560_DPRAM_SIZE);
if(!current_core->cpm_reg.dpram){
printf("malloc failed for dpram\n");
skyeye_exit(-1);
}
else
printf("malloc succ for dpram, dpram=0x%x\n", current_core->cpm_reg.dpram);
current_core->cpm_reg.iram = (void *)malloc(MPC8560_IRAM_SIZE);
if(!current_core->cpm_reg.iram){
printf("malloc failed for iram\n");
skyeye_exit(-1);
}
else
printf("malloc succ for dpram, dpram=0x%x\n", current_core->cpm_reg.iram);
ppc_dec_init();
// initialize srs (mostly for prom)
int i;
for (i=0; i<16; i++) {
current_core->sr[i] = 0x2aa*i;
}
/*sys_create_mutex(&exception_mutex);*/
PPC_CPU_WARN("You are using the generic CPU!\n");
PPC_CPU_WARN("This is much slower than the just-in-time compiler and\n");
PPC_CPU_WARN("should only be used for debugging purposes or if there's\n");
PPC_CPU_WARN("no just-in-time compiler for your platform.\n");
return true;
}
ARMword
lh79520_io_read_byte (ARMul_State * state, ARMword addr)
{
//some parts of kernel such as printascii use byte operation
if (addr >= UART1_PHYS + UARTDR && addr <= UART1_PHYS + UARTICR)
return lh79520_io_read_word (state, addr);
else {
printf ("SKYEYE: %s error\n", __func__);
printf ("SKYEYE: state->pc=%x,state->instr=%x,addr=%x\n",
state->pc, state->instr, addr);
system ("stty sane");
skyeye_exit (-1);
}
}
static void
ppc_init_state ()
{
/* initial phsical memory to DEFAULT_GMEMORY_SIZE */
if(!(boot_rom = malloc(DEFAULT_BOOTROM_SIZE))){
fprintf(stderr, "can not initialize physical memory...\n");
skyeye_exit(-1);
}
/*we set start_addr */
boot_rom_start_addr = 0xFFFFFFFF - DEFAULT_BOOTROM_SIZE + 1;
boot_romSize = DEFAULT_BOOTROM_SIZE;
/* initialize init_ram parameters */
if(!(init_ram = malloc(INIT_RAM_SIZE))){
fprintf(stderr, "malloc failed!\n");
skyeye_exit(-1);
}
init_ram_size = INIT_RAM_SIZE;
init_ram_start_addr = 0xe4010000;
memset(&gCPU, 0, sizeof gCPU);
//skyeye_config.mach->mach_init(&gCPU, skyeye_config.mach);
ppc_cpu_init();
/* write something to a file for debug or profiling */
if (!prof_file) {
prof_file = fopen ("./kernel_prof_131.txt", "w");
}
/* initialize the alignment and endianess for powerpc */
generic_arch_t* arch_instance = get_arch_instance(NULL);
arch_instance->alignment = UnAlign;
arch_instance->endianess = Big_endian;
/* Before boot linux, we need to do some preparation */
//ppc_boot();
}
void arm_dyncom_run(cpu_t* cpu){
arm_core_t* core = (arm_core_t*)cpu->cpu_data;
addr_t phys_pc = core->Reg[15];
#if 0
if(mmu_read_(core, core->pc, PPC_MMU_CODE, &phys_pc) != PPC_MMU_OK){
/* we donot allow mmu exception in tagging state */
fprintf(stderr, "In %s, can not translate the pc 0x%x\n", __FUNCTION__, core->pc);
exit(-1);
}
#endif
#if 0
cpu->dyncom_engine->code_start = phys_pc;
cpu->dyncom_engine->code_end = get_end_of_page(phys_pc);
cpu->dyncom_engine->code_entry = phys_pc;
#endif
int rc = cpu_run(cpu);
switch (rc) {
case JIT_RETURN_NOERR: /* JIT code wants us to end execution */
break;
case JIT_RETURN_SINGLESTEP:
case JIT_RETURN_FUNCNOTFOUND:
cpu_tag(cpu, core->Reg[15]);
cpu->dyncom_engine->functions = 0;
cpu_translate(cpu);
/*
*If singlestep,we run it here,otherwise,break.
*/
if (cpu->dyncom_engine->flags_debug & CPU_DEBUG_SINGLESTEP){
rc = cpu_run(cpu);
if(rc != JIT_RETURN_TRAP)
break;
}
else
break;
case JIT_RETURN_TRAP:
break;
default:
fprintf(stderr, "unknown return code: %d\n", rc);
skyeye_exit(-1);
}// switch (rc)
return;
}
void
ep7312_io_write_byte (void *state, uint32_t addr, uint32_t data)
{
//fprintf(stderr,"skyeye:ep7312_io_write_byte,@addr is %x",addr);
unsigned char offset = 0;
unsigned char ret;
switch (addr - 0x80000000) {
case PADR:
io.padr = data;
break;
case PBDR:
io.pbdr = data;
break;
case PDDR:
io.pddr = data;
break;
case PADDR:
io.paddr = data;
break;
case PBDDR:
io.pbddr = data;
break;
case PDDDR:
io.pdddr = data;
break;
case PEDR:
data = io.pedr;
break;
case PEDDR:
io.peddr = data;
break;
case INTMR3:
io.intmr3 = data;
break;
case INTMR2:
io.intmr2 = data;
break;
default:
printf ("SKYEYE: ep7312_io_write_byte error@@@@@@@\n");
//SKYEYE_OUTREGS (stderr);
skyeye_exit (-1);
break;
}
}
/*
* === FUNCTION ======================================================================
* Name: trigger
* Description: This function triggers a trap. A trap causes the following to
* occur, if ET = 1:
* - Traps are disabled, ET = 0
* - The existing user supervisor mode is preserved, PS <- S
* - The user/supervisor mode is changed to supervisor, S = 1
* - The register window is advanced to a new window, CWP = (CWP - 1) % NWINDOWS
* - The trapped program counters are saved in local registers 1 and 2 of the
* new window, r[17] = PC, r[18] = NPC
* - The tt field is written to the particular value that identifies the
* exception of interrupt request, except as defined for 'Reset Trap' of 'Error
* Mode'
* - If the trap is 'Reset Trap' control is transfered to 0 address, PC = 0,
* NPC = 4
* - if the trap is not a 'Reset Trap' control is transferred into the trap
* table, PC=TBR, NPC = TBR + 4
*
* If ET = 0 and a precise trap occurs, the processor enters in error_mode
* state and halts execution. If ET = 0 and an interrupt request or an
* interrupting or deferred exception occurs, it is ignored.
* =====================================================================================
*/
static int trigger(void)
{
int et = bit(PSRREG, PSR_ET);
// DBG("%s: TBR 0x%x ET=%d PSR=0x%x\n", __func__, TBRREG, et, PSRREG);
if( et )
{
int S;
// disable traps
clear_bit(PSRREG, PSR_ET);
// supervisor mode is preserved
S = bit(PSRREG, PSR_S);
if( S ) set_bit(PSRREG, PSR_PS); else clear_bit(PSRREG, PSR_PS);
/* put the processor in supervisor mode */
set_bit(PSRREG, PSR_S);
/* adavance the register window */
iu_sub_cwp();
/* save trapped program counters */
REG(L1) = PCREG;
REG(L2) = NPCREG;
PCREG = TBRREG;
NPCREG = TBRREG + 4;
// DBG("%s: TBR 0x%x CWP=0x%x WIM=0x%x\n", __func__, TBRREG, CWP, WIMREG);
}
else
{
/* FIXME: this needs to be specified */
SKYEYE_ERR("Interrupt while ET disabled, processor halt (PC = 0x%x, NPC = 0x%x)\n", PCREG, NPCREG);
skyeye_exit(1);
}
return SPARC_SUCCESS;
}
ARMword
ep7312_io_read_byte (ARMul_State * state, ARMword addr)
{
ARMword data = -1;
unsigned char offset = 0;
unsigned char ret;
switch (addr - 0x80000000) {
case PADR:
data = io.padr;
break;
case PBDR:
data = io.pbdr;
break;
case PDDR:
data = io.pddr;
break;
case PADDR:
data = io.paddr;
break;
case PBDDR:
data = io.pbddr;
break;
case PDDDR:
data = io.pdddr;
break;
case PEDR:
data = io.pedr;
break;
case PEDDR:
data = io.peddr;
break;
default:
printf ("SKYEYE: ep7312_io_read_byte error\n");
printf ("SKYEYE: state->pc=%x,state->instr=%x,addr=%x\n",
state->pc, state->instr, addr);
skyeye_exit (-1);
break;
}
return data;
}
uint32_t
ep7312_io_read_byte (void *state, uint32_t addr)
{
uint32_t data = -1;
unsigned char offset = 0;
unsigned char ret;
switch (addr - 0x80000000) {
case PADR:
data = io.padr;
break;
case PBDR:
data = io.pbdr;
break;
case PDDR:
data = io.pddr;
break;
case PADDR:
data = io.paddr;
break;
case PBDDR:
data = io.pbddr;
break;
case PDDDR:
data = io.pdddr;
break;
case PEDR:
data = io.pedr;
break;
case PEDDR:
data = io.peddr;
break;
default:
printf ("SKYEYE: ep7312_io_read_byte error\n");
printf ("SKYEYE: addr=%x\n", addr);
skyeye_exit (-1);
break;
}
return data;
}
uint32_t
ep7312_io_read_halfword (void *state, uint32_t addr)
{
printf ("SKYEYE: ep7312_io_read_halfword error\n");
skyeye_exit (-1);
}
ARMword
ep7312_io_read_halfword (ARMul_State * state, ARMword addr)
{
printf ("SKYEYE: ep7312_io_read_halfword error\n");
skyeye_exit (-1);
}
static uint32_t
mpc8641d_io_read_word (void *state, uint32_t offset)
{
PPC_CPU_State* cpu = (PPC_CPU_State *)state;
e500_core_t * core = &cpu->core[0];
mpc8641d_io_t *io = &mpc8641d_io;
//printf("DBG:in %s,read CCSR,offset=0x%x,pc=0x%x\n", __FUNCTION__, offset, current_core->pc);
if (offset >= 0x919C0 && offset <= 0x919E0) {
switch (offset) {
default:
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
skyeye_exit (-1);
}
}
if (offset >= 0x2000 && offset <= 0x2E58) {
switch (offset) {
case 0x2E44:
return io->ddr_ctrl.err_disable;
default:
fprintf (stderr,
"in %s, error when read CCSR.offset=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
skyeye_exit (-1);
}
}
/* PIC Global register */
if (offset >= 0x40000 && offset <= 0x7FFF0) {
#if 0
int tmp;
if (offset == 0x41020) {
/* source attribute register for DMA0 */
//printf("In %s,read gcr=0x%x\n", __FUNCTION__, *result);
*result = io->pic_global.gcr & ~0x80000000; /* we clear RST bit after finish initialization of PIC */
//*result = io->pic_global.gcr & ~0x1;
printf ("In %s,read gcr=0x%x, pc=0x%x\n",
__FUNCTION__, *result, current_core->pc);
return r;
}
r = e500_mpic_read_word (offset, &tmp);
*result = tmp;
return r;
#endif
switch (offset) {
case 0x400a0:
return io->pic_global.iack;
case 0x41000:
return io->pic_global.frr; /* according to MPC8572 manual */
case 0x41020:
/* source attribute register for DMA0 */
//printf("In %s,read gcr=0x%x\n", __FUNCTION__, *result);
return io->pic_global.gcr & ~0x80000000; /* we clear RST bit after finish initialization of PIC */
//printf("In %s,read gcr=0x%x, pc=0x%x\n", __FUNCTION__, *result, current_core->pc);
case 0x410a0:
case 0x410b0:
case 0x410c0:
case 0x410d0:
return io->mpic.ipivpr[(offset - 0x410a0) >> 4];
case 0x410e0:
return io->pic_global.svr;
case 0x410f0:
return io->pic_global.tfrr;
case 0x41120:
return io->pic_global.gtvpr0;
case 0x41160:
return io->pic_global.gtvpr1;
case 0x41170:
return io->pic_global.gtdr1;
case 0x411a0:
return io->pic_global.gtvpr2;
case 0x411B0:
return io->pic_global.gtdr2;
case 0x411E0:
return io->pic_global.gtvpr3;
default:
/*
fprintf(stderr,"in %s, error when read global.offset=0x%x, \
pc=0x%x\n",__FUNCTION__, offset, current_core->pc);
return r;
*/
break;
//skyeye_exit(-1);
}
if (offset >= 0x50000 && offset <= 0x50170) {
int index = (offset - 0x50000) >> 4;
if (index & 0x1)
return io->pic_ram.eidr[index >> 1];
else
return io->pic_ram.eivpr[index >> 1];
static uint32_t
mpc8641d_io_read_byte (void *state, uint32_t offset)
{
PPC_CPU_State* cpu = (PPC_CPU_State *)state;
e500_core_t * core = &cpu->core[0];
mpc8641d_io_t *io = &mpc8641d_io;
if (offset >= 0x919C0 && offset <= 0x919E0) {
switch (offset) {
default:
fprintf (stderr,
"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",
__FUNCTION__, offset, core->pc);
skyeye_exit (-1);
}
}
if (offset >= 0xE0000 && offset <= 0xE0020) {
switch (offset) {
case 0xE0000:
return io->por_conf.porpllsr;
default:
fprintf (stderr,
"in %s, error when read CCSR.addr=0x%x,pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
skyeye_exit (-1);
}
}
switch (offset) {
case 0x0:
return cpu->ccsr;
case 0x90C80:
return io->sccr;
case 0x300C:
return io->i2c_reg.i2csr;
case 0x8006:
return io->pci_cfg.cfg_data;
case 0x4500:
if(io->uart[0].lcr & 0x80)
return io->uart[0].dlb;
else{
io->uart[0].lsr &= ~0x01;
return io->uart[0].rbr;
}
case 0x4501:
//printf("In %s,read offset=0x%x,pc=0x%x\n", __FUNCTION__, offset, current_core->pc);
if (io->uart[0].lcr & 0x80)
return io->uart[0].dmb;
else
return io->uart[0].ier;
case 0x4502:
if (io->uart[0].lcr & 0x80)
return io->uart[0].afr;
else {
uint32_t tmp = io->uart[0].iir;
io->uart[0].iir = (io->uart[0].iir & 0xf0) | 0x1;
//printf("In %s,read offset=0x%x,iir=0x%x, pc=0x%x\n", __FUNCTION__, offset, tmp, current_core->pc);
return tmp;
}
case 0x4503:
//printf("In %s,read offset=0x%x\n", __FUNCTION__, offset);
return io->uart[0].lcr;
case 0x4504:
//printf("In %s,read offset=0x%x\n", __FUNCTION__, offset);
return io->uart[0].mcr;
case 0x4505:
return io->uart[0].lsr; /* THRE */
case 0x4506:
return io->uart[0].msr;
case 0x4507:
return io->uart[0].scr;
case 0x4600:
return io->uart[1].rbr;
case 0x4601:
//printf("In %s,read offset=0x%x,pc=0x%x\n", __FUNCTION__, offset, current_core->pc);
if (io->uart[1].lcr & 0x80)
return io->uart[1].dmb;
else
return io->uart[1].ier;
case 0x4602:
if (io->uart[1].lcr & 0x80)
return io->uart[1].afr;
else
return io->uart[1].iir;
case 0x4603:
//printf("In %s,read offset=0x%x\n", __FUNCTION__, offset);
return io->uart[1].lcr;
case 0x4604:
//printf("In %s,read offset=0x%x\n", __FUNCTION__, offset);
return io->uart[1].mcr;
case 0x4607:
return io->uart[1].scr;
default:
fprintf (stderr,
"in %s, error when read CCSR. offset=0x%x, pc=0x%x\n",
__FUNCTION__, offset, current_core->pc);
//skyeye_exit(-1);
}
}
static void
dbct_test_speed_sig(int signo)
{
printf("\n0x%llx %llu\n", dbct_test_speed_state->instr_count, dbct_test_speed_state->instr_count);
skyeye_exit(0);
}
ARMword
cs89712_io_read_halfword (ARMul_State * state, ARMword addr)
{
/*printf("SKYEYE: cs89712_io_read_halfword error\n"); */
skyeye_exit (-1);
}
void nandflash_sb_setup(struct nandflash_device* dev)
{
uint8 flag=0xFF;
int len,start,needinit=0;
struct stat statbuf;
struct nandflash_sb_status *nf;
int i;
nf=(struct nandflash_sb_status *)malloc(sizeof(struct nandflash_sb_status));
if (nf==NULL)
{
printf("error malloc nandflash_sb_status!\n");
skyeye_exit(-1);
}
dev->poweron=nandflash_sb_poweron;
dev->readdata=nandflash_sb_readdata;
dev->readio=nandflash_sb_readio;
dev->readRB=nandflash_sb_readRB;
dev->reset=nandflash_sb_reset;
dev->sendaddr=nandflash_sb_sendaddr;
dev->sendcmd=nandflash_sb_sendcmd;
dev->senddata=nandflash_sb_senddata;
dev->setALE=nandflash_sb_setALE;
dev->setCE=nandflash_sb_setCE;
dev->setCLE=nandflash_sb_setCLE;
dev->setRE=nandflash_sb_setRE;
dev->setWE=nandflash_sb_setWE;
dev->setWP=nandflash_sb_setWP;
memset(nf,0,sizeof(struct nandflash_sb_status));
#ifdef POSIX_SHARE_MEMORY_BROKEN
nf->readbuffer=(uint8*)malloc(dev->pagedumpsize);
#endif
nf->writebuffer=(uint8*)malloc(dev->pagedumpsize);
//nf->memsize=528*32*4096;
if ((nf->fdump= open(dev->dump, FILE_FLAG, S_IRUSR |S_IWUSR )) < 0)
{
free(nf);
printf("error open nandflash dump!\n");
skyeye_exit(-1);
}
if (fstat(nf->fdump, &statbuf) < 0) /* need size of input file */
{
free(nf);
printf("error fstat function\n");
skyeye_exit(-1);
}
if (statbuf.st_size<dev->devicesize)
{
printf("\nInit nandflash dump file.\n");
needinit=1;
start=statbuf.st_size;
len=dev->devicesize-start;
lseek(nf->fdump,dev->devicesize-1,SEEK_SET);
write(nf->fdump,&flag,1);
#ifndef __MINGW32__
fsync(nf->fdump);
#else
_flushall();
#endif
}
#ifndef POSIX_SHARE_MEMORY_BROKEN
if (fstat(nf->fdump, &statbuf) < 0) /* need size of input file */
{
free(nf);
printf("error fstat function\n");
skyeye_exit(-1);
}
printf("file size:%d\n",statbuf.st_size);
if ((nf->addrspace= mmap(0, statbuf.st_size, PROT_READ | PROT_WRITE,
MAP_SHARED, nf->fdump, 0)) == MAP_FAILED)
{
free(nf);
printf("error mmap nandflash file\n");
skyeye_exit(-1);
}
if (needinit)
{
for(i=start;i<dev->devicesize;i++)
{
*(nf->addrspace+i)=flag;
}
if (!msync(nf->addrspace,dev->devicesize,MS_SYNC))
printf("finish init nandflash dump\n");
}
#else
nf->curblock=-1;
if (needinit)
{
memset(nf->readbuffer,0xff,dev->pagedumpsize);
lseek(nf->fdump,start,SEEK_SET);
while((dev->devicesize-start)>=dev->pagesize)
{
write(nf->fdump,nf->readbuffer,dev->pagesize);
start=start+dev->pagesize;
}
for (i=start;i<dev->devicesize;i++)
write(nf->fdump,&flag,1);
}
#endif
dev->priv=nf;
nandflash_sb_poweron(dev);
}
int
do_log_option (skyeye_option_t * this_option, int num_params,
const char *params[])
{
char name[MAX_PARAM_NAME], value[MAX_PARAM_NAME];
int i, fd, logon, memlogon;
unsigned long long start, end, length;
#if 0
/*2004-08-09 chy init skyeye_config.log */
skyeye_config.log.log_fd = 0;
skyeye_config.log.logon = 0;
skyeye_config.log.memlogon = 0;
skyeye_config.log.start = 0;
skyeye_config.log.end = 0;
skyeye_config.log.length = 0;
for (i = 0; i < num_params; i++) {
if (split_param (params[i], name, value) < 0)
SKYEYE_ERR
("log_info: Error: log has wrong parameter \"%s\".\n",
name);
if (!strncmp ("logon", name, strlen (name))) {
sscanf (value, "%d", &logon);
if (logon != 0 && logon != 1)
SKYEYE_ERR
("log_info: Error logon value %d\n",
logon);
if (logon == 1) {
SKYEYE_INFO ("log_info: log is on.\n");
}
else {
SKYEYE_INFO ("log_info: log is off.\n");
}
skyeye_config.log.logon = logon;
}
else if (!strncmp ("memlogon", name, strlen (name))) {
sscanf (value, "%d", &memlogon);
if (memlogon != 0 && memlogon != 1)
SKYEYE_ERR
("log_info: Error logon value %d\n",
memlogon);
if (memlogon == 1) {
SKYEYE_INFO ("log_info: memory klog is on.\n");
}
else {
SKYEYE_INFO ("log_info: memory log is off.\n");
}
skyeye_config.log.memlogon = memlogon;
}
else if (!strncmp ("logfile", name, strlen (name))) {
if ((skyeye_logfd = fopen (value, "w+")) == NULL) {
//SKYEYE_DBG("SkyEye Error when open log file %s\n", value);
perror ("SkyEye: Error when open log file: ");
skyeye_exit (-1);
}
skyeye_config.log.log_fd = skyeye_logfd;
SKYEYE_INFO ("log_info:log file is %s, fd is 0x%x\n",
value, skyeye_logfd);
}
else if (!strncmp ("start", name, strlen (name))) {
start = strtoul (value, NULL, 0);
skyeye_config.log.start = start;
SKYEYE_INFO ("log_info: log start clock %llu\n",
start);
}
else if (!strncmp ("end", name, strlen (name))) {
end = strtoul (value, NULL, 0);
skyeye_config.log.end = end;
SKYEYE_INFO ("log_info: log end clock %llu\n", end);
}
else if (!strncmp ("length", name, strlen (name))) {
sscanf (value, "%llu", &length);
skyeye_config.log.length = length;
SKYEYE_INFO ("log_info: log instr length %llu\n",
length);
}
else
SKYEYE_ERR ("Error: Unknown cpu name \"%s\"\n", params[0]);
}
#endif
return 0;
}
ARMword
ARMul_DoProg (ARMul_State * state)
{
ARMword pc = 0;
/*
* 2007-01-24 removed the term-io functions by Anthony Lee,
* moved to "device/uart/skyeye_uart_stdio.c".
*/
//teawater add DBCT_TEST_SPEED 2005.10.04---------------------------------------
#ifdef DBCT_TEST_SPEED
{
if (!dbct_test_speed_state) {
//init timer
struct itimerval value;
struct sigaction act;
dbct_test_speed_state = state;
state->instr_count = 0;
act.sa_handler = dbct_test_speed_sig;
act.sa_flags = SA_RESTART;
//cygwin don't support ITIMER_VIRTUAL or ITIMER_PROF
#ifndef __CYGWIN__
if (sigaction(SIGVTALRM, &act, NULL) == -1) {
#else
if (sigaction(SIGALRM, &act, NULL) == -1) {
#endif //__CYGWIN__
fprintf(stderr, "init timer error.\n");
exit(-1);
//skyeye_exit(-1);
}
if (skyeye_config.dbct_test_speed_sec) {
value.it_value.tv_sec = skyeye_config.dbct_test_speed_sec;
} else {
value.it_value.tv_sec = DBCT_TEST_SPEED_SEC;
}
printf("dbct_test_speed_sec = %ld\n", value.it_value.tv_sec);
value.it_value.tv_usec = 0;
value.it_interval.tv_sec = 0;
value.it_interval.tv_usec = 0;
#ifndef __CYGWIN__
if (setitimer(ITIMER_VIRTUAL, &value, NULL) == -1) {
#else
if (setitimer(ITIMER_REAL, &value, NULL) == -1) {
#endif //__CYGWIN__
fprintf(stderr, "init timer error.\n");
//skyeye_exit(-1);
}
}
}
#endif //DBCT_TEST_SPEED
//AJ2D--------------------------------------------------------------------------
state->Emulate = RUN;
while (state->Emulate != STOP) {
state->Emulate = RUN;
/*ywc 2005-03-31 */
if (state->prog32Sig && ARMul_MODE32BIT) {
#ifdef DBCT
if (skyeye_config.no_dbct) {
pc = ARMul_Emulate32 (state);
} else {
pc = ARMul_Emulate32_dbct (state);
}
#else
pc = ARMul_Emulate32 (state);
#endif
}
else {
//pc = ARMul_Emulate26 (state);
}
//chy 2006-02-22, should test debugmode first
//chy 2006-04-14, put below codes in ARMul_Emulate
#if 0
if(debugmode)
if(remote_interrupt())
state->Emulate = STOP;
#endif
}
/*
* 2007-01-24 removed the term-io functions by Anthony Lee,
* moved to "device/uart/skyeye_uart_stdio.c".
*/
return (pc);
}
/***************************************************************************\
* Emulate the execution of one instruction. Start the correct emulator *
* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the *
* address of the instruction that is executed. *
\***************************************************************************/
ARMword
ARMul_DoInstr (ARMul_State * state)
{
ARMword pc = 0;
state->Emulate = ONCE;
/*ywc 2005-03-31 */
if (state->prog32Sig && ARMul_MODE32BIT) {
#ifdef DBCT
if (skyeye_config.no_dbct) {
pc = ARMul_Emulate32 (state);
} else {
//teawater add compile switch for DBCT GDB RSP function 2005.10.21--------------
#ifndef DBCT_GDBRSP
printf("DBCT GDBRSP function switch is off.\n");
printf("To use this function, open \"#define DBCT_GDBRSP\" in arch/arm/common/armdefs.h & recompile skyeye.\n");
skyeye_exit(-1);
#endif //DBCT_GDBRSP
//AJ2D--------------------------------------------------------------------------
pc = ARMul_Emulate32_dbct (state);
}
#else
pc = ARMul_Emulate32 (state);
#endif
}
//else
//pc = ARMul_Emulate26 (state);
return (pc);
}
/***************************************************************************\
* This routine causes an Abort to occur, including selecting the correct *
* mode, register bank, and the saving of registers. Call with the *
* appropriate vector's memory address (0,4,8 ....) *
\***************************************************************************/
void
ARMul_Abort (ARMul_State * state, ARMword vector)
{
ARMword temp;
int isize = INSN_SIZE;
int esize = (TFLAG ? 0 : 4);
int e2size = (TFLAG ? -4 : 0);
state->Aborted = FALSE;
if (state->prog32Sig)
if (ARMul_MODE26BIT)
temp = R15PC;
else
temp = state->Reg[15];
else
temp = R15PC | ECC | ER15INT | EMODE;
switch (vector) {
case ARMul_ResetV: /* RESET */
SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE,
0);
break;
case ARMul_UndefinedInstrV: /* Undefined Instruction */
SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE,
isize);
break;
case ARMul_SWIV: /* Software Interrupt */
SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
isize);
break;
case ARMul_PrefetchAbortV: /* Prefetch Abort */
state->AbortAddr = 1;
SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
esize);
break;
case ARMul_DataAbortV: /* Data Abort */
SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,
e2size);
break;
case ARMul_AddrExceptnV: /* Address Exception */
SETABORT (IBIT, SVC26MODE, isize);
break;
case ARMul_IRQV: /* IRQ */
//chy 2003-09-02 the if sentence seems no use
#if 0
if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
|| (temp & ARMul_CP13_R0_IRQ))
#endif
SETABORT (IBIT,
state->prog32Sig ? IRQ32MODE : IRQ26MODE,
esize);
break;
case ARMul_FIQV: /* FIQ */
//chy 2003-09-02 the if sentence seems no use
#if 0
if (!state->is_XScale || !state->CPRead[13] (state, 0, &temp)
|| (temp & ARMul_CP13_R0_FIQ))
#endif
SETABORT (INTBITS,
state->prog32Sig ? FIQ32MODE : FIQ26MODE,
esize);
break;
}
if (ARMul_MODE32BIT) {
/*if (state->mmu.control & CONTROL_VECTOR)
vector += 0xffff0000; //for v4 high exception address*/
if (state->vector_remap_flag)
vector += state->vector_remap_addr; /* support some remap function in LPC processor */
ARMul_SetR15 (state, vector);
} else
ARMul_SetR15 (state, R15CCINTMODE | vector);
}
void
ep7312_io_write_halfword (void *state, uint32_t addr, uint32_t data)
{
printf ("SKYEYE: ep7312_io_write_halfword error\n");
skyeye_exit (-1);
}
bool FASTCALL ppc_exception(e500_core_t *core, uint32 type, uint32 flags, uint32 a)
{
switch(type){
case CRI_INPUT:
case MACH_CHECK:
case DATA_ST:
core->srr[0] = core->pc;
core->srr[1] = core->msr;
/* ESR_DST 0x00800000 Storage Exception - Data miss */
core->esr = 0x00800000;
core->dear = a; /* save the data address accessed by exception instruction */
/* CE,ME,DE is unchanged, other bits should be clear */
core->msr &= 0x21200;
//printf("In %s,Data ST triggered,dear=0x%x,pc=0x%x\n", __FUNCTION__, a, core->pc);
//skyeye_exit(-1);
break;
case INSN_ST:
fprintf(stderr,"Unimplement exception type %d, pc=0x%x.\n", type, core->pc);
skyeye_exit(-1);
case EXT_INT:
//printf("In %s,EXT_INT\n", __FUNCTION__);
core->srr[0] = core->npc;
core->srr[1] = core->msr;
/* CE,ME,DE is unchanged, other bits should be clear */
core->msr &= 0x21200;
break;
case ALIGN:
case PROG:
case FP_UN:
fprintf(stderr,"Unimplement exception type %d, pc=0x%x.\n", type, core->pc);
skyeye_exit(-1);
break;
case SYSCALL:
//printf(" In %s, SYSCALL exp happened,r0=%d, pc=0x%x,\n", __FUNCTION__, core->gpr[0],core->pc);
core->srr[0] = core->npc;
core->srr[1] = core->msr;
/* WE,EE,PR,IS,DS,FP,FE0,FE1 in msr should be cleared */
core->msr &= ~(0x2e930);
break;
case AP_UN:
fprintf(stderr,"Unimplement exception type %d, pc=0x%x.\n", type, core->pc);
skyeye_exit(-1);
case DEC:
core->srr[0] = core->npc;
core->srr[1] = core->msr;
/* CE,ME and DE bit unchanged, other bit should be clear*/
core->msr &= 0x21200;
/* DIS bit is set */
core->tsr |= 0x8000000;
//printf("In %s, timer interrupt happened.\n", __FUNCTION__);
break;
case FIT:
case WD:
fprintf(stderr,"Unimplement exception type %d, pc=0x%x.\n", type, core->pc);
skyeye_exit(-1);
break;
case DATA_TLB:
//printf(" In %s, DATA_TLB exp happened, pc=0x%x,addr=0x%x, pir=0x%x\n", __FUNCTION__, core->pc, a, core->pir);
core->srr[0] = core->pc;
core->srr[1] = core->msr;
//core->esr |= ST;
core->dear = a; /* save the data address accessed by exception instruction */
core->msr &= 0x21200;
/* Update TLB */
/**
* if TLBSELD = 00, MAS0[ESEL] is updated with the next victim information for TLB0.Finially, * the MAS[0] field is updated with the incremented value of TLB0[NV].Thus, ESEL points to
* the current victim
* (the entry to be replaced), while MAS0[NV] points to the next victim to be used if a TLB0 * entry is replaced
*/
/**
* update TLBSEL with TLBSELD
*/
core->mmu.mas[0] = (core->mmu.mas[4] & 0x10000000) | (core->mmu.mas[0] & (~0x10000000));
/* if TLBSELD == 0, update ESEL and NV bit in MAS Register*/
if(!TLBSELD(core->mmu.mas[4])){
/* if TLBSELD == 0, ESEL = TLB[0].NV */
#if 0
/* update ESEL of MAS0 */
static int tlb0_nv = 0;
//offset = ((tlb0_nv & 0x1) << 7) | (EPN(core->mmu.mas[2]) & 0x7f);
core->mmu.tlb0_nv = tlb0_nv;
if(tlb0_nv == 0xF)
tlb0_nv = 0;
tlb0_nv++;
#endif
core->mmu.mas[0] = (core->mmu.tlb0_nv << 18) | (core->mmu.mas[0] & 0xFFF0FFFF) ;
/* update NV of MAS0 , NV = ~TLB[0].NV */
core->mmu.mas[0] = (~core->mmu.tlb0_nv & 0x3) | (core->mmu.mas[0] & 0xFFFFFFFC);
//printf("In %s,core->mmu.mas[0]=0x%x\n", __FUNCTION__, core->mmu.mas[0]);
}
/**
* set zeros of permis and U0 - U3
*/
core->mmu.mas[3] &= 0xFFFFFC00;
/**
* set zeros of RPN
*/
core->mmu.mas[3] &= 0xFFF;
/**
* Set EPN to EPN of access
*/
core->mmu.mas[2] = (a & 0xFFFFF000) | (core->mmu.mas[2] &0xFFF);
/**
* Set TSIZE[0 - 3] to TSIZED
*/
core->mmu.mas[1] = (core->mmu.mas[4] & 0xF00)|(core->mmu.mas[1] & 0xFFFFF0FF);
/**
* Set TID
*/
core->mmu.mas[1] = (core->mmu.mas[1] & 0xFF00FFFF)|((core->mmu.pid[0] & 0xFF) << 16);
/**
* set Valid bit
*/
core->mmu.mas[1] = current_core->mmu.mas[1] | 0x80000000;
/* update SPID with PID */
core->mmu.mas[6] = (core->mmu.mas[6] & 0xFF00FFFF) | ((core->mmu.pid[0] & 0xFF) << 16);
if(flags == PPC_MMU_WRITE)
core->esr = 0x00800000;
else
core->esr = 0x0;
break;
case INSN_TLB:
//printf(" In %s, DATA_TLB exp happened, pc=0x%x,addr=0x%x\n", __FUNCTION__, core->pc, a);
core->srr[0] = core->pc;
core->srr[1] = core->msr;
core->msr &= 0x21200;
/**
* if TLBSELD = 00, MAS0[ESEL] is updated with the next victim information for TLB0.Finially, * the MAS[0] field is updated with the incremented value of TLB0[NV].Thus, ESEL points to
* the current victim
* (the entry to be replaced), while MAS0[NV] points to the next victim to be used if a TLB0 * entry is replaced
*/
/**
* update TLBSEL with TLBSELD
*/
core->mmu.mas[0] = (core->mmu.mas[4] & 0x10000000) | (core->mmu.mas[0] & (~0x10000000));
/* if TLBSELD == 0, update ESEL and NV bit in MAS Register*/
if(!TLBSELD(core->mmu.mas[4])){
/* if TLBSELD == 0, ESEL = TLB[0].NV */
#if 0
/* update ESEL of MAS0 */
static int tlb0_nv = 0;
//offset = ((tlb0_nv & 0x1) << 7) | (EPN(core->mmu.mas[2]) & 0x7f);
core->mmu.tlb0_nv = tlb0_nv;
if(tlb0_nv == 0xF)
tlb0_nv = 0;
tlb0_nv++;
#endif
core->mmu.mas[0] = (core->mmu.tlb0_nv << 18) | (core->mmu.mas[0] & 0xFFF0FFFF) ;
/* update NV of MAS0 , NV = ~TLB[0].NV */
core->mmu.mas[0] = (~core->mmu.tlb0_nv & 0x3) | (core->mmu.mas[0] & 0xFFFFFFFC);
//printf("In %s,core->mmu.mas[0]=0x%x\n", __FUNCTION__, core->mmu.mas[0]);
}
/**
* set zeros of permis and U0 - U3
*/
core->mmu.mas[3] &= 0xFFFFFC00;
/**
* set zeros of RPN
*/
core->mmu.mas[3] &= 0xFFF;
/**
* Set EPN to EPN of access
*/
core->mmu.mas[2] = (a & 0xFFFFF000) | (core->mmu.mas[2] &0xFFF);
/**
* Set TSIZE[0 - 3] to TSIZED
*/
core->mmu.mas[1] = (core->mmu.mas[4] & 0xF00)|(core->mmu.mas[1] & 0xFFFFF0FF);
/**
* Set TID
*/
core->mmu.mas[1] = (core->mmu.mas[1] & 0xFF00FFFF)|((core->mmu.pid[0] & 0xFF) << 16);
/* update SPID with PID */
core->mmu.mas[6] = (core->mmu.mas[6] & 0xFF00FFFF) | ((core->mmu.pid[0] & 0xFF) << 16);
break;
case DEBUG:
default:
fprintf(stderr,"Unknown exception type %d.pc=0x%x\n", type, core->pc);
skyeye_exit(-1);
}
core->npc = (core->ivpr & 0xFFFF0000) | (core->ivor[type] & 0xFFF0);
//printf("In %s,npc=0x%x, &npc=0x%x\n", __FUNCTION__, core->npc, &core->npc);
return true;
}
void
cs89712_io_write_halfword (ARMul_State * state, ARMword addr, ARMword data)
{
printf ("SKYEYE: cs89712_io_write_halfword error\n");
skyeye_exit (-1);
}
exception_t load_file(const char* filename, generic_address_t load_addr){
FILE* f;
uint8 data;
int nread = 0;
generic_address_t addr = load_addr;
f = fopen(filename, "rb");
if(f == NULL){
skyeye_log(Error_log, __FUNCTION__, "Can not open file %s.\n", filename);
return File_open_exp;
}
/* read a char and write it to the memory */
while(nread = fread(&data, 1, 1, f)){
if(bus_write(8, addr, data) != 0){
/* error handler for address error */
fclose(f);
return Excess_range_exp;
}
addr++;
}
skyeye_log(Info_log, __FUNCTION__, "Load the file %s to the memory 0x%x\n", filename, load_addr);
fclose(f);
#if 0
if (mb[bank].filename
&& (f = fopen (mb[bank].filename, "rb"))) {
if (fread
(global_memory.rom[bank], 1, mb[bank].len,
f) <= 0) {
perror ("fread");
fprintf (stderr,
"Failed to load '%s'\n",
mb[bank].filename);
skyeye_exit (-1);
}
fclose (f);
p = (char *) global_memory.rom[bank];
s = 0;
while (s < global_memory.rom_size[bank]) {
generic_arch_t* arch_instance = get_arch_instance(NULL);
if (arch_instance->endianess == Big_endian) /*big enddian? */
swap = ((uint32_t) p[3]) |
(((uint32_t) p[2]) <<
8) | (((uint32_t)
p[1]) << 16) |
(((uint32_t) p[0]) <<
24);
else
swap = ((uint32_t) p[0]) |
(((uint32_t) p[1]) <<
8) | (((uint32_t)
p[2]) << 16) |
(((uint32_t) p[3]) <<
24);
*(uint32_t *) p = swap;
p += 4;
s += 4;
}
/*ywc 2004-03-30 */
//printf("Loaded ROM %s\n", mb[bank].filename);
if (mb[bank].type == MEMTYPE_FLASH) {
printf ("Loaded FLASH %s\n",
mb[bank].filename);
}
else if (mb[bank].type == MEMTYPE_RAM) {
printf ("Loaded RAM %s\n",
mb[bank].filename);
}
else if (mb[bank].type == MEMTYPE_ROM) {
printf ("Loaded ROM %s\n",
mb[bank].filename);
}
}
else if (mb[bank].filename[0] != '\0') {
perror (mb[bank].filename);
fprintf (stderr,
"bank %d, Couldn't open boot ROM %s - execution will "
"commence with the debuger.\n", bank,
mb[bank].filename);
}
#endif
return No_exp;
}
