Beispiel #1
0
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
        unsigned device=(ctrl->channel0[0])>>8;
        smbus_write_byte(SMBUS_HUB, 0x01, device);
        smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
Beispiel #2
0
static void rtd2132_write_reg(struct device *dev, u8 reg, u8 value)
{
	if (RTD2132_DEBUG_REG)
		printk(BIOS_DEBUG, "RTD2132 0x%02x <- 0x%02x\n", reg, value);
	smbus_write_byte(dev, RTD2132_COMMAND, reg);
	smbus_write_byte(dev, RTD2132_DATA, value);
}
Beispiel #3
0
static inline void change_i2c_mux(unsigned device)
{
#define SMBUS_HUB 0x18
        int ret;
        print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
        ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
        print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
        ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
        print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
}
Beispiel #4
0
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
	int ret,i;
	unsigned device=(ctrl->channel0[0])>>8;
	/* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
	i = 2;
	do {
		ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
	} while ((ret != 0) && (i-->0));
	smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
Beispiel #5
0
static inline void change_i2c_mux(unsigned device)
{
	int ret, i;
	printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device);
	i = 2;
	do {
		ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
		printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret);
	} while ((ret != 0) && (i-->0));
	ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
	printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret);
}
Beispiel #6
0
static void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
	int ret,i;
	u8 device = ctrl->spd_switch_addr;

	printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id);

	/* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
	i=2;
	do {
		ret = smbus_write_byte(SMBUS_HUB, 0x01, (1<<(device & 0x7)));
	} while ((ret!=0) && (i-->0));
	smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
Beispiel #7
0
int mainboard_set_fbd_clock(int speed)
{
	switch(speed) {
		case 533:
			smbus_write_byte(0x6f, 0x80, 0x21);
			return 0;
		case 667:
			smbus_write_byte(0x6f, 0x80, 0x23);
			return 0;
		default:
			printk(BIOS_ERR, "Invalid clock: %dMHz\n", speed);
			die("");
			return -1;
	}
}
Beispiel #8
0
static void at24rf08c_init(struct device *dev)
{
	int i, j;

	if (!dev->enabled)
		return;

        /* Ensure that EEPROM/RFID chip is not accessible through RFID.
	   Need to do it only on 5c.  */
	if (dev->path.type != DEVICE_PATH_I2C || dev->path.i2c.device != 0x5c)
		return;

	printk (BIOS_DEBUG, "Locking EEPROM RFID\n");

	for (i = 0; i < 8; i++)
	{
		/* After a register write AT24RF08C sometimes stops responding.
		   Retry several times in case of failure.
		 */
		for (j = 0; j < 100; j++)
			if (smbus_write_byte(dev, i, 0x0f) >= 0)
				break;
	}

	printk (BIOS_DEBUG, "init EEPROM done\n");
}
Beispiel #9
0
void main(unsigned long bist)
{
	if (bist == 0)
		enable_lapic();

	i5000_lpc_config();

	w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);

	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

	early_config();

	setup_gpio();

	enable_smbus();

	/* setup PCIe MMCONF base address */
	pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
			   CONFIG_MMCONF_BASE_ADDRESS >> 16);

        smbus_write_byte(0x6f, 0x00, 0x63);
        smbus_write_byte(0x6f, 0x01, 0x04);
        smbus_write_byte(0x6f, 0x02, 0x53);
        smbus_write_byte(0x6f, 0x03, 0x39);
        smbus_write_byte(0x6f, 0x08, 0x06);
        smbus_write_byte(0x6f, 0x09, 0x00);

	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
	i5000_fbdimm_init();
	smbus_write_byte(0x69, 0x01, 0x01);
}
Beispiel #10
0
void mainboard_romstage_entry(unsigned long bist)
{
	if (bist == 0)
		enable_lapic();

	i5000_lpc_config();

	winbond_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);

	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

	early_config();

	setup_gpio();

	enable_smbus();

        smbus_write_byte(0x6f, 0x00, 0x63);
        smbus_write_byte(0x6f, 0x01, 0x04);
        smbus_write_byte(0x6f, 0x02, 0x53);
        smbus_write_byte(0x6f, 0x03, 0x39);
        smbus_write_byte(0x6f, 0x08, 0x06);
        smbus_write_byte(0x6f, 0x09, 0x00);

	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
	i5000_fbdimm_init();
	smbus_write_byte(0x69, 0x01, 0x01);
}
Beispiel #11
0
void main(unsigned long bist)
{
	if (bist == 0)
		enable_lapic();

	i5000_lpc_config();

	w83627hf_enable_serial(PNP_DEV(0x2e, 2), 0x3f8);

	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

	early_config();

	setup_gpio();

	enable_smbus();

	/* setup PCIe MMCONF base address */
	pci_write_config32(PCI_DEV(0, 16, 0), 0x64,
			   CONFIG_MMCONF_BASE_ADDRESS >> 16);

	outb(0x07, 0x11b8);

	/* These are smbus write captured with serialice. They
	   seem to setup the clock generator */

	smbus_write_byte(0x6f, 0x88, 0x1f);
	smbus_write_byte(0x6f, 0x81, 0xff);
	smbus_write_byte(0x6f, 0x82, 0xff);
	smbus_write_byte(0x6f, 0x80, 0x23);

	outb(0x03, 0x11b8);
	outb(0x01, 0x11b8);

	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, DEFAULT_RCBA | 1);
	i5000_fbdimm_init();
	smbus_write_byte(0x69, 0x01, 0x01);
}
Beispiel #12
0
static void lm63_init(struct device *dev)
{
	int result;
	if (dev->enabled && dev->path.type == DEVICE_PATH_I2C) {
		if (ops_smbus_bus(get_pbus_smbus(dev))) {
			if (dev->bus->dev->path.type == DEVICE_PATH_I2C)
				smbus_set_link(dev);	// it is under mux
			result = smbus_read_byte(dev, 0x03);
//                      result &= ~0x04;
			result |= 0x04;
			smbus_write_byte(dev, 0x03, result & 0xff);	// config lm63
		}
	}
}
Beispiel #13
0
static int w83793_td_level(struct device *dev, int fan, const char *level)
{
	fan *= 0x10;

	smbus_write_byte(dev, 0x30 + fan, level[0]);
	smbus_write_byte(dev, 0x31 + fan, level[1]);
	smbus_write_byte(dev, 0x32 + fan, level[2]);
	smbus_write_byte(dev, 0x33 + fan, level[3]);
	smbus_write_byte(dev, 0x34 + fan, level[4]);
	smbus_write_byte(dev, 0x35 + fan, level[5]);
	smbus_write_byte(dev, 0x36 + fan, level[6]);
	return 0;
}
Beispiel #14
0
static int w83793_tr_level(struct device *dev, int fan, const char *level)
{
	fan *= 0x10;

	smbus_write_byte(dev, 0x70 + fan, level[0]);
	smbus_write_byte(dev, 0x71 + fan, level[1]);
	smbus_write_byte(dev, 0x72 + fan, level[2]);
	smbus_write_byte(dev, 0x73 + fan, level[3]);
	smbus_write_byte(dev, 0x74 + fan, level[4]);
	smbus_write_byte(dev, 0x75 + fan, level[5]);
	smbus_write_byte(dev, 0x76 + fan, level[6]);
	return 0;
}
Beispiel #15
0
static int w83793_td_fan_level(struct device *dev, int fan, const char *level)
{
	fan *= 0x10;

	smbus_write_byte(dev, 0x38 + fan, level[0]);
	smbus_write_byte(dev, 0x39 + fan, level[1]);
	smbus_write_byte(dev, 0x3a + fan, level[2]);
	smbus_write_byte(dev, 0x3b + fan, level[3]);
	smbus_write_byte(dev, 0x3c + fan, level[4]);
	smbus_write_byte(dev, 0x3d + fan, level[5]);
	smbus_write_byte(dev, 0x3e + fan, level[6]);
	return 0;
}
Beispiel #16
0
static int w83793_tr_fan_level(struct device *dev, int fan, const char *level)
{
	fan *= 0x10;

	smbus_write_byte(dev, 0x78 + fan, level[0]);
	smbus_write_byte(dev, 0x79 + fan, level[1]);
	smbus_write_byte(dev, 0x7a + fan, level[2]);
	smbus_write_byte(dev, 0x7b + fan, level[3]);
	smbus_write_byte(dev, 0x7c + fan, level[4]);
	smbus_write_byte(dev, 0x7d + fan, level[5]);
	smbus_write_byte(dev, 0x7e + fan, level[6]);
	return 0;
}
Beispiel #17
0
void mainboard_romstage_entry(unsigned long bist)
{
	if (bist == 0)
		enable_lapic();

	i5000_lpc_config();

	winbond_enable_serial(SERIAL_DEV, 0x3f8);
	console_init();

	/* Halt if there was a built in self test failure */
	report_bist_failure(bist);

	early_config();

	setup_gpio();

	enable_smbus();

	outb(0x07, 0x11b8);

	/* These are smbus write captured with serialice. They
	   seem to setup the clock generator */

	smbus_write_byte(0x6f, 0x88, 0x1f);
	smbus_write_byte(0x6f, 0x81, 0xff);
	smbus_write_byte(0x6f, 0x82, 0xff);
	smbus_write_byte(0x6f, 0x80, 0x23);

	outb(0x03, 0x11b8);
	outb(0x01, 0x11b8);

	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xf0, (uintptr_t)DEFAULT_RCBA | 1);
	i5000_fbdimm_init();
	smbus_write_byte(0x69, 0x01, 0x01);
}
Beispiel #18
0
static void adm1027_enable_monitoring(device_t dev)
{
	int result;

	result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);

	if (!(result & CFG1_RDY)) {
		printk(BIOS_DEBUG, "ADM1027: monitoring not ready\n");
		return;
	}
	result = (result | CFG1_STRT);
	result = smbus_write_byte(dev, ADM1027_REG_CONFIG1, result);

	result = smbus_read_byte(dev, ADM1027_REG_CONFIG1);
	if (!(result & CFG1_STRT)) {
		printk(BIOS_DEBUG, "ADM1027: monitoring would not enable\n");
	}
	printk(BIOS_DEBUG, "ADM1027: monitoring enabled\n");
}
Beispiel #19
0
uint8_t pcal9538a_set_pull_up_down(PCAL9538A *pcal, uint8_t config){
  return smbus_write_byte(pcal->config.i2c, pcal->config.address, PCAL9538A_RA_PUD_DIR, config);
}
Beispiel #20
0
uint8_t pcal9538a_write_outputs(PCAL9538A *pcal, uint8_t config){
  return smbus_write_byte(pcal->config.i2c, pcal->config.address, PCAL9538A_RA_OUTPUT, config);
}
Beispiel #21
0
uint8_t pcal9538a_set_output_type(PCAL9538A *pcal, uint8_t config){
  return smbus_write_byte(pcal->config.i2c, pcal->config.address, PCAL9538A_RA_OUT_TYPE, config);
}
Beispiel #22
0
uint8_t pcal9538a_set_input_inversion(PCAL9538A *pcal, uint8_t config){
  return smbus_write_byte(pcal->config.i2c, pcal->config.address, PCAL9538A_RA_INVERSION, config);
}
Beispiel #23
0
/**
 * Do some S2881-specific HWM initialization for the ADT7463 chip.
 *
 * Should be factored out so that it can be more general.
 *
 * See Analog Devices ADT7463 datasheet, Rev C (2004):
 * http://www.analog.com/en/prod/0,,766_825_ADT7463,00.html
 */
static void adt7463_init(struct device *adt7463)
{
	int result;

	printk(BIOS_DEBUG, "ADT7463 is %s\n", dev_path(adt7463));

	/* Set all fans to 'Fastest Speed Calculated by All 3 Temperature
	 * Channels Controls PWMx'.
	 */
	result = smbus_write_byte(adt7463, 0x5c, 0xc2);
	result = smbus_write_byte(adt7463, 0x5d, 0xc2);
	result = smbus_write_byte(adt7463, 0x5e, 0xc2);

	/* Make sure that our fans never stop when temp. falls below Tmin,
	 * but rather keep going at minimum duty cycle (applies to automatic
	 * fan control mode only).
	 */
	result = smbus_write_byte(adt7463, 0x62, 0xc0);

	/* Set minimum PWM duty cycle to 25%, rather than the default 50%. */
	result = smbus_write_byte(adt7463, 0x64, 0x40);
	result = smbus_write_byte(adt7463, 0x65, 0x40);
	result = smbus_write_byte(adt7463, 0x66, 0x40);

	/* Set Tmin to 55C, rather than the default 90C. Above this temperature
	 * the fans will start blowing harder as temperature increases
	 * (automatic mode only).
	 */
	result = smbus_write_byte(adt7463, 0x67, 0x37);
	result = smbus_write_byte(adt7463, 0x68, 0x37);
	result = smbus_write_byte(adt7463, 0x69, 0x37);

	/* Set THERM limit to 70C, rather than the default 100C.
	 * The fans will kick in at 100% if the sensors reach this temperature,
	 * (only in automatic mode, but supposedly even when hardware is
	 * locked up). This is a failsafe measure.
	 */
	result = smbus_write_byte(adt7463, 0x6a, 0x46);
	result = smbus_write_byte(adt7463, 0x6b, 0x46);
	result = smbus_write_byte(adt7463, 0x6c, 0x46);

	/* Remote temperature 1 offset (LSB == 0.25C). */
	result = smbus_write_byte(adt7463, 0x70, 0x02);

	/* Remote temperature 2 offset (LSB == 0.25C). */
	result = smbus_write_byte(adt7463, 0x72, 0x01);

	/* Set TACH measurements to normal (1/second). */
	result = smbus_write_byte(adt7463, 0x78, 0xf0);

	printk(BIOS_DEBUG, "ADT7463 properly initialized\n");
}
Beispiel #24
0
static void rtd2132_firmware_stop(struct device *dev)
{
	smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_STOP);
	mdelay(60);
}
Beispiel #25
0
static void rtd2132_firmware_start(struct device *dev)
{
	smbus_write_byte(dev, RTD2132_FIRMWARE, RTD2132_FIRMWARE_START);
}
Beispiel #26
0
uint8_t pcal9538a_set_output_dir(PCAL9538A *pcal, uint8_t config){
  return smbus_write_byte(pcal->config.i2c, pcal->config.address, PCAL9538A_RA_CONFIG, config);
}
Beispiel #27
0
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
	static const uint16_t spd_addr[] = {
		// Node 0
		DIMM0, DIMM1, DIMM2, 0,
		0, 0, 0, 0,
		// Node 1
		0, 0, 0, 0,
		0, 0, 0, 0,
	};
	unsigned bsp_apicid = 0;
	int needs_reset = 0;
	struct sys_info *sysinfo = &sysinfo_car;

	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
	console_init();
	enable_rom_decode();

	print_info("now booting... fallback\n");

	/* Is this a CPU only reset? Or is this a secondary CPU? */
	if (!cpu_init_detectedx && boot_cpu()) {
		/* Nothing special needs to be done to find bus 0. */
		/* Allow the HT devices to be found. */
		enumerate_ht_chain();
	}

	print_info("now booting... real_main\n");

	if (bist == 0)
		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);

	/* Halt if there was a built in self test failure. */
	report_bist_failure(bist);

	setup_default_resource_map();
	setup_coherent_ht_domain();
	wait_all_core0_started();

	print_info("now booting... Core0 started\n");

#if CONFIG_LOGICAL_CPUS
	/* It is said that we should start core1 after all core0 launched. */
	start_other_cores();
	wait_all_other_cores_started(bsp_apicid);
#endif
	init_timer();
	ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */

	needs_reset = optimize_link_coherent_ht();
	needs_reset |= optimize_link_incoherent_ht(sysinfo);
	needs_reset |= k8t890_early_setup_ht();

	if (needs_reset) {
		print_debug("ht reset -\n");
		soft_reset();
	}

	/* the HT settings needs to be OK, because link freq change may cause HT disconnect */
	vt8237_sb_enable_fid_vid();
	enable_fid_change();
	init_fidvid_bsp(bsp_apicid);

	/* Stop the APs so we can start them later in init. */
	allow_all_aps_stop(bsp_apicid);

	/* It's the time to set ctrl now. */
	fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);

	enable_smbus();

	/* this seems to be some GPIO on the SMBus--in any case, setting these
	 * two bits reduces the pullup impedance of the bus lines and is required
	 * in order to be able to read SPD info */
	smbus_write_byte(0x48, 0x07, smbus_read_byte(0x48, 0x07) | 0x80);
	smbus_write_byte(0x4a, 0x07, smbus_read_byte(0x4a, 0x07) | 0x10);

	unsigned char mask;

	mask = 0;
//	mask |= 1 /* AGP voltage 1.7 V (not verified, just vendor BIOS value) */
//	mask |= 2 /* V-Link voltage 2.6 V (not verified either) */
	smbus_write_byte(0x4a, 0x00, (smbus_read_byte(0x4a, 0x00) & ~0x0f) | (0x0f ^ (mask << 2)));
	smbus_write_byte(0x4a, 0x01, (smbus_read_byte(0x4a, 0x01) & ~0x03) | (0x03 ^ mask));

	mask = 25; /* RAM voltage in decivolts, valid range from 25 to 28 */
	mask = 3 - (mask - 25);
	smbus_write_byte(0x4a, 0x02, 0x4f | (mask << 4));
	smbus_write_byte(0x4a, 0x03, 0x04 | mask);

	sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
	post_cache_as_ram();
}
Beispiel #28
0
uint8_t pcal9538a_set_input_latch(PCAL9538A *pcal, uint8_t config){
  return smbus_write_byte(pcal->config.i2c, pcal->config.address, PCAL9538A_RA_LATCH, config);
}
Beispiel #29
0
uint8_t pcal9538a_set_pull_enabled(PCAL9538A *pcal, uint8_t config){
  return smbus_write_byte(pcal->config.i2c, pcal->config.address, PCAL9538A_RA_PUD_ENABLE, config);
}
Beispiel #30
0
static int w83795_set_bank(struct device *dev, uint8_t bank)
{
	return smbus_write_byte(dev, W83795_REG_BANKSEL, bank);
}