void verstage_mainboard_init(void)
{
soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
/* TPM I2C bus */
i2c_init(2);
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
/* Set up the pads required to load romstage. */
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funits, ARRAY_SIZE(funits));
/* PMIC */
i2c_init(I2CPWR_BUS);
pmic_init(I2CPWR_BUS);
/* TPM */
i2c_init(I2C3_BUS);
/* EC */
i2c_init(I2C2_BUS);
/*
* Set power detect override for GPIO, audio & sdmmc3 rails.
* GPIO rail override is required to put it into 1.8V mode.
*/
pmc_override_pwr_det(PMC_GPIO_RAIL_AO_MASK | PMC_AUDIO_RAIL_AO_MASK |
PMC_SDMMC3_RAIL_AO_MASK, PMC_GPIO_RAIL_AO_DISABLE |
PMC_AUDIO_RAIL_AO_DISABLE |
PMC_SDMMC3_RAIL_AO_DISABLE);
}
static void mainboard_init(device_t dev)
{
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
i2c_init(I2C1_BUS);
setup_audio();
}
void verstage_mainboard_init(void)
{
soc_configure_funits(funits, ARRAY_SIZE(funits));
/* TPM */
i2c_init(I2C3_BUS);
/* EC */
i2c_init(I2C2_BUS);
}
void romstage_mainboard_init(void)
{
/* Bring up controller interfaces for ramstage loading. */
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
/* TPM I2C bus */
i2c_init(2);
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
/* Set up controllers and pads to load romstage. */
soc_configure_funits(funits, ARRAY_SIZE(funits));
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
i2c_init(I2CPWR_BUS);
pmic_init(I2CPWR_BUS);
}
static void mainboard_init(device_t dev)
{
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
setup_ec_spi();
setup_usb();
setup_audio();
i2c_init(I2C1_BUS); /* for max98090 codec */
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
soc_configure_funits(funits, ARRAY_SIZE(funits));
i2c_init(I2CPWR_BUS);
pmic_init(I2CPWR_BUS);
/* Foster has no TPM yet. This is for future TPM. */
i2c_init(I2C3_BUS);
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
/* Set up the pads required to load romstage. */
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funitcfgs, ARRAY_SIZE(funitcfgs));
i2c_init(4);
pmic_init(4);
tegra_spi_init(4);
}
/* Audio init: clocks and enables/resets */
static void setup_audio(void)
{
/* Audio codec (ES755) uses OSC freq (via AUD_MCLK), s/b 38.4MHz */
soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit));
/*
* As per NVIDIA hardware team, we need to take ALL audio devices
* connected to AHUB (AUDIO, APB2APE, I2S, SPDIF, etc.) out of reset
* and clock-enabled, otherwise reading AHUB devices (in our case,
* I2S/APBIF/AUDIO<XBAR>) will hang.
*/
soc_configure_ape();
clock_enable_audio();
}
static void mainboard_init(device_t dev)
{
soc_configure_pads(padcfgs, ARRAY_SIZE(padcfgs));
soc_configure_funits(funits, ARRAY_SIZE(funits));
/* I2C6 bus (audio, etc.) */
soc_configure_i2c6pad();
i2c_init(I2C6_BUS);
setup_audio();
/* if panel needs to bringup */
#if IS_ENABLED(CONFIG_CHROMEOS)
if (!vboot_skip_display_init())
#endif
configure_display_blocks();
powergate_unused_partitions();
}
/* Audio init: clocks and enables/resets */
static void setup_audio(void)
{
/*
* External peripheral 1: audio codec (max98090) uses 12MHz CLK1
* NOTE: We can't use a funits struct/call here because EXTPERIPH1/2/3
* don't have BASE regs or CAR RST/ENA bits. Also, the mux setting for
* EXTPERIPH1/DAP_MCLK1 is rolled into the I2S1 padcfg.
*/
clock_configure_source(extperiph1, CLK_M, 12000);
soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit));
clock_external_output(1); /* For external MAX98090 audio codec. */
/*
* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
* connected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (in our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*/
clock_enable_audio();
}
static void mainboard_init(device_t dev)
{
soc_configure_funits(funits, ARRAY_SIZE(funits));
/* I2C6 bus (audio, etc.) */
soc_configure_i2c6pad();
i2c_init(I2C6_BUS);
setup_audio();
/* Temp hack for P1 board: Enable speaker amp (powerup, etc.) */
enable_ad4567_spkr_amp();
elog_init();
elog_add_boot_reason();
fix_ec_sw_sync();
/* configure panel gpio pads */
soc_configure_pads(lcd_gpio_padcfgs, ARRAY_SIZE(lcd_gpio_padcfgs));
/* if panel needs to bringup */
if (!vboot_skip_display_init())
configure_display_blocks();
}
/* Audio init: clocks and enables/resets */
static void setup_audio(void)
{
/* Audio codec (RT5677) uses 12MHz CLK1/EXTPERIPH1 */
clock_configure_source(extperiph1, PLLP, 12000);
/* Configure AUD_MCLK pad drive strength */
write32((unsigned int *)TEGRA_APB_MISC_GP_BASE + 0xF4,
(0x10 << PINGROUP_DRVUP_SHIFT | 0x10 << PINGROUP_DRVDN_SHIFT));
/* Set up audio peripheral clocks/muxes */
soc_configure_funits(audio_funit, ARRAY_SIZE(audio_funit));
/* Enable CLK1_OUT */
clock_external_output(1);
/*
* As per NVIDIA hardware team, we need to take ALL audio devices
* connected to AHUB (AUDIO, APB2APE, I2S, SPDIF, etc.) out of reset
* and clock-enabled, otherwise reading AHUB devices (in our case,
* I2S/APBIF/AUDIO<XBAR>) will hang.
*/
soc_configure_ape();
clock_enable_audio();
}
