enum ia_css_err
ia_css_pipe_set_irq_mask(struct ia_css_pipe *pipe,
unsigned int or_mask,
unsigned int and_mask)
{
const struct ia_css_fw_info *fw = &sh_css_sp_fw;
unsigned int HIVE_ADDR_host_sp_com = fw->info.sp.host_sp_com;
unsigned int offset;
struct sh_css_event_irq_mask event_irq_mask;
(void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */
sh_css_dtrace(SH_DBG_TRACE, "ia_css_pipe_set_irq_mask("
"or_mask=%x, and_mask=%x)\n",
or_mask, and_mask);
assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES);
/*assert(or_mask <= UINT16_MAX);*/
/*assert(and_mask <= UINT16_MAX);*/
event_irq_mask.or_mask = (uint16_t)or_mask;
event_irq_mask.and_mask = (uint16_t)and_mask;
offset = offsetof(struct host_sp_communication,
host2sp_event_irq_mask[ia_css_pipe_get_pipe_num(pipe)]);
assert(offset % HRT_BUS_BYTES == 0);
sp_dmem_store(SP0_ID,
(unsigned int)sp_address_of(host_sp_com) + offset,
&event_irq_mask, sizeof(event_irq_mask));
return IA_CSS_SUCCESS;
}
enum ia_css_err
ia_css_event_get_irq_mask(const struct ia_css_pipe *pipe,
unsigned int *or_mask,
unsigned int *and_mask)
{
const struct ia_css_fw_info *fw = &sh_css_sp_fw;
unsigned int HIVE_ADDR_host_sp_com = fw->info.sp.host_sp_com;
unsigned int offset;
struct sh_css_event_irq_mask event_irq_mask;
(void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */
sh_css_dtrace(SH_DBG_TRACE, "ia_css_event_get_irq_mask()\n");
assert(pipe);
assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES);
offset = offsetof(struct host_sp_communication,
host2sp_event_irq_mask[ia_css_pipe_get_pipe_num(pipe)]);
assert(offset % HRT_BUS_BYTES == 0);
sp_dmem_load(SP0_ID,
(unsigned int)sp_address_of(host_sp_com) + offset,
&event_irq_mask, sizeof(event_irq_mask));
if (or_mask)
*or_mask = event_irq_mask.or_mask;
if (and_mask)
*and_mask = event_irq_mask.and_mask;
return IA_CSS_SUCCESS;
}
static void
store_sp_per_frame_data(const struct ia_css_fw_info *fw)
{
unsigned int HIVE_ADDR_sp_per_frame_data = 0;
assert(fw != NULL);
switch (fw->type) {
case ia_css_sp_firmware:
HIVE_ADDR_sp_per_frame_data = fw->info.sp.per_frame_data;
break;
#if defined(IS_ISP_2500_SYSTEM)
case ia_css_sp1_firmware:
(void)fw;
break;
#endif
case ia_css_acc_firmware:
HIVE_ADDR_sp_per_frame_data = fw->info.acc.per_frame_data;
break;
case ia_css_isp_firmware:
return;
}
sp_dmem_store(SP0_ID,
(unsigned int)sp_address_of(sp_per_frame_data),
&per_frame_data,
sizeof(per_frame_data));
}
/* Query the state of SP */
ia_css_spctrl_sp_sw_state ia_css_spctrl_get_state(sp_ID_t sp_id)
{
ia_css_spctrl_sp_sw_state state;
unsigned int HIVE_ADDR_sp_sw_state;
if (sp_id >= N_SP_ID)
return IA_CSS_SP_SW_TERMINATED;
HIVE_ADDR_sp_sw_state = spctrl_cofig_info[sp_id].spctrl_state_dmem_addr;
(void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */
state = sp_dmem_load_uint32(sp_id, (unsigned)sp_address_of(sp_sw_state));
return state;
}
/* Query the state of SP1 */
ia_css_spctrl_sp_sw_state ia_css_spctrl_get_state(sp_ID_t sp_id)
{
ia_css_spctrl_sp_sw_state state = 0;
unsigned int HIVE_ADDR_sp_sw_state;
if (sp_id >= N_SP_ID)
return IA_CSS_SP_SW_TERMINATED;
HIVE_ADDR_sp_sw_state = spctrl_cofig_info[sp_id].spctrl_state_dmem_addr;
(void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */
if (sp_id == SP0_ID)
state = sp_dmem_load_uint32(sp_id, (unsigned)sp_address_of(sp_sw_state));
#if defined(HAS_SEC_SP)
else
state = sp_dmem_load_uint32(sp_id, (unsigned)sp1_address_of(sp_sw_state));
#endif /* HAS_SEC_SP */
return state;
}
static void
store_sp_per_frame_data(const struct sh_css_fw_info *fw)
{
unsigned int HIVE_ADDR_sp_per_frame_data = 0;
switch (fw->type) {
case sh_css_sp_firmware:
HIVE_ADDR_sp_per_frame_data = fw->info.sp.per_frame_data;
break;
case sh_css_acc_firmware:
HIVE_ADDR_sp_per_frame_data = fw->info.acc.per_frame_data;
break;
case sh_css_isp_firmware:
return;
}
sp_dmem_store(SP0_ID,
(unsigned int)sp_address_of(sp_per_frame_data),
&per_frame_data,
sizeof(per_frame_data));
}
void
sh_css_sp_start_isp(void)
{
const struct ia_css_fw_info *fw;
unsigned int HIVE_ADDR_sp_sw_state;
fw = &sh_css_sp_fw;
HIVE_ADDR_sp_sw_state = fw->info.sp.sw_state;
if (sp_running)
return;
(void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */
/* no longer here, sp started immediately */
/*sh_css_debug_pipe_graph_dump_epilogue();*/
store_sp_group_data();
store_sp_per_frame_data(fw);
sp_dmem_store_uint32(SP0_ID,
(unsigned int)sp_address_of(sp_sw_state),
(uint32_t)(SP_SW_STATE_NULL));
//init_host2sp_command();
/* Note 1: The sp_start_isp function contains a wait till
* the input network is configured by the SP.
* Note 2: Not all SP binaries supports host2sp_commands.
* In case a binary does support it, the host2sp_command
* will have status cmd_ready after return of the function
* sh_css_hrt_sp_start_isp. There is no race-condition here
* because only after the process_frame command has been
* received, the SP starts configuring the input network.
*/
ia_css_mmu_invalidate_cache();
sh_css_hrt_sp_start_isp();
sp_running = true;
}
bool ia_css_pipeline_has_stopped(struct ia_css_pipeline *pipeline)
{
/* Android compilation files if made an local variable
stack size on android is limited to 2k and this structure
is around 2.5K, in place of static malloc can be done but
if this call is made too often it will lead to fragment memory
versus a fixed allocation */
static struct sh_css_sp_group sp_group;
unsigned int thread_id;
const struct ia_css_fw_info *fw;
unsigned int HIVE_ADDR_sp_group;
fw = &sh_css_sp_fw;
HIVE_ADDR_sp_group = fw->info.sp.group;
ia_css_pipeline_get_sp_thread_id(pipeline->pipe_num, &thread_id);
sp_dmem_load(SP0_ID,
(unsigned int)sp_address_of(sp_group),
&sp_group, sizeof(struct sh_css_sp_group));
return sp_group.pipe[thread_id].num_stages == 0;
}
void
sh_css_event_init_irq_mask(void)
{
int i;
const struct ia_css_fw_info *fw = &sh_css_sp_fw;
unsigned int HIVE_ADDR_host_sp_com = fw->info.sp.host_sp_com;
unsigned int offset;
struct sh_css_event_irq_mask event_irq_mask_init;
event_irq_mask_init.or_mask = IA_CSS_EVENT_TYPE_ALL;
event_irq_mask_init.and_mask = IA_CSS_EVENT_TYPE_NONE;
(void)HIVE_ADDR_host_sp_com; /* Suppress warnings in CRUN */
assert(sizeof(event_irq_mask_init) % HRT_BUS_BYTES == 0);
for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) {
offset = offsetof(struct host_sp_communication,
host2sp_event_irq_mask[i]);
assert(offset % HRT_BUS_BYTES == 0);
sp_dmem_store(SP0_ID,
(unsigned int)sp_address_of(host_sp_com) + offset,
&event_irq_mask_init, sizeof(event_irq_mask_init));
}
}
/* Local function to initialize a buffer queue. This reduces
* the chances of copy-paste errors or typos.
*/
STORAGE_CLASS_INLINE void
init_bufq(unsigned int desc_offset,
unsigned int elems_offset,
ia_css_queue_t *handle)
{
const struct ia_css_fw_info *fw;
unsigned int q_base_addr;
ia_css_queue_remote_t remoteq;
fw = &sh_css_sp_fw;
#ifdef C_RUN
q_base_addr = (unsigned int)sp_address_of(ia_css_bufq_host_sp_queue);
#else
q_base_addr = fw->info.sp.host_sp_queue;
#endif
/* Setup queue location as SP and proc id as SP0_ID */
remoteq.location = IA_CSS_QUEUE_LOC_SP;
remoteq.proc_id = SP0_ID;
remoteq.cb_desc_addr = q_base_addr + desc_offset;
remoteq.cb_elems_addr = q_base_addr + elems_offset;
/* Initialize the queue instance and obtain handle */
ia_css_queue_remote_init(handle, &remoteq);
}
