/**
* Will setup clocks, GPIOs, and regulators to correctly initialize the touch
* sensor to be ready for work.
*
* In the correct order according to the sensor spec this function will
* enable/disable regulators, SPI platform clocks, and reset line, all to set
* the sensor in a correct power on or off state "electrical" wise.
*
* @see spi_prepare_set
* @note This function will not send any commands to the sensor it will only
* control it "electrically".
*/
static int device_prepare(struct fpc1020_data *fpc1020, bool enable)
{
int rc = 0;
int error = 0;
mutex_lock(&fpc1020->lock);
if (enable && !fpc1020->prepared) {
spi_bus_lock(fpc1020->spi->master);
fpc1020->prepared = true;
dev_info(&fpc1020->spi->dev, "%s: power on!!!!\n", __func__);
error = fpc1020_io_regulator_configure(fpc1020);
if (error) {
dev_err(&fpc1020->spi->dev,
"fpc1020_probe - io regulator configuration failed.\n");
}
error = fpc1020_io_regulator_set(fpc1020, true);
if (error) {
dev_err(&fpc1020->spi->dev,
"fpc1020_probe - io regulator enable failed.\n");
}
usleep_range(100, 1000);
rc = spi_set_fabric(fpc1020, true);
if (rc)
goto exit_3;
usleep_range(100, 200);
#if defined(CONFIG_QSEECOM)
rc = set_pipe_ownership(fpc1020, true);
if (rc)
goto exit_5;
#endif
} else if (!enable && fpc1020->prepared) {
#if defined(CONFIG_QSEECOM)
(void)set_pipe_ownership(fpc1020, false);
exit_5:
#endif
(void)spi_set_fabric(fpc1020, false);
exit_3:
(void)select_pin_ctl(fpc1020, "fpc1020_cs_high");
(void)select_pin_ctl(fpc1020, "fpc1020_reset_reset");
usleep_range(100, 1000);
(void)select_pin_ctl(fpc1020, "fpc1020_cs_low");
fpc1020->prepared = false;
spi_bus_unlock(fpc1020->spi->master);
}
mutex_unlock(&fpc1020->lock);
return rc;
}
static ssize_t spi_bus_lock_set(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct fpc1145_data *fpc1145 = dev_get_drvdata(dev);
if (!strncmp(buf, "lock", strlen("lock")))
spi_bus_lock(fpc1145->spi->master);
else if (!strncmp(buf, "unlock", strlen("unlock")))
spi_bus_unlock(fpc1145->spi->master);
else
return -EINVAL;
return count;
}
static inline int bcm_make_transfer(bcm_mpi_t *t, struct spi_message *msg)
{
int ret;
msg->spi = t->dev;
if (t->bus_is_locked) {
ret = bcm63xx_spi_raw_sync_locked(t->dev, &(t->trx_opts), msg);
}
else {
spi_bus_lock(t->dev->master);
ret = bcm63xx_spi_raw_sync_locked(t->dev, &(t->trx_opts), msg);
spi_bus_unlock(t->dev->master);
}
if (!ret) {
ret = msg->status;
}
return (ret);
}
void bcm_mpi_deinit(bcm_mpi_t *t)
{
bcm_pr_debug("%s()\n", __func__);
#ifdef BCMPH_DEBUG_MPI
bcm_mpi_dump_and_reset_trace(t);
#endif
#ifdef BCMPH_USE_SPI_DRIVER
#ifndef BCMPH_NOHW
if (t->bus_is_locked) {
spi_bus_unlock(t->dev->master);
t->bus_is_locked = false;
}
spi_unregister_device(t->dev);
#endif // !BCMPH_NOHW
t->dev = NULL;
#else // !BCMPH_USE_SPI_DRIVER
#ifndef BCMPH_NOHW
if (bcm_mpi_dev_data.ref_count > 0) {
if (1 == bcm_mpi_dev_data.ref_count) {
platform_driver_unregister(&(bcm63xx_spi_driver));
}
else {
bcm_mpi_dev_data.ref_count -= 1;
}
}
else {
bcm_pr_err("Illegal call of %s()\n", __func__);
}
#endif // !BCMPH_NOHW
#endif // !BCMPH_USE_SPI_DRIVER
}
/**
* Will setup clocks, GPIOs, and regulators to correctly initialize the touch
* sensor to be ready for work.
*
* In the correct order according to the sensor spec this function will
* enable/disable regulators, SPI platform clocks, and reset line, all to set
* the sensor in a correct power on or off state "electrical" wise.
*
* @see spi_prepare_set
* @note This function will not send any commands to the sensor it will only
* control it "electrically".
*/
static int device_prepare(struct fpc1145_data *fpc1145, bool enable)
{
int rc;
mutex_lock(&fpc1145->lock);
if (enable && !fpc1145->prepared) {
spi_bus_lock(fpc1145->spi->master);
fpc1145->prepared = true;
select_pin_ctl(fpc1145, "fpc1145_reset_reset");
rc = vreg_setup(fpc1145, "vcc_spi", true);
if (rc)
goto exit;
rc = vreg_setup(fpc1145, "vdd_io", true);
if (rc)
goto exit_1;
rc = vreg_setup(fpc1145, "vdd_ana", true);
if (rc)
goto exit_2;
usleep_range(100, 1000);
rc = spi_set_fabric(fpc1145, true);
if (rc)
goto exit_3;
rc = set_clks(fpc1145, true);
if (rc)
goto exit_4;
(void)select_pin_ctl(fpc1145, "fpc1145_cs_high");
(void)select_pin_ctl(fpc1145, "fpc1145_reset_active");
usleep_range(100, 200);
(void)select_pin_ctl(fpc1145, "fpc1145_cs_active");
rc = set_pipe_ownership(fpc1145, true);
if (rc)
goto exit_5;
} else if (!enable && fpc1145->prepared) {
rc = 0;
(void)set_pipe_ownership(fpc1145, false);
exit_5:
(void)set_clks(fpc1145, false);
exit_4:
(void)spi_set_fabric(fpc1145, false);
exit_3:
(void)select_pin_ctl(fpc1145, "fpc1145_cs_high");
(void)select_pin_ctl(fpc1145, "fpc1145_reset_reset");
usleep_range(FPC1145_VREG_SETUP_US,
FPC1145_VREG_SETUP_US + 100);
(void)select_pin_ctl(fpc1145, "fpc1145_cs_low");
usleep_range(FPC1145_VREG_SETUP_US,
FPC1145_VREG_SETUP_US + 100);
exit_2:
(void)vreg_setup(fpc1145, "vdd_ana", false);
exit_1:
(void)vreg_setup(fpc1145, "vdd_io", false);
exit:
(void)vreg_setup(fpc1145, "vcc_spi", false);
fpc1145->prepared = false;
spi_bus_unlock(fpc1145->spi->master);
} else {
rc = 0;
}
mutex_unlock(&fpc1145->lock);
return rc;
}
/**
* cros_ec_cmd_xfer_spi - Transfer a message over SPI and receive the reply
*
* @ec_dev: ChromeOS EC device
* @ec_msg: Message to transfer
*/
static int cros_ec_cmd_xfer_spi(struct cros_ec_device *ec_dev,
struct cros_ec_command *ec_msg)
{
struct cros_ec_spi *ec_spi = ec_dev->priv;
struct spi_transfer trans;
struct spi_message msg;
int i, len;
u8 *ptr;
u8 *rx_buf;
int sum;
int ret = 0, final_ret;
len = cros_ec_prepare_tx(ec_dev, ec_msg);
dev_dbg(ec_dev->dev, "prepared, len=%d\n", len);
/* If it's too soon to do another transaction, wait */
if (ec_spi->last_transfer_ns) {
unsigned long delay; /* The delay completed so far */
delay = ktime_get_ns() - ec_spi->last_transfer_ns;
if (delay < EC_SPI_RECOVERY_TIME_NS)
ndelay(EC_SPI_RECOVERY_TIME_NS - delay);
}
rx_buf = kzalloc(len, GFP_KERNEL);
if (!rx_buf)
return -ENOMEM;
spi_bus_lock(ec_spi->spi->master);
/* Transmit phase - send our message */
debug_packet(ec_dev->dev, "out", ec_dev->dout, len);
memset(&trans, 0, sizeof(trans));
trans.tx_buf = ec_dev->dout;
trans.rx_buf = rx_buf;
trans.len = len;
trans.cs_change = 1;
spi_message_init(&msg);
spi_message_add_tail(&trans, &msg);
ret = spi_sync_locked(ec_spi->spi, &msg);
/* Get the response */
if (!ret) {
/* Verify that EC can process command */
for (i = 0; i < len; i++) {
switch (rx_buf[i]) {
case EC_SPI_PAST_END:
case EC_SPI_RX_BAD_DATA:
case EC_SPI_NOT_READY:
ret = -EAGAIN;
ec_msg->result = EC_RES_IN_PROGRESS;
default:
break;
}
if (ret)
break;
}
if (!ret)
ret = cros_ec_spi_receive_response(ec_dev,
ec_msg->insize + EC_MSG_TX_PROTO_BYTES);
} else {
dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
}
final_ret = terminate_request(ec_dev);
spi_bus_unlock(ec_spi->spi->master);
if (!ret)
ret = final_ret;
if (ret < 0)
goto exit;
ptr = ec_dev->din;
/* check response error code */
ec_msg->result = ptr[0];
ret = cros_ec_check_result(ec_dev, ec_msg);
if (ret)
goto exit;
len = ptr[1];
sum = ptr[0] + ptr[1];
if (len > ec_msg->insize) {
dev_err(ec_dev->dev, "packet too long (%d bytes, expected %d)",
len, ec_msg->insize);
ret = -ENOSPC;
goto exit;
}
/* copy response packet payload and compute checksum */
for (i = 0; i < len; i++) {
sum += ptr[i + 2];
if (ec_msg->insize)
ec_msg->data[i] = ptr[i + 2];
}
sum &= 0xff;
debug_packet(ec_dev->dev, "in", ptr, len + 3);
if (sum != ptr[len + 2]) {
dev_err(ec_dev->dev,
"bad packet checksum, expected %02x, got %02x\n",
sum, ptr[len + 2]);
ret = -EBADMSG;
goto exit;
}
ret = len;
exit:
kfree(rx_buf);
if (ec_msg->command == EC_CMD_REBOOT_EC)
msleep(EC_REBOOT_DELAY_MS);
return ret;
}
/**
* cros_ec_pkt_xfer_spi - Transfer a packet over SPI and receive the reply
*
* @ec_dev: ChromeOS EC device
* @ec_msg: Message to transfer
*/
static int cros_ec_pkt_xfer_spi(struct cros_ec_device *ec_dev,
struct cros_ec_command *ec_msg)
{
struct ec_host_response *response;
struct cros_ec_spi *ec_spi = ec_dev->priv;
struct spi_transfer trans, trans_delay;
struct spi_message msg;
int i, len;
u8 *ptr;
u8 *rx_buf;
u8 sum;
int ret = 0, final_ret;
len = cros_ec_prepare_tx(ec_dev, ec_msg);
dev_dbg(ec_dev->dev, "prepared, len=%d\n", len);
/* If it's too soon to do another transaction, wait */
if (ec_spi->last_transfer_ns) {
unsigned long delay; /* The delay completed so far */
delay = ktime_get_ns() - ec_spi->last_transfer_ns;
if (delay < EC_SPI_RECOVERY_TIME_NS)
ndelay(EC_SPI_RECOVERY_TIME_NS - delay);
}
rx_buf = kzalloc(len, GFP_KERNEL);
if (!rx_buf)
return -ENOMEM;
spi_bus_lock(ec_spi->spi->master);
/*
* Leave a gap between CS assertion and clocking of data to allow the
* EC time to wakeup.
*/
spi_message_init(&msg);
if (ec_spi->start_of_msg_delay) {
memset(&trans_delay, 0, sizeof(trans_delay));
trans_delay.delay_usecs = ec_spi->start_of_msg_delay;
spi_message_add_tail(&trans_delay, &msg);
}
/* Transmit phase - send our message */
memset(&trans, 0, sizeof(trans));
trans.tx_buf = ec_dev->dout;
trans.rx_buf = rx_buf;
trans.len = len;
trans.cs_change = 1;
spi_message_add_tail(&trans, &msg);
ret = spi_sync_locked(ec_spi->spi, &msg);
/* Get the response */
if (!ret) {
/* Verify that EC can process command */
for (i = 0; i < len; i++) {
switch (rx_buf[i]) {
case EC_SPI_PAST_END:
case EC_SPI_RX_BAD_DATA:
case EC_SPI_NOT_READY:
ret = -EAGAIN;
ec_msg->result = EC_RES_IN_PROGRESS;
default:
break;
}
if (ret)
break;
}
if (!ret)
ret = cros_ec_spi_receive_packet(ec_dev,
ec_msg->insize + sizeof(*response));
} else {
dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
}
final_ret = terminate_request(ec_dev);
spi_bus_unlock(ec_spi->spi->master);
if (!ret)
ret = final_ret;
if (ret < 0)
goto exit;
ptr = ec_dev->din;
/* check response error code */
response = (struct ec_host_response *)ptr;
ec_msg->result = response->result;
ret = cros_ec_check_result(ec_dev, ec_msg);
if (ret)
goto exit;
len = response->data_len;
sum = 0;
if (len > ec_msg->insize) {
dev_err(ec_dev->dev, "packet too long (%d bytes, expected %d)",
len, ec_msg->insize);
ret = -EMSGSIZE;
goto exit;
}
for (i = 0; i < sizeof(*response); i++)
sum += ptr[i];
/* copy response packet payload and compute checksum */
memcpy(ec_msg->data, ptr + sizeof(*response), len);
for (i = 0; i < len; i++)
sum += ec_msg->data[i];
if (sum) {
dev_err(ec_dev->dev,
"bad packet checksum, calculated %x\n",
sum);
ret = -EBADMSG;
goto exit;
}
ret = len;
exit:
kfree(rx_buf);
if (ec_msg->command == EC_CMD_REBOOT_EC)
msleep(EC_REBOOT_DELAY_MS);
return ret;
}
static int device_prepare(struct fpc1020_data *fpc1020, bool enable)
{
int rc;
mutex_lock(&fpc1020->lock);
if (enable && !fpc1020->prepared) {
spi_bus_lock(fpc1020->spi->master);
fpc1020->prepared = true;
/* select_pin_ctl(fpc1020, "fpc1020_reset_reset"); */
/*
rc = vreg_setup(fpc1020, "vcc_spi", true);
if (rc)
goto exit;
rc = vreg_setup(fpc1020, "vdd_io", true);
if (rc)
goto exit_1;
rc = vreg_setup(fpc1020, "vdd_ana", true);
if (rc)
goto exit_2;
*/
usleep_range(100, 1000);
rc = spi_set_fabric(fpc1020, true);
if (rc)
goto exit_3;
rc = set_clks(fpc1020, true);
if (rc)
goto exit_4;
/* (void)select_pin_ctl(fpc1020, "fpc1020_cs_high"); */
/* (void)select_pin_ctl(fpc1020, "fpc1020_reset_active"); */
usleep_range(100, 200);
/* (void)select_pin_ctl(fpc1020, "fpc1020_cs_active"); */
#if defined(SUPPORT_TRUSTZONE)
rc = set_pipe_ownership(fpc1020, true);
if (rc)
goto exit_5;
#endif
} else if (!enable && fpc1020->prepared) {
rc = 0;
#if defined(SUPPORT_TRUSTZONE)
(void)set_pipe_ownership(fpc1020, false);
exit_5:
#endif
(void)set_clks(fpc1020, false);
exit_4:
(void)spi_set_fabric(fpc1020, false);
exit_3:
(void)select_pin_ctl(fpc1020, "fpc1020_cs_high");
(void)select_pin_ctl(fpc1020, "fpc1020_reset_reset");
usleep_range(100, 1000);
/*
(void)vreg_setup(fpc1020, "vdd_ana", false);
exit_2:
(void)vreg_setup(fpc1020, "vdd_io", false);
exit_1:
(void)vreg_setup(fpc1020, "vcc_spi", false);
exit:
*/
(void)select_pin_ctl(fpc1020, "fpc1020_cs_low");
fpc1020->prepared = false;
spi_bus_unlock(fpc1020->spi->master);
} else {
rc = 0;
}
mutex_unlock(&fpc1020->lock);
return rc;
}
static int ice40_fpga_ops_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t count)
{
struct ice40_fpga_priv *priv = mgr->priv;
struct spi_device *dev = priv->dev;
struct spi_message message;
struct spi_transfer assert_cs_then_reset_delay = {
.cs_change = 1,
.delay_usecs = ICE40_SPI_RESET_DELAY
};
struct spi_transfer housekeeping_delay_then_release_cs = {
.delay_usecs = ICE40_SPI_HOUSEKEEPING_DELAY
};
int ret;
if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
dev_err(&dev->dev,
"Partial reconfiguration is not supported\n");
return -ENOTSUPP;
}
/* Lock the bus, assert CRESET_B and SS_B and delay >200ns */
spi_bus_lock(dev->master);
gpiod_set_value(priv->reset, 1);
spi_message_init(&message);
spi_message_add_tail(&assert_cs_then_reset_delay, &message);
ret = spi_sync_locked(dev, &message);
/* Come out of reset */
gpiod_set_value(priv->reset, 0);
/* Abort if the chip-select failed */
if (ret)
goto fail;
/* Check CDONE is de-asserted i.e. the FPGA is reset */
if (gpiod_get_value(priv->cdone)) {
dev_err(&dev->dev, "Device reset failed, CDONE is asserted\n");
ret = -EIO;
goto fail;
}
/* Wait for the housekeeping to complete, and release SS_B */
spi_message_init(&message);
spi_message_add_tail(&housekeeping_delay_then_release_cs, &message);
ret = spi_sync_locked(dev, &message);
fail:
spi_bus_unlock(dev->master);
return ret;
}
static int ice40_fpga_ops_write(struct fpga_manager *mgr,
const char *buf, size_t count)
{
struct ice40_fpga_priv *priv = mgr->priv;
return spi_write(priv->dev, buf, count);
}
static int ice40_fpga_ops_write_complete(struct fpga_manager *mgr,
struct fpga_image_info *info)
{
struct ice40_fpga_priv *priv = mgr->priv;
struct spi_device *dev = priv->dev;
const u8 padding[ICE40_SPI_NUM_ACTIVATION_BYTES] = {0};
/* Check CDONE is asserted */
if (!gpiod_get_value(priv->cdone)) {
dev_err(&dev->dev,
"CDONE was not asserted after firmware transfer\n");
return -EIO;
}
/* Send of zero-padding to activate the firmware */
return spi_write(dev, padding, sizeof(padding));
}
static const struct fpga_manager_ops ice40_fpga_ops = {
.state = ice40_fpga_ops_state,
.write_init = ice40_fpga_ops_write_init,
.write = ice40_fpga_ops_write,
.write_complete = ice40_fpga_ops_write_complete,
};
static int ice40_fpga_probe(struct spi_device *spi)
{
struct device *dev = &spi->dev;
struct ice40_fpga_priv *priv;
struct fpga_manager *mgr;
int ret;
priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->dev = spi;
/* Check board setup data. */
if (spi->max_speed_hz > ICE40_SPI_MAX_SPEED) {
dev_err(dev, "SPI speed is too high, maximum speed is "
__stringify(ICE40_SPI_MAX_SPEED) "\n");
return -EINVAL;
}
if (spi->max_speed_hz < ICE40_SPI_MIN_SPEED) {
dev_err(dev, "SPI speed is too low, minimum speed is "
__stringify(ICE40_SPI_MIN_SPEED) "\n");
return -EINVAL;
}
if (spi->mode & SPI_CPHA) {
dev_err(dev, "Bad SPI mode, CPHA not supported\n");
return -EINVAL;
}
/* Set up the GPIOs */
priv->cdone = devm_gpiod_get(dev, "cdone", GPIOD_IN);
if (IS_ERR(priv->cdone)) {
ret = PTR_ERR(priv->cdone);
dev_err(dev, "Failed to get CDONE GPIO: %d\n", ret);
return ret;
}
priv->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
if (IS_ERR(priv->reset)) {
ret = PTR_ERR(priv->reset);
dev_err(dev, "Failed to get CRESET_B GPIO: %d\n", ret);
return ret;
}
mgr = fpga_mgr_create(dev, "Lattice iCE40 FPGA Manager",
&ice40_fpga_ops, priv);
if (!mgr)
return -ENOMEM;
spi_set_drvdata(spi, mgr);
ret = fpga_mgr_register(mgr);
if (ret)
fpga_mgr_free(mgr);
return ret;
}
static int ice40_fpga_remove(struct spi_device *spi)
{
struct fpga_manager *mgr = spi_get_drvdata(spi);
fpga_mgr_unregister(mgr);
return 0;
}
static const struct of_device_id ice40_fpga_of_match[] = {
{ .compatible = "lattice,ice40-fpga-mgr", },
{},
};