void spi_write_a16byte(unsigned short spi_dat)
{
spi_enable();
//hi_ssp_writedata(spi_data);
ssp_writew(SSP_DR, spi_dat);
printk("spi_data:0x%x\n", spi_dat);
msleep(10);
spi_disable();
}
void spi_chanel_select(int channal)
{
spi_enable();
while(spi_busy());
spi_desable();
if(channal > 0)
YX_GPIO_SC_PERCTRL1(12, 1);
else YX_GPIO_SC_PERCTRL1(12, 0);
}
void spi_init(_Bool isMsb, spi_op_mode_t opMode, spi_mode_t mode,
spi_prescaler_t scaler)
{
spi_set_msb_lsb(isMsb);
spi_set_operation_mode(opMode);
spi_set_prescaler(scaler);
spi_set_mode(mode);
spi_enable();
}
/**
* \brief Initialize SPI as master.
*/
static void spi_master_initialize(void)
{
/* Configure an SPI peripheral. */
uint32_t spi_chip_sel, spi_clk_freq, spi_clk_pol, spi_clk_pha;
spi_enable_clock(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_disable_loopback(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, spi_get_pcs(2)); // This sets the value of PCS within the Mode Register.
spi_set_variable_peripheral_select(SPI_MASTER_BASE); // PCS needs to be set within each transfer (PCS within SPI_TDR).
spi_disable_peripheral_select_decode(SPI_MASTER_BASE); // Each CS is to be connected to a single device.
spi_set_delay_between_chip_select(SPI_MASTER_BASE, SPI_DLYBCS);
/* Set communication parameters for CS0 */
spi_chip_sel = 0;
spi_clk_freq = 100000; // SPI CLK for RTC = 100kHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_16_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED); // CS rises after SPI transfers have completed.
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS1 */
spi_chip_sel = 1;
spi_clk_freq = 2000000; // SPI CLK for RTC = 4MHz.
spi_clk_pol = 0;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS2 */
spi_chip_sel = 2;
spi_clk_freq = 44000000; // SPI CLK for MEM2 = 44MHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Enable SPI Communication */
spi_enable(SPI_MASTER_BASE);
}
void spi_frequency(spi_t *obj, int hz) {
spi_disable(obj);
uint32_t PCLK = SystemCoreClock;
obj->spi->DIV = PCLK/hz - 1;
obj->spi->DLY = 0;
spi_enable(obj);
}
/** Set up the SPI buses.
* Set up the SPI peripheral, SPI clocks, SPI pins, and SPI pins' clocks.
*/
void spi_setup(void)
{
/* Enable SPI1 periperal clock */
RCC_APB2ENR |= RCC_APB2ENR_SPI1EN;
/* Enable SPI2 periperal clock */
RCC_APB1ENR |= RCC_APB1ENR_SPI2EN;
/* Enable GPIO clocks for CS lines */
RCC_AHB1ENR |= RCC_AHB1ENR_IOPAEN | RCC_AHB1ENR_IOPBEN;
/* Setup CS line GPIOs */
/* Deselect FPGA CS */
gpio_set(GPIOA, GPIO4);
/* Deselect configuration flash and front-end CS */
gpio_set(GPIOB, GPIO11 | GPIO12);
/* FPGA CS */
gpio_mode_setup(GPIOA, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO4);
/* Configuration flash CS */
gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO12);
/* Front-end CS */
gpio_mode_setup(GPIOB, GPIO_MODE_OUTPUT, GPIO_PUPD_PULLUP, GPIO11);
/* Setup SPI alternate function */
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO6 | GPIO7);
gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO6 | GPIO7);
gpio_mode_setup(GPIOB, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO13 | GPIO14 |
GPIO15);
gpio_set_af(GPIOB, GPIO_AF5, GPIO13 | GPIO14 | GPIO15);
/* Setup SPI parameters. */
spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_2, 0, 0,
SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
spi_enable_ss_output(SPI1); /* Required, see 25.3.1 section about NSS */
spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_2, 0, 0,
SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
spi_enable_ss_output(SPI2); /* Required, see 25.3.1 section about NSS */
/* Finally enable the SPI. */
spi_enable(SPI1);
spi_enable(SPI2);
chMtxInit(&spi_mutex);
}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
int DSS; // DSS (data select size)
int polarity = (mode & 0x2) ? 1 : 0;
int phase = (mode & 0x1) ? 1 : 0;
uint16_t tmp = 0;
uint16_t mask = 0xf03;
uint16_t wk_spcmd0;
uint8_t splw;
switch (mode) {
case 0:
case 1:
case 2:
case 3:
// Do Nothing
break;
default:
error("SPI format error");
return;
}
switch (bits) {
case 8:
DSS = 0x7;
splw = 0x20;
break;
case 16:
DSS = 0xf;
splw = 0x40;
break;
case 32:
DSS = 0x2;
splw = 0x60;
break;
default:
error("SPI module don't support other than 8/16/32bits");
return;
}
tmp |= phase;
tmp |= (polarity << 1);
tmp |= (DSS << 8);
obj->bits = bits;
spi_disable(obj);
wk_spcmd0 = obj->spi->SPCMD0;
wk_spcmd0 &= ~mask;
wk_spcmd0 |= (mask & tmp);
obj->spi->SPCMD0 = wk_spcmd0;
obj->spi->SPDCR = splw;
if (slave) {
obj->spi->SPCR &=~(1 << 3); // MSTR to 0
} else {
obj->spi->SPCR |= (1 << 3); // MSTR to 1
}
spi_enable(obj);
}
// Initialize Pin and SPI like specified into config file
void nrf24l01_init()
{
// Init SPI pins
ioport_set_pin_dir(CONF_NRF24L01_SS_PIN, IOPORT_DIR_INPUT);
ioport_set_pin_mode(CONF_NRF24L01_SS_PIN, IOPORT_MODE_PULLUP);
ioport_set_pin_dir(CONF_NRF24L01_MOSI_PIN, IOPORT_DIR_OUTPUT);
ioport_set_pin_mode(CONF_NRF24L01_MOSI_PIN, IOPORT_MODE_PULLUP);
ioport_set_pin_high(CONF_NRF24L01_MOSI_PIN);
ioport_set_pin_dir(CONF_NRF24L01_MISO_PIN, IOPORT_DIR_INPUT);
ioport_set_pin_dir(CONF_NRF24L01_SCK_PIN, IOPORT_DIR_OUTPUT);
ioport_set_pin_high(CONF_NRF24L01_SCK_PIN);
// Init nrf24l01 pins
ioport_set_pin_dir(CONF_NRF24L01_CE_PIN, IOPORT_DIR_OUTPUT);
ioport_set_pin_dir(CONF_NRF24L01_CSn_PIN, IOPORT_DIR_OUTPUT);
ioport_set_pin_dir(CONF_NRF24L01_IRQ_PIN, IOPORT_DIR_INPUT);
ioport_set_pin_low(CONF_NRF24L01_CE_PIN);
spi_deselect_device(&CONF_NRF24L01_SPI, &nrf24l01_spi_device_conf);
spi_master_init(&CONF_NRF24L01_SPI);
spi_master_setup_device(&CONF_NRF24L01_SPI, &nrf24l01_spi_device_conf, SPI_MODE_0, CONF_NRF24L01_CLOCK_SPEED, 0);
spi_enable(&CONF_NRF24L01_SPI);
// Wait nrf24l01 power on reset
delay_ms(Tpor);
nrf24l01_power_off();
// Reset registers to default state
nrf24l01_write_register(NRF24L01_CONFIG_REG, NRF24L01_CONFIG_REG_DEF);
nrf24l01_write_register(NRF24L01_STATUS_REG, NRF24L01_STATUS_REG_DEF);
// TODO: reset all registers
// Config parameters sets in CONF_NRF24L01
nrf24l01_set_power_amplifier(CONF_NRF24L01_PA);
nrf24l01_set_data_rate(CONF_NRF24L01_DATA_RATE);
nrf24l01_set_crc(CONF_NRF24L01_CRC);
nrf24l01_set_addr_len(CONF_NRF24L01_ADDR_LEN);
uint8_t nrf24l01_rx_addr[5] = { CONF_NRF24L01_RX_ADDR };
uint8_t nrf24l01_tx_addr[5] = { CONF_NRF24L01_TX_ADDR };
nrf24l01_set_rx_addr(nrf24l01_rx_addr);
nrf24l01_set_tx_addr(nrf24l01_tx_addr);
nrf24l01_write_register(NRF24L01_RF_CH_REG, CONF_NRF24L01_RF_CHANNEL);
nrf24l01_write_register(NRF24L01_RX_PW_P0_REG, CONF_NRF24L01_PAYLOAD);
nrf24l01_write_register(NRF24L01_RX_PW_P1_REG, CONF_NRF24L01_PAYLOAD);
// Power-up (Power Down -> Standby-I)
uint8_t configReg = nrf24l01_read_register(NRF24L01_CONFIG_REG);
nrf24l01_write_register(NRF24L01_CONFIG_REG, configReg | NRF24L01_PWR_UP_BM);
delay_us(Tpd2stby);
}
void spi_frequency(spi_t *obj, int hz)
{
spi_disable(obj);
// rise DIV value if it cannot be divided
obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1;
obj->spi->DLY = 0;
spi_enable(obj);
}
u8 A7105_ReadReg(u8 address)
{
u8 data;
CS_LO();
spi_xfer(SPI2, 0x40 | address);
spi_disable(SPI2);
spi_set_bidirectional_receive_only_mode(SPI2);
spi_enable(SPI2);
int i;
for(i = 0; i < 10; i++)
;
spi_disable(SPI2);
data = spi_read(SPI2);
CS_HI();
spi_set_unidirectional_mode(SPI2);
spi_enable(SPI2);
return data;
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName clk, PinName cs)
{
CMU_ClockEnable(cmuClock_HFPER, true);
spi_preinit(obj, mosi, miso, clk, cs);
CMU_ClockEnable(spi_get_clock_tree(obj), true);
usart_init(obj, 100000, usartDatabits8, true, usartClockMode0);
spi_enable_pins(obj, true, mosi, miso, clk, cs);
spi_enable(obj, true);
}
unsigned char NRF24L01_Read_Buf(unsigned char reg,unsigned char *pBuf,unsigned char len)
{
unsigned char status,u8_ctr;
spi_enable();
status=spi_send(reg);
for(u8_ctr=0;u8_ctr<len;u8_ctr++)pBuf[u8_ctr]=spi_read(0XFF);//????
return status;
spi_disable();
}
/**
* Initiates transmission of all bytes within the specified FIFO via SPI
*/
void spi_transmit_fifo(fifo_t* buffer)
{
// if (spi_still_transmitting_fifo(my_spi))
// return;
spi_buffer = buffer;
interrupt_enable(INTERRUPT_SPI);
spi_interrupt_upon_READY_enable(my_spi);
spi_enable(my_spi);
}
void test_spi_write() {
// Copy of test_spi_write_ready()
spi_enable(SPI0);
spi_select_slave(SPI0, SPI_SELECTOR_0);
TEST_ASSERT_TRUE(spi_tx_ready(SPI0));
spi_write(SPI0, 0b01011010);
TEST_ASSERT_FALSE(spi_tx_ready(SPI0));
delay_ms(1);
TEST_ASSERT_TRUE(spi_tx_ready(SPI0));
}
static void spi_drivers_setup()
{
//SPI1 to extern
gpio_set_spi_clk(GPIO_A, GPIO_PIN_5);
gpio_set_spi_miso(GPIO_A, GPIO_PIN_6);
gpio_set_spi_mosi(GPIO_A, GPIO_PIN_7);
spi_enable(SPI_1, 4000000, SPI_CLOCK_MODE_IDLE_LOW_RISING);
boot_success("External SPI enabled at 4000000\n");
}
void usb_spi_board_disable(struct usb_spi_config const *config)
{
spi_enable(CONFIG_SPI_FLASH_PORT, 0);
/* Disable clocks to SPI2 module */
STM32_RCC_APB1ENR &= ~STM32_RCC_PB1_SPI2;
/* Release SPI GPIOs */
gpio_config_module(MODULE_SPI_FLASH, 0);
}
void acq_start()
{
spi_enable(SPI_C1);
spi_enable_rx_dma(SPI_C1);
dma_enable_transfer_complete_interrupt(DMA1, DMA_CHANNEL2);
dma_enable_half_transfer_interrupt(DMA1, DMA_CHANNEL2);
dma_enable_channel(DMA1, DMA_CHANNEL2);
nvic_enable_irq(NVIC_DMA1_CHANNEL2_IRQ);
}
void test_spi_read_ready() {
delay_ms(1);
spi_enable(SPI0);
spi_select_slave(SPI0, SPI_SELECTOR_0);
spi_read(SPI0);
spi_write(SPI0, 0b00011100);
TEST_ASSERT_FALSE(spi_rx_ready(SPI0));
delay_ms(1);
TEST_ASSERT_TRUE(spi_rx_ready(SPI0));
}
/* *************** HAL API functions **************************************** */
void hal_init( void ) {
int ret = 0;
/* Reset variables used in file. */
hal_system_time = 0;
// hal_reset_flags();
/* Enable GPIOA clock. Enable AFIO clock. */
rcc_peripheral_enable_clock(&RCC_APB2ENR,
RCC_APB2ENR_IOPAEN |
RCC_APB2ENR_IOPBEN |
RCC_APB2ENR_IOPCEN |
RCC_APB2ENR_SPI1EN |
RCC_APB2ENR_AFIOEN );
/* The following pins are output pins. */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,RST); //reset
gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SLP_TR); //sleep
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_PUSHPULL,SEL); //cs
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL,
SCK | MOSI | MISO); //sck mosi miso
spi_disable(RF_SPI);
SPI2_I2SCFGR = 0;
/* Setup SPI parameters. */
spi_init_master(RF_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_16, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
spi_set_unidirectional_mode(RF_SPI);
spi_set_full_duplex_mode(RF_SPI); /* Not receive-only */
spi_enable_software_slave_management(RF_SPI);
spi_set_nss_high(RF_SPI);
spi_enable_ss_output(RF_SPI); /* Required, see NSS, 25.3.1 section. */
/* Finally enable the SPI. */
spi_enable(RF_SPI);
/* Set GPIO4 (in GPIO port C) to 'input float'. */
gpio_set_mode(RF_IRQ_PORT, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, RF_IRQ_PIN);
gpio_clear(RF_IRQ_PORT, RF_IRQ_PIN);
/* Configure the EXTI subsystem. */
exti_select_source(EXTI4, RF_IRQ_PORT);
exti_set_trigger(EXTI4, EXTI_TRIGGER_RISING);
exti_enable_request(EXTI4);
exti_reset_request(EXTI4);
PRINTF("Enabling interrupts\r\n");
/* Enable EXTI0 interrupt. */
nvic_enable_irq(NVIC_EXTI4_IRQ);
nvic_set_priority(NVIC_EXTI4_IRQ,4);
//@@@!? timer_init();
// ret = trx_init();
// if(ret!=0)
// {
// PRINTF("rf231:hal init failed\r\n");
// }else
// {
// PRINTF("rf231:hal init success\r\n");
// }
}
/*
* Reads a uint16 from the MS5611 address `adr`, stores it to `c`.
*/
static void ms5611_read_u16(uint8_t adr, uint16_t* c)
{
/* adr must be 0xA0 to 0xAE */
uint16_t data_received;
spi_enable(MS5611_SPID); // The SPI peripheral is enabled. // CHIBIOS spiSelect(&MS5611_SPID);
spi_send8(MS5611_SPID, adr); // Data is written to the SPI interface after the previous write transfer has finished.
data_received = spi_read(MS5611_SPID); //A PROM read returns a 2 byte result
spi_disable(MS5611_SPID); // spiUnselect(&MS5611_SPID);
*c = data_received;
}
static int command_spirom(int argc, char **argv)
{
uint8_t txmandev[] = {0x90, 0x00, 0x00, 0x00};
uint8_t txjedec[] = {0x9f};
uint8_t txunique[] = {0x4b, 0x00, 0x00, 0x00, 0x00};
uint8_t txsr1[] = {0x05};
uint8_t txsr2[] = {0x35};
spi_enable(CONFIG_SPI_FLASH_PORT, 1);
printrx("Man/Dev ID", txmandev, sizeof(txmandev), 2);
printrx("JEDEC ID", txjedec, sizeof(txjedec), 3);
printrx("Unique ID", txunique, sizeof(txunique), 8);
printrx("Status reg 1", txsr1, sizeof(txsr1), 1);
printrx("Status reg 2", txsr2, sizeof(txsr2), 1);
spi_enable(CONFIG_SPI_FLASH_PORT, 0);
return EC_SUCCESS;
}
void lcd_enable(bool enable)
{
if(lcd_active() == enable)
return;
lcd_set_active(enable);
if(lcd_active())
{
// enable spi
spi_enable(true);
// reset
imx233_lcdif_reset_lcd(true);
imx233_lcdif_reset_lcd(false);
mdelay(1);
imx233_lcdif_reset_lcd(true);
mdelay(1);
// "power" on
lcd_power(true);
// setup registers
lcd_power_seq();
lcd_init_seq();
lcd_display_on_seq();
imx233_dma_reset_channel(APB_LCDIF);
imx233_dma_start_command(APB_LCDIF, &lcdif_dma[0].dma);
}
else
{
// power down
lcd_display_off_seq();
lcd_power(false);
// stop lcdif
BF_CLR(LCDIF_CTRL, DOTCLK_MODE);
/* stmp37xx errata: clearing DOTCLK_MODE won't clear RUN: wait until
* fifo is empty and then clear manually */
while(!BF_RD(LCDIF_STAT, TXFIFO_EMPTY));
BF_CLR(LCDIF_CTRL, RUN);
// disable spi
spi_enable(false);
}
}
/**
* \brief Initialize EDBG SPI communication for SAM
*
*/
enum status_code adp_interface_init(void)
{
sysclk_init();
/* Configure the SPI interface */
spi_master_init(EDBG_SPI_MODULE);
spi_master_setup_device(EDBG_SPI_MODULE, &SPI_DEVICE, SPI_MODE_0,
SPI_BAUDRATE, 0);
spi_enable(EDBG_SPI_MODULE);
return STATUS_OK;
}
void test_spi_transmission_complete() {
delay_ms(1);
spi_enable(SPI0);
spi_select_slave(SPI0, SPI_SELECTOR_0);
spi_write(SPI0, 0b01011010);
spi_write(SPI0, 0b01011011);
TEST_ASSERT_FALSE(SPI0->SPI_SR & (0x1u << 1));
TEST_ASSERT_FALSE(SPI0->SPI_SR & (0x1u << 9));
delay_ms(1);
TEST_ASSERT_TRUE(SPI0->SPI_SR & (0x1u << 1));
TEST_ASSERT_TRUE(SPI0->SPI_SR & (0x1u << 9));
}
extern void init_spi (void) {
sysclk_enable_pba_module(SYSCLK_SPI);
static const gpio_map_t SPI_GPIO_MAP = {
{SPI_SCK_PIN, SPI_SCK_FUNCTION },
{SPI_MISO_PIN, SPI_MISO_FUNCTION},
{SPI_MOSI_PIN, SPI_MOSI_FUNCTION},
{SPI_NPCS0_PIN, SPI_NPCS0_FUNCTION },
{SPI_NPCS1_PIN, SPI_NPCS1_FUNCTION },
};
// Assign GPIO to SPI.
gpio_enable_module(SPI_GPIO_MAP, sizeof(SPI_GPIO_MAP) / sizeof(SPI_GPIO_MAP[0]));
spi_options_t spiOptions = {
.reg = DAC_SPI,
.baudrate = 4000000,
.bits = 8,
.trans_delay = 0,
.spck_delay = 0,
.stay_act = 1,
.spi_mode = 1,
.modfdis = 1
};
// Initialize as master.
spi_initMaster(SPI, &spiOptions);
// Set SPI selection mode: variable_ps, pcs_decode, delay.
spi_selectionMode(SPI, 0, 0, 0);
// Enable SPI module.
spi_enable(SPI);
// spi_setupChipReg( SPI, &spiOptions, FPBA_HZ );
spi_setupChipReg(SPI, &spiOptions, sysclk_get_pba_hz() );
// add ADC chip register
spiOptions.reg = ADC_SPI;
spiOptions.baudrate = 20000000;
spiOptions.bits = 16;
spiOptions.spi_mode = 2;
spiOptions.spck_delay = 0;
spiOptions.trans_delay = 5;
spiOptions.stay_act = 0;
spiOptions.modfdis = 0;
spi_setupChipReg( SPI, &spiOptions, FPBA_HZ );
// spi_enable(SPI);
}
void lcd_enable(bool enable)
{
if(lcd_on == enable)
return;
lcd_on = enable;
if(lcd_on)
{
// enable spi
spi_enable(true);
// reset
imx233_lcdif_reset_lcd(true);
imx233_lcdif_reset_lcd(false);
mdelay(1);
imx233_lcdif_reset_lcd(true);
mdelay(1);
// "power" on
lcd_power(true);
// setup registers
imx233_lcdif_enable_sync_signals(true); // we need frame signals during init
lcd_power_seq();
lcd_init_seq();
lcd_display_on_seq();
imx233_dma_reset_channel(APB_LCDIF);
imx233_dma_start_command(APB_LCDIF, &lcdif_dma[0].dma);
BF_SET(LCDIF_CTRL, DOTCLK_MODE);
BF_SET(LCDIF_CTRL, RUN);
}
else
{
// power down
lcd_display_off_seq();
lcd_power(false);
// stop lcdif
BF_CLR(LCDIF_CTRL, DOTCLK_MODE);
// disable spi
spi_enable(false);
}
}
/*==============================================================================
hal_spiInit()
=============================================================================*/
void * hal_spiInit(void)
{
//! [slave_config]
struct spi_slave_inst_config st_slaveDevConf;
//! [slave_config]
//! [master_config]
struct spi_config st_masterConf;
//! [master_config]
/* Configure and initialize software device instance of peripheral slave */
//! [slave_conf_defaults]
spi_slave_inst_get_config_defaults(&st_slaveDevConf);
//! [slave_conf_defaults]
//! [ss_pin]
st_slaveDevConf.ss_pin = st_ss;
//! [ss_pin]
//! [slave_init]
spi_attach_slave(&st_spi, &st_slaveDevConf);
//! [slave_init]
/* Configure, initialize and enable SERCOM SPI module */
//! [conf_defaults]
spi_get_config_defaults(&st_masterConf);
//! [conf_defaults]
//! [mux_setting]
st_masterConf.mux_setting = SAMD20_SPI0_SERCOM_MUX_SETTING;
//! [mux_setting]
/* Configure pad 0 for data in */
//! [di]
st_masterConf.pinmux_pad0 = SAMD20_SPI0_SERCOM_PMUX0;
//! [di]
/* Configure pad 1 as unused */
//! [ss]
st_masterConf.pinmux_pad1 = PINMUX_UNUSED;
//! [ss]
/* Configure pad 2 for data out */
//! [do]
st_masterConf.pinmux_pad2 = SAMD20_SPI0_SERCOM_PMUX2;
//! [do]
/* Configure pad 3 for SCK */
//! [sck]
st_masterConf.pinmux_pad3 = SAMD20_SPI0_SERCOM_PMUX3;
//! [sck]
//! [init]
spi_init(&st_masterInst, SAMD20_SPI0_SERCOM, &st_masterConf);
//! [init]
//! [enable]
spi_enable(&st_masterInst);
//! [enable]
return ((void *)&st_spi);
} /* hal_spiInit() */
/** Initialization ************************************************************/
static void qt60168_resources_init(U32 fpba_hz)
{
static const gpio_map_t QT60168_SPI_GPIO_MAP =
{
{QT60168_SPI_SCK_PIN, QT60168_SPI_SCK_FUNCTION }, // SPI Clock.
{QT60168_SPI_MISO_PIN, QT60168_SPI_MISO_FUNCTION }, // MISO.
{QT60168_SPI_MOSI_PIN, QT60168_SPI_MOSI_FUNCTION }, // MOSI.
{QT60168_SPI_NPCS0_PIN, QT60168_SPI_NPCS0_FUNCTION} // Chip Select NPCS.
};
// SPI options.
spi_options_t spiOptions =
{
.reg = QT60168_SPI_NCPS,
.baudrate = 1000000, // Defined in conf_qt60168.h.
.bits = 8, // Defined in conf_qt60168.h.
.spck_delay = 0,
.trans_delay = 0,
.stay_act = 0,
.spi_mode = 3,
.modfdis = 1
};
// Assign I/Os to SPI.
gpio_enable_module(QT60168_SPI_GPIO_MAP,
sizeof(QT60168_SPI_GPIO_MAP) / sizeof(QT60168_SPI_GPIO_MAP[0]));
// Initialize as master.
spi_initMaster(QT60168_SPI, &spiOptions);
// Set selection mode: variable_ps, pcs_decode, delay.
spi_selectionMode(QT60168_SPI, 0, 0, 0);
// Enable SPI.
spi_enable(QT60168_SPI);
// Initialize QT60168 with SPI clock Osc0.
spi_setupChipReg(QT60168_SPI, &spiOptions, 2*FOSC0);
}
void controller_init(U32 fcpu_hz, U32 fhsb_hz, U32 fpbb_hz, U32 fpba_hz) {
qt60168_resources_init(fpba_hz);
// Initialize QT60168 component.
qt60168_init(fpba_hz);
// Init timer to get key value.
rtc_init_qt();
// Invalidate the timeout already
cpu_set_timeout(0, &cpu_time_clear_wheel);
}
void system_pre_init(void)
{
/* Enable direct NVIC */
MEC1322_EC_INT_CTRL |= 1;
/* Disable ARM TRACE debug port */
MEC1322_EC_TRACE_EN &= ~1;
/* Deassert nSIO_RESET */
MEC1322_PCR_PWR_RST_CTL &= ~(1 << 0);
spi_enable(CONFIG_SPI_FLASH_PORT, 1);
}
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName clk)
{
// CS is currently not part of the mbed HAL
PinName cs = NC;
CMU_ClockEnable(cmuClock_HFPER, true);
spi_preinit(obj, mosi, miso, clk, cs);
CMU_ClockEnable(spi_get_clock_tree(obj), true);
usart_init(obj, 100000, usartDatabits8, true, usartClockMode0);
spi_enable_pins(obj, true, mosi, miso, clk, cs);
spi_enable(obj, true);
}