/***************************************************************************** * EEPROM_ReadData * * Reads a data buffer from EEPROM, from a given address * *****************************************************************************/ ee_err_t EEPROM_ReadData(uint16_t NoOfBytes, uint32_t Addr, uint8_t *inbuf) { ee_err_t status = ee_ok; // make sure the write process is ready while(EEPROM_GetWriteReady() != ee_ok); // send the PAGE_PROGRAM command status |= EEPROM_SendCmd(EEPROM_CMD_READ_DATA_BYTES, EEPROM_CMD_CNT ); // send the address status |= EEPROM_SendAddress(Addr); if(status != ee_ok) { status = ee_error; } else { gEepromAssertCS_d(); status |= spi_master_transfer(mEepromSpiInstance_c, NULL, inbuf, NoOfBytes); gEepromDeassertCS_d(); } if(status == ee_ok) { return status; } else { return ee_error; } }
ee_err_t EEPROM_ReadStatus(uint8_t* flashStatus) { ee_err_t status = ee_ok; status |= EEPROM_SendCmd( EEPROM_CMD_READ_STATUS, EEPROM_CMD_CNT ); if(status == ee_ok) { if(spi_master_transfer(mEepromSpiInstance_c, NULL, ¤tStatus, sizeof(currentStatus)) != 0) { status |= ee_error; } gEepromDeassertCS_d(); } if(status != ee_ok) { status = ee_error; } else { if ( NULL != flashStatus ) { *flashStatus = currentStatus; } } return status; }
/*------------------------------------------------------------------------------------------------- * @fn MRFI_SPI_WRITE_BYTE * * @brief data * * @param none * * @return none * */ uint8_t SpiWriteByte(uint8_t data) { uint8_t tmp; tmp = data; spi_master_transfer(&tmp, 1); return tmp; }
int erase_spimem(void) { uint16_t dumbuf[2], i; dumbuf[0] = CE; if(INTERNAL_MEMORY_FALLBACK_MODE) { for (i = 0; i < 4096; i++) { spi_mem_buff[i] = 0; // Initialize the memory buffer. } return; } uint32_t timeout = chip_erase_timeout; spi_master_transfer(dumbuf, 1, 2); // Chip-Erase (this operation can take up to 7s for each chip) while((check_if_wip(2) != 0) && timeout--){ } if((check_if_wip(2) != 0) || !timeout) return -1; timeout = chip_erase_timeout; while((check_if_wip(2) != 0) && timeout--){ } if((check_if_wip(2) != 0) || !timeout) return -1; timeout = chip_erase_timeout; while((check_if_wip(2) != 0) && timeout--){ } if((check_if_wip(2) != 0) || !timeout) return -1; return 1; }
void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event) { lock_deep_sleep(); _acquire(); _callback = callback; _irq.callback(&SPI::irq_handler_asynch); spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage); }
void SPI::start_transfer(const Buffer& tx, const Buffer& rx, const event_callback_t& callback, int event) { aquire(); _current_transaction.callback = callback; _current_transaction.tx_buffer = tx; _current_transaction.rx_buffer = rx; _irq.callback(&SPI::irq_handler_asynch); spi_master_transfer(&_spi, tx.buf, tx.length, rx.buf, rx.length, _irq.entry(), event , _usage); }
int main(void) { int status; char buf[256]; uint8_t commandbyte; uint8_t responsebyte; cpu_init(DEFAULT_CPU_FREQ); #ifdef CONSOLE_SERIAL serial_stdio(CONSOLE_PORT); #endif #ifdef CONSOLE_SEMIHOSTING semihosting_stdio(CONSOLE_PORT) #endif #ifdef CONSOLE_USB usb_serial_stdio(NULL); getch(); #endif printf("\033[H\033[2J%s SPI Master Test (" __DATE__ " " __TIME__ ")\n\n", MCUFAMILYNAME); puts(revision); printf("\nCPU Freq:%u Hz Compiler:%s %s %s\n\n", (unsigned int) SystemCoreClock, __COMPILER__, __VERSION__, __ABI__); if ((status = spi_master_init(SPI_PORT, 8, 0, 281250, SPI_MSBFIRST))) { printf("ERROR: spi_master_init() failed at line %d, %s\n", status, strerror(errno)); exit(1); } for (;;) { printf("Enter a value to send: "); gets(buf); commandbyte = atoi(buf); if ((status = spi_master_transfer(SPI_PORT, &commandbyte, 1, &responsebyte, 1))) { printf("ERROR: spi_master_transfer() failed at line %d, %s\n", status, strerror(errno)); exit(1); } printf("Response was %02X\n\n", responsebyte); } }
static int spimem_read_h(uint32_t spi_chip, uint32_t addr, uint8_t* read_buff, uint32_t size) { uint32_t i; uint32_t size2 = size; uint32_t left_over = 0; if (INTERNAL_MEMORY_FALLBACK_MODE) { if (addr > 0x0FFF) return -2; if ((addr + size -1) > 0x0FFF) size2 = 0x0FFF - size; for (i = 0; i < size2; i++) { *(read_buff + i) = spi_mem_buff[addr + i]; } return size2; } if (addr > 0xFFFFF) // Invalid address to write to. return -2; if ((addr + size - 1) > 0xFFFFF) size2 = 0xFFFFF - size; msg_buff[0] = RD; msg_buff[1] = (uint16_t)((addr & 0x000F0000) >> 16); msg_buff[2] = (uint16_t)((addr & 0x0000FF00) >> 8); msg_buff[3] = (uint16_t)(addr & 0x000000FF); for(i = 4; i < 260; i++) { msg_buff[i] = 0; } if(check_if_wip(spi_chip) != 0) // A write is still in effect, FAILURE_RECOVERY. return -4; spi_master_transfer(msg_buff, 260, spi_chip); // Keeps CS low so that read may begin immediately. for(i = 4; i < (size2 + 4); i++) { *(read_buff + (i - 4)) = (uint8_t)msg_buff[i]; } return size2; }
static ee_err_t EEPROM_WritePage(uint32_t NoOfBytes, uint32_t Addr, uint8_t *Outbuf) { ee_err_t status = ee_ok; if (NoOfBytes == 0) { return ee_ok; } // make sure the write process is ready while(EEPROM_GetWriteReady() != ee_ok); /** * write data */ if (NoOfBytes > EEPROM_PAGE_SIZE) { return ee_too_big; } // send the PAGE_PROGRAM command status |= EEPROM_SendCmd(EEPROM_CMD_PROGRAM_PAGE, EEPROM_CMD_CNT ); // send the address status |= EEPROM_SendAddress(Addr); /** * send data */ gEepromAssertCS_d(); if(spi_master_transfer(mEepromSpiInstance_c, Outbuf, NULL, NoOfBytes) != 0) { status = ee_error; } gEepromDeassertCS_d(); if(status == ee_ok) { return status; } else { return ee_error; } }
/** * \brief Start SPI transfer test. */ static void spi_master_go(void) { uint32_t i; /* Configure SPI as master, set up SPI clock. */ spi_master_initialize(); spi_master_transfer(gs_uc_spi_m_tbuffer, COMM_BUFFER_SIZE, gs_uc_spi_m_rbuffer, COMM_BUFFER_SIZE); for (i = 0; i < COMM_BUFFER_SIZE; i++) { if(gs_uc_spi_m_rbuffer[i] !=gs_uc_spi_m_tbuffer[i]) { break; } } if(i == COMM_BUFFER_SIZE) { puts("SPI transfer test success! \r"); } else { puts("SPI transfer test fail! \r"); } }
static ee_err_t EEPROM_SendCmd(const uint8_t cmdToSend, uint8_t endFlag) { ee_err_t status = ee_ok; uint8_t txSize = 1, cmdBuf[1]; cmdBuf[0] = cmdToSend; gEepromAssertCS_d(); if(spi_master_transfer(mEepromSpiInstance_c, cmdBuf, NULL, txSize) != 0) { status = ee_error; } if ( EEPROM_CMD_END == endFlag ) { gEepromDeassertCS_d(); } return status; }
static ee_err_t EEPROM_SendAddress(uint32_t eepromAddress) { ee_err_t status = ee_ok; uint32_t fmtAddr = 0; // if the address is bigger than 24 bytes, exit if ( eepromAddress > 0x00FFFFFF) { return ee_error; } // arrange bytes fmtAddr |= ( eepromAddress & 0xFF0000 ) >> 16; fmtAddr |= ( eepromAddress & 0x00FF00 ); fmtAddr |= ( eepromAddress & 0x0000FF ) << 16; if(spi_master_transfer(mEepromSpiInstance_c, (uint8_t*)&fmtAddr, NULL, 3) != 0) { status = ee_error; } return status; }
/** * \brief Start SPI transfer test. */ static void spi_master_go(void) { uint32_t cmd; uint32_t block; uint32_t i; /* Configure SPI as master, set up SPI clock. */ spi_master_initialize(); /* * Send CMD_TEST to indicate the start of test, and device shall return * RC_RDY. */ while (1) { cmd = CMD_TEST; puts("-> Master sending CMD_TEST... \r"); spi_master_transfer(&cmd, sizeof(cmd)); if (cmd == RC_RDY) { puts(" <- Slave response RC_SYN, RC_RDY \r"); break; } if (cmd != RC_SYN) { printf("-E- Response unexpected: 0x%x \n\r", (unsigned)cmd); return; } } /* Send CMD_DATA with 4 blocks (64 bytes per page). */ puts("-> Master sending CMD_DATA... \r"); cmd = CMD_DATA | MAX_DATA_BLOCK_NUMBER; spi_master_transfer(&cmd, sizeof(cmd)); puts(" <---- Slave response RC_RDY \r"); for (block = 0; block < MAX_DATA_BLOCK_NUMBER; block++) { for (i = 0; i < COMM_BUFFER_SIZE; i++) { gs_uc_spi_buffer[i] = block; } printf("-> Master sending block %u ... \n\r", (unsigned)block); spi_master_transfer(gs_uc_spi_buffer, COMM_BUFFER_SIZE); if (block) { for (i = 0; i < COMM_BUFFER_SIZE; i++) { if (gs_uc_spi_buffer[i] != (block - 1)) { break; } } if (i < COMM_BUFFER_SIZE) { printf("-E- block %u contains unexpected data \n\r", (unsigned)block); } else { printf(" <- Slave response last block %x \n\r", (unsigned)(block - 1)); } } } for (i = 0; i < MAX_RETRY; i++) { cmd = CMD_STATUS; puts("-> Master sending CMD_STATUS... \r"); spi_master_transfer(&cmd, sizeof(cmd)); if (cmd == RC_RDY) { puts(" <- Slave response RC_RDY \r"); break; } } if (i >= MAX_RETRY) { puts(" <- Slave no response \r"); return; } puts("-> Master request slave status... \r"); spi_master_transfer(&gs_spi_status, sizeof(struct status_block_t)); puts(" <- Slave reports status...\r"); printf("-I- Received %u commands:", (unsigned)gs_spi_status.ul_total_command_number); for (i = 0; i < gs_spi_status.ul_total_command_number; i++) { printf(" 0x%08x", (unsigned)gs_spi_status.ul_cmd_list[i]); } printf(" \n\r-I- Received %lu data blocks \n\r", (unsigned long)gs_spi_status.ul_total_block_number); for (i = 0; i < MAX_RETRY; i++) { puts("-> Master sending CMD_END... \r"); cmd = CMD_END; spi_master_transfer(&cmd, sizeof(cmd)); if (cmd == RC_SYN) { puts(" <- Slave response RC_SYN \r"); break; } } if (i >= MAX_RETRY) { puts(" <- Slave no response \r"); } puts("\r"); puts("SPI transfer test finished! \r"); }
/*------------------------------------------------------------------------------------------------- * @fn APIWriteArrayBytes * * @brief data * * @param none * * @return none * */ void SPIWriteArrayBytes(uint8_t *buf, uint8_t cnt) { uint8_t *p; p = buf; spi_master_transfer(p, cnt); }
int spimem_read(uint32_t addr, uint8_t* read_buff, uint32_t size) { uint32_t i; uint32_t spi_chip; uint32_t size2 = size; uint32_t left_over = 0; if (INTERNAL_MEMORY_FALLBACK_MODE) { if (addr > 0x0FFF) return -2; if ((addr + size -1) > 0x0FFF) size2 = 0x0FFF - size; for (i = 0; i < size2; i++) { *(read_buff + i) = spi_mem_buff[addr + i]; } return size2; } if(SPI_HEALTH1) spi_chip = 1; else if(SPI_HEALTH2) spi_chip = 2; else if(SPI_HEALTH3) spi_chip = 3; else { // Something has gone horribly wrong, let the FDIR task know. // FAILURE_RECOVERY return -1; } if (addr > 0xFFFFF) // Invalid address to write to. return -2; // USAGE_ERROR if ((addr + size2 - 1) > 0xFFFFF) // Read would overflow highest address, read less. size2 = 0xFFFFF - size2; if (xSemaphoreTake(Spi0_Mutex, (TickType_t) 1) == pdTRUE) // Only Block for a single tick. { enter_atomic(); // Atomic operation begins. msg_buff[0] = RD; msg_buff[1] = (uint16_t)((addr & 0x000F0000) >> 16); msg_buff[2] = (uint16_t)((addr & 0x0000FF00) >> 8); msg_buff[3] = (uint16_t)(addr & 0x000000FF); for(i = 4; i < 260; i++) { msg_buff[i] = 0; } if(check_if_wip(spi_chip) != 0) // A write is still in effect, FAILURE_RECOVERY. { exit_atomic(); xSemaphoreGive(Spi0_Mutex); return -4; } spi_master_transfer(msg_buff, 260, spi_chip); // Keeps CS low so that read may begin immediately. for(i = 4; i < (size2 + 4); i++) { *(read_buff + (i - 4)) = (uint8_t)msg_buff[i]; } exit_atomic(); xSemaphoreGive(Spi0_Mutex); return size; }