void spi_release_bus(struct spi_slave *slave)
{
struct omap3_spi_slave *ds = to_omap3_spi(slave);
/* Reset the SPI hardware */
spi_reset(ds);
}
/**
* \brief Test SPI setting.
*
* This test tests SPI reset/enable/disable.
*
* \param test Current test case.
*/
static void run_spi_ctrl_test(const struct test_case *test)
{
spi_enable_clock(CONF_TEST_SPI);
/* Test enable */
spi_enable(CONF_TEST_SPI);
test_assert_true(test, spi_is_enabled(CONF_TEST_SPI),
"Test SPI enable: enable failed");
/* Test reset */
spi_reset(CONF_TEST_SPI);
test_assert_true(test,
!spi_is_enabled(CONF_TEST_SPI) &&
CONF_TEST_SPI->SPI_MR == 0 &&
CONF_TEST_SPI->SPI_IMR == 0 &&
CONF_TEST_SPI->SPI_CSR[0] == 0 &&
CONF_TEST_SPI->SPI_CSR[1] == 0 &&
CONF_TEST_SPI->SPI_CSR[2] == 0 &&
CONF_TEST_SPI->SPI_CSR[3] == 0 &&
#if SAM4L
CONF_TEST_SPI->SPI_WPCR == 0,
#else
CONF_TEST_SPI->SPI_WPMR == 0,
#endif
"Test SPI reset: should have read 0");
}
/*
* SPI2:
* SCK - PB13
* MISO - PB14
* MOSI - PB15
*/
void SPI2_init(){
// turn on clocking
//rcc_periph_clock_enable(RCC_SPI2 | RCC_GPIOB);
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN);
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPBEN);
// SCK, MOSI - push-pull output
gpio_set_mode(GPIO_BANK_SPI2_SCK, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI2_SCK);
gpio_set_mode(GPIO_BANK_SPI2_MOSI, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI2_MOSI);
// MISO - opendrain in
gpio_set_mode(GPIO_BANK_SPI2_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI2_MISO);
spi_reset(SPI2);
/* Set up SPI in Master mode with:
* Clock baud rate: 1/64 of peripheral clock frequency (APB1, 36MHz)
* Clock polarity: Idle High
* Clock phase: Data valid on 2nd clock pulse
* Data frame format: 8-bit
* Frame format: MSB First
*/
spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
// nvic_enable_irq(NVIC_SPI2_IRQ); // enable SPI interrupt
spi_enable(Current_SPI);
}
/*
* SPI1 remapped:
* SCK - PB3
* MISO - PB4
* MOSI - PB5
*/
void SPI1_init(){
// enable AFIO & other clocking
rcc_peripheral_enable_clock(&RCC_APB2ENR,
RCC_APB2ENR_SPI1EN | RCC_APB2ENR_AFIOEN | RCC_APB2ENR_IOPBEN);
// remap SPI1 (change pins from PA5..7 to PB3..5); also turn off JTAG
gpio_primary_remap(AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF, AFIO_MAPR_SPI1_REMAP);
// SCK, MOSI - push-pull output
gpio_set_mode(GPIO_BANK_SPI1_RE_SCK, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_RE_SCK);
gpio_set_mode(GPIO_BANK_SPI1_RE_MOSI, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI1_RE_MOSI);
// MISO - opendrain in
gpio_set_mode(GPIO_BANK_SPI1_RE_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT, GPIO_SPI1_RE_MISO);
spi_reset(SPI1);
/* Set up SPI in Master mode with:
* Clock baud rate: 1/128 of peripheral clock frequency (APB2, 72MHz)
* Clock polarity: CPOL=0, CPHA=0
* Data frame format: 8-bit
* Frame format: MSB First
*/
spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_256, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
nvic_enable_irq(NVIC_SPI1_IRQ); // enable SPI interrupt
spi_enable(Current_SPI);
}
/**
* \internal
* \brief Initialize Proxy PLC controller.
*
* This function will change the system clock prescaler configuration to
* match the parameters.
*
* \note The parameters to this function are device-specific.
*
*/
static void _pplc_if_config(void)
{
uint32_t ul_cpuhz;
uint8_t uc_div;
ul_cpuhz = sysclk_get_cpu_hz();
uc_div = ul_cpuhz / gs_ul_pplc_clock;
/* Enable SPI peripheral. */
spi_enable_clock(PPLC_SPI_MODULE);
/* Reset SPI */
spi_disable(PPLC_SPI_MODULE);
spi_reset(PPLC_SPI_MODULE);
/* Configure SPI */
spi_set_master_mode(PPLC_SPI_MODULE);
spi_disable_mode_fault_detect(PPLC_SPI_MODULE);
spi_set_peripheral_chip_select_value(PPLC_SPI_MODULE, PPLC_PCS);
spi_set_clock_polarity(PPLC_SPI_MODULE, PPLC_CS, 0);
spi_set_clock_phase(PPLC_SPI_MODULE, PPLC_CS, 1);
spi_set_bits_per_transfer(PPLC_SPI_MODULE, PPLC_CS, SPI_CSR_BITS_8_BIT);
spi_set_fixed_peripheral_select(PPLC_SPI_MODULE);
spi_set_baudrate_div(PPLC_SPI_MODULE, PPLC_CS, uc_div);
spi_set_transfer_delay(PPLC_SPI_MODULE, PPLC_CS, PPLC_DLYBS,
PPLC_DLYBCT);
spi_configure_cs_behavior(PPLC_SPI_MODULE, PPLC_CS, SPI_CS_RISE_NO_TX);
/* Get board PPLC PDC base address and enable receiver and transmitter */
g_pplc_pdc = spi_get_pdc_base(PPLC_SPI_MODULE);
spi_enable(PPLC_SPI_MODULE);
}
/**
* \brief Initialize SPI as slave.
*/
static void spi_slave_initialize(void)
{
uint32_t i;
/* Reset status */
gs_spi_status.ul_total_block_number = 0;
gs_spi_status.ul_total_command_number = 0;
for (i = 0; i < NB_STATUS_CMD; i++) {
gs_spi_status.ul_cmd_list[i] = 0;
}
gs_ul_spi_state = SLAVE_STATE_IDLE;
gs_ul_spi_cmd = RC_SYN;
puts("-I- Initialize SPI as slave \r");
/* Configure an SPI peripheral. */
spi_enable_clock(SPI_SLAVE_BASE);
spi_disable(SPI_SLAVE_BASE);
spi_reset(SPI_SLAVE_BASE);
spi_set_slave_mode(SPI_SLAVE_BASE);
spi_disable_mode_fault_detect(SPI_SLAVE_BASE);
spi_set_peripheral_chip_select_value(SPI_SLAVE_BASE, SPI_CHIP_SEL);
spi_set_clock_polarity(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_enable_interrupt(SPI_SLAVE_BASE, SPI_IER_RDRF);
spi_enable(SPI_SLAVE_BASE);
/* Start waiting command. */
spi_slave_transfer(&gs_ul_spi_cmd, sizeof(gs_ul_spi_cmd));
}
int devspi_xfer(struct spi_slave *sl, const char *obuf, char *ibuf, unsigned int len)
{
struct dev_spi *spi;
int i;
if (len <= 0)
return len;
spi = DEV_SPI[sl->bus];
if (!spi)
return -EINVAL;
mutex_lock(spi->mutex);
spi_reset(spi->base);
spi->sl = sl;
//init_dma(spi->tx_dma_config, (uint32_t)obuf, len);
//init_dma(spi->rx_dma_config, (uint32_t)ibuf, len);
//dma_enable_transfer_complete_interrupt(spi->rx_dma_config->base, spi->rx_dma_config->stream);
//nvic_set_priority(spi->rx_dma_config->irq, 1);
//nvic_enable_irq(spi->rx_dma_config->irq);
spi_enable(spi->base);
//spi_enable_rx_dma(spi->base);
//spi_enable_tx_dma(spi->base);
for(i = 0; i < len; i++) {
spi_send(spi->base, (uint16_t)obuf[i]);
}
return len;
}
void radio_init()
{
rcc_periph_clock_enable(R_RCC_SPI);
rcc_periph_clock_enable(R_RCC_GPIO);
gpio_mode_setup(R_SPI_PORT, GPIO_MODE_AF, GPIO_PUPD_NONE,
R_SPI_PINS);
gpio_set_af(R_SPI_PORT, R_SPI_AFn, R_SPI_PINS);
gpio_mode_setup(R_CS_PORT, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE,
R_CS_PIN);
// Reset and enable the SPI periph
spi_reset(R_SPI);
spi_init_master(R_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_64,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_CRCL_8BIT,
SPI_CR1_MSBFIRST);
// Trigger an RXNE event when we have 8 bits (one byte) in the buffer
spi_fifo_reception_threshold_8bit(R_SPI);
// NSS must be set high for the peripheral to function
spi_enable_software_slave_management(R_SPI);
spi_set_nss_high(R_SPI);
gpio_set(R_CS_PORT, R_CS_PIN);
// Enable
spi_enable(R_SPI);
radio_sleep();
}
/*
* 初始化SPI寄存器
* */
static void spi_init(void)
{
#ifdef _DEBUG_GM814X
printk(KERN_INFO "2-----spi_init------\n");
#endif
gpio_select();
clock_enable();
spi_reset();
// 1. SET CH_CFG
CH_CFG = HIGH_SPEED_EN | SW_RST | MASTER | CPOL | CPHA;
// 2. SET CLK_CFG
CLK_CFG &= ~ ( 0x7ff );
CLK_CFG = SPI_CLKSEL | ENCLK | SPI_SCALER;
// 3. SET MODE_CFG
MODE_CFG &= ( u32 ) ( 1 << 31 );
MODE_CFG = CH_WIDTH | TRAILING_CNT | BUS_WIDTH | RX_RDY_LVL | TX_RDY_LVL | RX_DMA_SW | TX_DMA_SW | DMA_TYPE;
// 4. SET SLAVE_SEL
SLAVE_SEL = SLAVE_CS_HIGH |SLAVE_AUTO_OFF;
// 5. SET SPI_INT_EN
SPI_INT_EN = SPI_INT_ENABLE;
// 6. SET SWAP_CONFIG
SWAP_CONFIG = RX_SWAP_EN | RX_SWAP_MODE | TX_SWAP_EN | TX_SWAP_MODE;
#ifdef _DEBUG_GM814X
printk(KERN_INFO "2------spi_init end---------\n");
#endif
}
void spi_release_bus(struct spi_slave *slave)
{
struct omap3_spi_priv *priv = to_omap3_spi(slave);
/* Reset the SPI hardware */
spi_reset(priv->regs);
}
/** Initialize the SPI peripheral
*
* Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
* @param[out] obj The SPI object to initialize
* @param[in] mosi The pin to use for MOSI
* @param[in] miso The pin to use for MISO
* @param[in] sclk The pin to use for SCLK
*/
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk)
{
MBED_ASSERT(obj);
MBED_ASSERT(mosi !=NC && miso!=NC && sclk !=NC );
if (g_sys_init == 0) {
sysclk_init();
system_board_init();
g_sys_init = 1;
}
Spi *sercombase = pinmap_find_sercom(mosi,miso,sclk);
MBED_ASSERT(sercombase!=NC);
pinmap_find_spi_info(sercombase, obj);
MBED_ASSERT(obj->spi.flexcom!=NC);
MBED_ASSERT(obj->spi.pdc!=NC);
/* Configure SPI pins */
pin_function(mosi, pinmap_find_function(mosi, PinMap_SPI_MOSI));
ioport_disable_pin(mosi);
pin_function(miso, pinmap_find_function(miso, PinMap_SPI_MISO));
ioport_disable_pin(miso);
pin_function(sclk, pinmap_find_function(sclk, PinMap_SPI_SCLK));
ioport_disable_pin(sclk);
#if (SAMG55)
/* Enable the peripheral and set SPI mode. */
flexcom_enable(obj->spi.flexcom);
flexcom_set_opmode(obj->spi.flexcom, FLEXCOM_SPI);
#else
/* Configure an SPI peripheral. */
spi_enable_clock(sercombase);
#endif
spi_disable(sercombase);
spi_reset(sercombase);
spi_set_lastxfer(sercombase);
spi_set_master_mode(sercombase);
spi_disable_mode_fault_detect(sercombase);
spi_set_peripheral_chip_select_value(sercombase, SPI_CHIP_SEL);
spi_set_clock_polarity(sercombase, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(sercombase, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(sercombase, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(sercombase, SPI_CHIP_SEL,(sysclk_get_cpu_hz() / gSPI_clock));
spi_set_transfer_delay(sercombase, SPI_CHIP_SEL, SPI_DLYBS,SPI_DLYBCT);
spi_enable(sercombase);
pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS);
obj->spi.spi_base=sercombase;
obj->spi.cs= SPI_CHIP_SEL;
obj->spi.polarity=SPI_CLK_POLARITY;
obj->spi.phase=SPI_CLK_PHASE;
obj->spi.transferrate=SPI_CSR_BITS_8_BIT;
obj->spi.is_slave=0;
}
void spi_release_bus(struct spi_slave *slave)
{
struct ipq_spi_slave *ds = to_ipq_spi(slave);
/* Reset the SPI hardware */
spi_reset(ds);
ds->initialized = 0;
}
platform_result_t platform_spi_deinit( const platform_spi_t* spi )
{
UNUSED_PARAMETER(spi);
/* Disable the RX and TX PDC transfer requests */
spi_disable( spi->peripheral );
spi_reset( spi->peripheral );
return PLATFORM_SUCCESS;
}
/**
* \brief Initialize SPI as master.
*/
static void spi_master_initialize(void)
{
/* Configure an SPI peripheral. */
uint32_t spi_chip_sel, spi_clk_freq, spi_clk_pol, spi_clk_pha;
spi_enable_clock(SPI_MASTER_BASE);
spi_reset(SPI_MASTER_BASE);
spi_set_master_mode(SPI_MASTER_BASE);
spi_disable_mode_fault_detect(SPI_MASTER_BASE);
spi_disable_loopback(SPI_MASTER_BASE);
spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, spi_get_pcs(2)); // This sets the value of PCS within the Mode Register.
spi_set_variable_peripheral_select(SPI_MASTER_BASE); // PCS needs to be set within each transfer (PCS within SPI_TDR).
spi_disable_peripheral_select_decode(SPI_MASTER_BASE); // Each CS is to be connected to a single device.
spi_set_delay_between_chip_select(SPI_MASTER_BASE, SPI_DLYBCS);
/* Set communication parameters for CS0 */
spi_chip_sel = 0;
spi_clk_freq = 100000; // SPI CLK for RTC = 100kHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_16_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED); // CS rises after SPI transfers have completed.
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS1 */
spi_chip_sel = 1;
spi_clk_freq = 2000000; // SPI CLK for RTC = 4MHz.
spi_clk_pol = 0;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Set communication parameters for CS2 */
spi_chip_sel = 2;
spi_clk_freq = 44000000; // SPI CLK for MEM2 = 44MHz.
spi_clk_pol = 1;
spi_clk_pha = 0;
spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
SPI_DLYBCT);
spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
/* Enable SPI Communication */
spi_enable(SPI_MASTER_BASE);
}
void send_data_to_autopilot_task(void)
{
if ( !SpiIsSelected() && spi_was_interrupted )
{
spi_was_interrupted = FALSE;
to_autopilot_from_last_radio();
spi_reset();
}
}
static int omap3_spi_release_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
struct omap3_spi_priv *priv = dev_get_priv(bus);
/* Reset the SPI hardware */
spi_reset(priv->regs);
return 0;
}
void _Pragma("entrypoint") send_data_to_autopilot_task(void)
{
#ifndef WCET_ANALYSIS
if ( !SpiIsSelected() && spi_was_interrupted )
{
spi_was_interrupted = FALSE;
to_autopilot_from_last_radio();
spi_reset();
}
#endif
}
/** \brief Initialize the SPI in master mode.
*
* \param p_spi Base address of the SPI instance.
*
*/
void spi_master_init(Spi *p_spi)
{
spi_enable_clock(p_spi);
spi_reset(p_spi);
spi_set_master_mode(p_spi);
spi_disable_mode_fault_detect(p_spi);
spi_disable_loopback(p_spi);
spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
spi_set_fixed_peripheral_select(p_spi);
spi_disable_peripheral_select_decode(p_spi);
spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
}
static void _spi_init_base(Spi * spi_base)
{
spi_enable_clock(spi_base);
spi_disable(spi_base);
spi_reset(spi_base);
spi_set_lastxfer(spi_base);
spi_set_master_mode(spi_base);
spi_disable_mode_fault_detect(spi_base);
spi_set_variable_peripheral_select(spi_base);
spi_enable_interrupt(_spi_base, SPI_IER_RDRF);
// spi_enable_loopback(spi_base); // ??????????????????
}
/*
* @fn nm_bus_init
* @brief Initialize the bus wrapper
* @return M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
*/
sint8 nm_bus_init(void *pvinit)
{
sint8 result = M2M_SUCCESS;
#ifdef CONF_WINC_USE_I2C
twihs_options_t opt;
/* Enable the peripheral clock for TWI */
pmc_enable_periph_clk(CONF_WINC_I2C_ID);
/* Configure the options of TWI driver */
opt.master_clk = sysclk_get_peripheral_hz();
opt.speed = CONF_WINC_TWIHS_CLOCK;
if (twihs_master_init(CONF_WINC_I2C, &opt) != TWIHS_SUCCESS) {
M2M_ERR("-E-\tTWI master initialization failed.\r");
while (1) {
/* Capture error */
}
}
#elif CONF_WINC_USE_SPI
/* Configure SPI pins. */
ioport_set_pin_mode(CONF_WINC_SPI_MISO_GPIO, CONF_WINC_SPI_MISO_FLAGS);
ioport_set_pin_mode(CONF_WINC_SPI_MOSI_GPIO, CONF_WINC_SPI_MOSI_FLAGS);
ioport_set_pin_mode(CONF_WINC_SPI_CLK_GPIO, CONF_WINC_SPI_CLK_FLAGS);
ioport_set_pin_mode(CONF_WINC_SPI_CS_GPIO, CONF_WINC_SPI_CS_FLAGS);
ioport_disable_pin(CONF_WINC_SPI_MISO_GPIO);
ioport_disable_pin(CONF_WINC_SPI_MOSI_GPIO);
ioport_disable_pin(CONF_WINC_SPI_CLK_GPIO);
ioport_disable_pin(CONF_WINC_SPI_CS_GPIO);
spi_enable_clock(CONF_WINC_SPI);
spi_disable(CONF_WINC_SPI);
spi_reset(CONF_WINC_SPI);
spi_set_master_mode(CONF_WINC_SPI);
spi_disable_mode_fault_detect(CONF_WINC_SPI);
spi_set_peripheral_chip_select_value(CONF_WINC_SPI, CONF_WINC_SPI_NPCS);
spi_set_clock_polarity(CONF_WINC_SPI,
CONF_WINC_SPI_NPCS, CONF_WINC_SPI_POL);
spi_set_clock_phase(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_PHA);
spi_set_bits_per_transfer(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(CONF_WINC_SPI, CONF_WINC_SPI_NPCS,
(sysclk_get_cpu_hz() / CONF_WINC_SPI_CLOCK));
spi_set_transfer_delay(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_DLYBS,
CONF_WINC_SPI_DLYBCT);
spi_enable(CONF_WINC_SPI);
nm_bsp_reset();
#endif
return result;
}
void spi_setup(void) {
pmc_enable_peripheral_clock(ID_SPI0);
pmc_enable_peripheral_clock(ID_PIOA);
pio_conf_pin_to_peripheral(PIOA, 0, 25); //MISO
pio_conf_pin_to_peripheral(PIOA, 0, 26); //MOSI
pio_conf_pin_to_peripheral(PIOA, 0, 27); //SPCK
pio_conf_pin_to_peripheral(PIOA, 0, 28); //NPCS0
pio_conf_pin_to_peripheral(PIOA, 0, 29); //NPCS1
pio_conf_pin_to_peripheral(PIOA, 0, 30); //NPSC2
pio_conf_pin_to_peripheral(PIOA, 0, 31); //NPSC3
spi_reset(SPI0);
}
void send_data_to_autopilot_task(void)
{
//vPrintString("S_2 send_data_to_autopilot_task start! \n\r"); //SunnyBeike
// modified by wanbo
// if ( !SpiIsSelected() && spi_was_interrupted )
{
spi_was_interrupted = FALSE;
to_autopilot_from_last_radio();
spi_reset();
}
//vPrintString("S_2 send_data_to_autopilot_task end! \n\r"); //SunnyBeike
}
void spi_start(void)
{
/* Reset flash chip */
gpio_clear(GPIOD, BL_SPI2_RST);
wait(10);
gpio_set(GPIOD, BL_SPI2_RST);
wait(10);
gpio_set(GPIOD, BL_SPI2_WP);
/* No WriteProtect, Set Chip select to 1(no select) */
gpio_set(GPIOB, BL_SPI2_NSS);
/* Reset and disable SPI */
spi_reset(SPI2);
/* Disable I2S */
SPI2_I2SCFGR = 0;
/* CR1 */
spi_set_clock_phase_0(SPI2); /* CPHA = 0 */
spi_set_clock_polarity_0(SPI2); /* CPOL = 0 */
spi_send_msb_first(SPI2); /* LSB = 0 */
spi_set_full_duplex_mode(SPI2); /* RXONLY = 0 */
spi_set_unidirectional_mode(SPI2); /* BIDI = 0 */
spi_enable_software_slave_management(SPI2); /* SSM = 1 */
spi_set_nss_high(SPI2); /* SSI = 1 */
spi_set_master_mode(SPI2); /* MSTR = 1 */
spi_set_dff_8bit(SPI2); /* DFf = 8 bit */
// spi_enable_crc(SPI2);
/* XXX: Too fast? Maybe DIV_4 will be better? */
spi_set_baudrate_prescaler(SPI2, SPI_CR1_BR_FPCLK_DIV_2);
/* CR2 */
spi_enable_ss_output(SPI2); /* SSOE = 1 */
/* Disable regular interrupt flags */
spi_disable_tx_buffer_empty_interrupt(SPI2);
spi_disable_rx_buffer_not_empty_interrupt(SPI2);
spi_disable_error_interrupt(SPI2);
/* Enabling RX/TX DMA flags */
spi_enable_tx_dma(SPI2);
spi_enable_rx_dma(SPI2);
d_print("REG: %lu:%lu\r\n", SPI_CR1(SPI2), SPI_CR2(SPI2));
spi_enable(SPI2);
}
/*--------------------------------------------------------------------------*/
static void spi_setup(void) {
/* Configure GPIOs: SS=PB12, SCK=PB13, MISO=PB14 and MOSI=PB15
* For now ignore the SS pin so we can use it to time the ISRs
*/
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, /* GPIO4 | */
GPIO13 |
GPIO15 );
gpio_set_mode(GPIOB, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT,
GPIO14);
/* Reset SPI, SPI_CR1 register cleared, SPI is disabled */
spi_reset(SPI2);
/* Explicitly disable I2S in favour of SPI operation */
SPI2_I2SCFGR = 0;
/* Set up SPI in Master mode with:
* Clock baud rate: 1/64 of peripheral clock frequency
* Clock polarity: Idle High
* Clock phase: Data valid on 2nd clock pulse
* Data frame format: 8-bit or 16-bit
* Frame format: MSB First
*/
#if USE_16BIT_TRANSFERS
spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_16BIT, SPI_CR1_MSBFIRST);
#else
spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
#endif
/*
* Set NSS management to software.
*
* Note:
* Setting nss high is very important, even if we are controlling the GPIO
* ourselves this bit needs to be at least set to 1, otherwise the spi
* peripheral will not send any data out.
*/
spi_enable_software_slave_management(SPI2);
spi_set_nss_high(SPI2);
/* Enable SPI2 periph. */
spi_enable(SPI2);
}
static void acq_spi_init(uint32_t spi)
{
spi_reset(spi);
spi_init_master(spi,
SPI_CR1_BAUDRATE_FPCLK_DIV_2,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
0,
SPI_CR1_MSBFIRST);
spi_set_data_size(spi, SPI_CR2_DS_14BIT);
spi_set_receive_only_mode(spi);
spi_fifo_reception_threshold_16bit(spi);
SPI_CR2(spi) |= SPI_CR2_NSSP;
spi_enable_rx_buffer_not_empty_interrupt(spi);
}
static void spi_setup(void) {
/* Radio RST */
gpio_set_mode(GPIOB, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO0);
/* Configure GPIOs: SS=PA4, SCK=PA5, MISO=PA6 and MOSI=PA7 */
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_PUSHPULL, GPIO4);
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO5 |
GPIO7 );
gpio_set_mode(GPIOA, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT,
GPIO6);
/* Reset SPI, SPI_CR1 register cleared, SPI is disabled */
spi_reset(SPI1);
/* Set up SPI in Master mode with:
* Clock baud rate: 1/64 of peripheral clock frequency
* Clock polarity: Idle High
* Clock phase: Data valid on 2nd clock pulse
* Data frame format: 8-bit
* Frame format: MSB First
*/
spi_init_master(SPI1,
SPI_CR1_BAUDRATE_FPCLK_DIV_64,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_DFF_8BIT,
SPI_CR1_MSBFIRST);
/*
* Set NSS management to software.
*
* Note:
* Setting nss high is very important, even if we are controlling the GPIO
* ourselves this bit needs to be at least set to 1, otherwise the spi
* peripheral will not send any data out.
*/
spi_enable_software_slave_management(SPI1);
spi_set_nss_high(SPI1);
/* Enable SPI1 periph. */
spi_enable(SPI1);
}
/** \brief Initialize the SPI in master mode.
*
* \param p_spi Base address of the SPI instance.
*
*/
void spi_master_init(Spi *p_spi)
{
#if SAMG55
flexcom_enable(BOARD_FLEXCOM_SPI);
flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
#else
spi_enable_clock(p_spi);
#endif
spi_reset(p_spi);
spi_set_master_mode(p_spi);
spi_disable_mode_fault_detect(p_spi);
spi_disable_loopback(p_spi);
spi_set_peripheral_chip_select_value(p_spi, DEFAULT_CHIP_ID);
spi_set_fixed_peripheral_select(p_spi);
spi_disable_peripheral_select_decode(p_spi);
spi_set_delay_between_chip_select(p_spi, CONFIG_SPI_MASTER_DELAY_BCS);
}
/* Function to setup the SPI1 */
static void spi_setup(void)
{
/* Enable SPI1 clock. */
rcc_periph_clock_enable(RCC_SPI1);
/* reset SPI1 */
spi_reset(SPI1);
/* init SPI1 master */
spi_init_master(SPI1,
SPI_CR1_BAUDRATE_FPCLK_DIV_64,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
SPI_CR1_DFF_8BIT,
SPI_CR1_MSBFIRST);
/* enable SPI1 first */
spi_enable(SPI1);
}
/**
* \brief Initialize SPI as slave.
*/
static void spi_slave_initialize(void)
{
g_uc_role = SLAVE_MODE;
puts("-I- Initialize SPI as slave \r");
/* Configure an SPI peripheral. */
spi_enable_clock(SPI_SLAVE_BASE);
spi_disable(SPI_SLAVE_BASE);
spi_reset(SPI_SLAVE_BASE);
spi_set_slave_mode(SPI_SLAVE_BASE);
spi_disable_mode_fault_detect(SPI_SLAVE_BASE);
spi_set_peripheral_chip_select_value(SPI_SLAVE_BASE, SPI_CHIP_PCS);
spi_set_clock_polarity(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI_SLAVE_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_enable(SPI_SLAVE_BASE);
}
/**
* \brief Set up an SPI device.
*
* The returned device descriptor structure must be passed to the driver
* whenever that device should be used as current slave device.
*
* \param p_spi Base address of the SPI instance.
* \param device Pointer to SPI device struct that should be initialized.
* \param flags SPI configuration flags. Common flags for all
* implementations are the SPI modes SPI_MODE_0 ...
* SPI_MODE_3.
* \param baud_rate Baud rate for communication with slave device in Hz.
* \param sel_id Board specific select id.
*/
void spi_master_setup_device(Spi *p_spi, const struct spi_device *device,
spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
{
/* avoid Cppcheck Warning */
UNUSED(sel_id);
UNUSED(flags);
spi_reset(p_spi);
spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
CONFIG_SPI_MASTER_DELAY_BCT);
spi_set_bits_per_transfer(p_spi, device->id,
CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
int16_t baud_div = spi_calc_baudrate_div(baud_rate, SystemCoreClock);
spi_set_baudrate_div(p_spi, device->id, baud_div);
spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
spi_set_clock_polarity(p_spi, device->id, flags >> 1);
spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
}