void spi_setup(void) {
rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN);
/* For spi signal pins */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPAEN);
/* For spi mode select on the l3gd20 */
rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPEEN);
/* Setup GPIOE3 pin for spi mode l3gd20 select. */
gpio_mode_setup(GPIOE, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, GPIO3);
/* Start with spi communication disabled */
gpio_set(GPIOE, GPIO3);
/* Setup GPIO pins for AF5 for SPI1 signals. */
gpio_mode_setup(GPIOA, GPIO_MODE_AF, GPIO_PUPD_NONE, GPIO5 | GPIO6 | GPIO7);
gpio_set_af(GPIOA, GPIO_AF5, GPIO5 | GPIO6 | GPIO7);
//spi initialization;
spi_set_master_mode(SPI1);
spi_set_baudrate_prescaler(SPI1, SPI_CR1_BR_FPCLK_DIV_64);
spi_set_clock_polarity_0(SPI1);
spi_set_clock_phase_0(SPI1);
spi_set_full_duplex_mode(SPI1);
spi_set_unidirectional_mode(SPI1); /* bidirectional but in 3-wire */
spi_set_data_size(SPI1, SPI_CR2_DS_8BIT);
spi_enable_software_slave_management(SPI1);
spi_send_msb_first(SPI1);
spi_set_nss_high(SPI1);
//spi_enable_ss_output(SPI1);
spi_fifo_reception_threshold_8bit(SPI1);
SPI_I2SCFGR(SPI1) &= ~SPI_I2SCFGR_I2SMOD;
spi_enable(SPI1);
}
/* Setup the SPI bus. This function may cause spurious signals on the SPI bus,
* so it should be called before the transaction starts (i.e. while SS is high).
* -CPOL is the clock polarity (0 or 1)
* -CPHA is the clock phase (0 or 1)
* -baudrate is one of libopencm3's SPI_CR1_BAUDRATE_FPCLK_DIV_X values.
* Baudrates are derived from the low-speed peripheral clock APB1.
* -firstbit is either SPI_CR1_MSBFIRST or SPI_CR1_LSBFIRST. */
void setup_spi(uint8_t cpol, uint8_t cpha, uint8_t baudrate, uint8_t firstbit){
disable_and_reset_spi_properly();
SPI_CR1(SPI3) &= 0xFFC7; /* Mask off baudrate bits. */
SPI_CR1(SPI3) |= baudrate;
if(0 == cpol){
spi_set_clock_polarity_0(SPI3);
} else {
spi_set_clock_polarity_1(SPI3);
}
if(0 == cpha){
spi_set_clock_phase_0(SPI3);
} else {
spi_set_clock_polarity_1(SPI3);
}
spi_set_unidirectional_mode(SPI3); /* bidirectional but in 3-wire */
spi_set_full_duplex_mode(SPI3);
SPI_CR1(SPI3) &= ~SPI_CR1_LSBFIRST;
SPI_CR1(SPI3) |= firstbit;
spi_enable_software_slave_management(SPI3);
spi_set_nss_high(SPI3);
spi_set_master_mode(SPI3);
spi_set_data_size(SPI3, SPI_CR2_DS_8BIT);
spi_fifo_reception_threshold_8bit(SPI3);
SPI_I2SCFGR(SPI3) &= ~SPI_I2SCFGR_I2SMOD;
/* All DMA configuration is handled by tx_spi(), rx_spi(), and rxtx_spi(). */
}
static void acq_spi_init(uint32_t spi)
{
spi_reset(spi);
spi_init_master(spi,
SPI_CR1_BAUDRATE_FPCLK_DIV_2,
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
SPI_CR1_CPHA_CLK_TRANSITION_1,
0,
SPI_CR1_MSBFIRST);
spi_set_data_size(spi, SPI_CR2_DS_14BIT);
spi_set_receive_only_mode(spi);
spi_fifo_reception_threshold_16bit(spi);
SPI_CR2(spi) |= SPI_CR2_NSSP;
spi_enable_rx_buffer_not_empty_interrupt(spi);
}
static void spi_setup(void)
{
spi_set_master_mode(SPI1);
spi_set_baudrate_prescaler(SPI1, SPI_CR1_BR_FPCLK_DIV_64);
spi_set_clock_polarity_1(SPI1);
spi_set_clock_phase_0(SPI1);
spi_set_bidirectional_transmit_only_mode(SPI1);
//spi_set_unidirectional_mode(SPI1); /* bidirectional but in 3-wire */
spi_set_data_size(SPI1, SPI_CR2_DS_16BIT);
//spi_enable_software_slave_management(SPI1);
spi_send_msb_first(SPI1);
spi_set_nss_low(SPI1);
//spi_enable_ss_output(SPI1);
//spi_fifo_reception_threshold_8bit(SPI1);
//SPI_I2SCFGR(SPI1) &= ~SPI_I2SCFGR_I2SMOD;
spi_enable(SPI1);
}
