Beispiel #1
0
/**
 * \brief Initialize SPI as master.
 */
static void spi_master_initialize(void)
{
	/* Configure an SPI peripheral. */
	uint32_t spi_chip_sel, spi_clk_freq, spi_clk_pol, spi_clk_pha;
	spi_enable_clock(SPI_MASTER_BASE);
	spi_reset(SPI_MASTER_BASE);
	spi_set_master_mode(SPI_MASTER_BASE);
	spi_disable_mode_fault_detect(SPI_MASTER_BASE);
	spi_disable_loopback(SPI_MASTER_BASE);

	spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, spi_get_pcs(2));	// This sets the value of PCS within the Mode Register.
	spi_set_variable_peripheral_select(SPI_MASTER_BASE);					// PCS needs to be set within each transfer (PCS within SPI_TDR).
	spi_disable_peripheral_select_decode(SPI_MASTER_BASE);					// Each CS is to be connected to a single device.
	spi_set_delay_between_chip_select(SPI_MASTER_BASE, SPI_DLYBCS);

	/* Set communication parameters for CS0	*/
	spi_chip_sel = 0;
	spi_clk_freq = 100000;	// SPI CLK for RTC = 100kHz.
	spi_clk_pol = 1;
	spi_clk_pha = 0;
	spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
			SPI_DLYBCT);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_16_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz())); 
	spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED);		// CS rises after SPI transfers have completed.
	spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
	spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
	
	/* Set communication parameters for CS1	*/
	spi_chip_sel = 1;
	spi_clk_freq = 2000000;	// SPI CLK for RTC = 4MHz.
	spi_clk_pol = 0;
	spi_clk_pha = 0;
	spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
	SPI_DLYBCT);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz())); 
	spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_RISE_FORCED);
	spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
	spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
	
	/* Set communication parameters for CS2	*/
	spi_chip_sel = 2;
	spi_clk_freq = 44000000;	// SPI CLK for MEM2 = 44MHz.
	spi_clk_pol = 1;
	spi_clk_pha = 0;
	spi_set_transfer_delay(SPI_MASTER_BASE, spi_chip_sel, SPI_DLYBS,
	SPI_DLYBCT);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, spi_chip_sel, SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, spi_chip_sel, spi_calc_baudrate_div(spi_clk_freq, sysclk_get_cpu_hz()));
	spi_configure_cs_behavior(SPI_MASTER_BASE, spi_chip_sel, SPI_CS_KEEP_LOW);
	spi_set_clock_polarity(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pol);
	spi_set_clock_phase(SPI_MASTER_BASE, spi_chip_sel, spi_clk_pha);
	
	/* Enable SPI Communication */
	spi_enable(SPI_MASTER_BASE);
}
Beispiel #2
0
/**
 * \internal
 * \brief Initialize Proxy PLC controller.
 *
 * This function will change the system clock prescaler configuration to
 * match the parameters.
 *
 * \note The parameters to this function are device-specific.
 *
 */
static void _pplc_if_config(void)
{
	uint32_t ul_cpuhz;
	uint8_t uc_div;

	ul_cpuhz = sysclk_get_cpu_hz();
	uc_div = ul_cpuhz / gs_ul_pplc_clock;

	/* Enable SPI peripheral. */
	spi_enable_clock(PPLC_SPI_MODULE);

	/* Reset SPI */
	spi_disable(PPLC_SPI_MODULE);
	spi_reset(PPLC_SPI_MODULE);

	/* Configure SPI */
	spi_set_master_mode(PPLC_SPI_MODULE);
	spi_disable_mode_fault_detect(PPLC_SPI_MODULE);
	spi_set_peripheral_chip_select_value(PPLC_SPI_MODULE, PPLC_PCS);
	spi_set_clock_polarity(PPLC_SPI_MODULE, PPLC_CS, 0);
	spi_set_clock_phase(PPLC_SPI_MODULE, PPLC_CS, 1);
	spi_set_bits_per_transfer(PPLC_SPI_MODULE, PPLC_CS, SPI_CSR_BITS_8_BIT);
	spi_set_fixed_peripheral_select(PPLC_SPI_MODULE);
	spi_set_baudrate_div(PPLC_SPI_MODULE, PPLC_CS, uc_div);
	spi_set_transfer_delay(PPLC_SPI_MODULE, PPLC_CS, PPLC_DLYBS,
			PPLC_DLYBCT);
	spi_configure_cs_behavior(PPLC_SPI_MODULE, PPLC_CS, SPI_CS_RISE_NO_TX);

	/* Get board PPLC PDC base address and enable receiver and transmitter */
	g_pplc_pdc = spi_get_pdc_base(PPLC_SPI_MODULE);
	spi_enable(PPLC_SPI_MODULE);
}
/** Initialize the SPI peripheral
 *
 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
 * @param[out] obj  The SPI object to initialize
 * @param[in]  mosi The pin to use for MOSI
 * @param[in]  miso The pin to use for MISO
 * @param[in]  sclk The pin to use for SCLK
 */
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk)
{
	MBED_ASSERT(obj);
	MBED_ASSERT(mosi !=NC && miso!=NC && sclk !=NC );
	
	 if (g_sys_init == 0) {
        sysclk_init();
        system_board_init();
        g_sys_init = 1;
    }
	
	Spi *sercombase = pinmap_find_sercom(mosi,miso,sclk);
	MBED_ASSERT(sercombase!=NC);
	
	pinmap_find_spi_info(sercombase, obj);
	MBED_ASSERT(obj->spi.flexcom!=NC);
	MBED_ASSERT(obj->spi.pdc!=NC);
	
    /* Configure SPI pins */
    pin_function(mosi, pinmap_find_function(mosi, PinMap_SPI_MOSI));
    ioport_disable_pin(mosi);

    pin_function(miso, pinmap_find_function(miso, PinMap_SPI_MISO));
    ioport_disable_pin(miso);

    pin_function(sclk, pinmap_find_function(sclk, PinMap_SPI_SCLK));
    ioport_disable_pin(sclk);
	
	#if (SAMG55)
	/* Enable the peripheral and set SPI mode. */
	flexcom_enable(obj->spi.flexcom);
	flexcom_set_opmode(obj->spi.flexcom, FLEXCOM_SPI);
	#else
	/* Configure an SPI peripheral. */
	spi_enable_clock(sercombase);
	#endif
	spi_disable(sercombase);
	spi_reset(sercombase);
	spi_set_lastxfer(sercombase);
	spi_set_master_mode(sercombase);
	spi_disable_mode_fault_detect(sercombase);
	spi_set_peripheral_chip_select_value(sercombase, SPI_CHIP_SEL);
	spi_set_clock_polarity(sercombase, SPI_CHIP_SEL, SPI_CLK_POLARITY);
	spi_set_clock_phase(sercombase, SPI_CHIP_SEL, SPI_CLK_PHASE);
	spi_set_bits_per_transfer(sercombase, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(sercombase, SPI_CHIP_SEL,(sysclk_get_cpu_hz() / gSPI_clock));
	spi_set_transfer_delay(sercombase, SPI_CHIP_SEL, SPI_DLYBS,SPI_DLYBCT);
	
	spi_enable(sercombase);

	pdc_disable_transfer(obj->spi.pdc, PERIPH_PTCR_RXTDIS |	PERIPH_PTCR_TXTDIS);

	obj->spi.spi_base=sercombase;
	obj->spi.cs= SPI_CHIP_SEL;
	obj->spi.polarity=SPI_CLK_POLARITY;
	obj->spi.phase=SPI_CLK_PHASE;
	obj->spi.transferrate=SPI_CSR_BITS_8_BIT;
	obj->spi.is_slave=0;
}
/*
 *	@fn		nm_bus_init
 *	@brief	Initialize the bus wrapper
 *	@return	M2M_SUCCESS in case of success and M2M_ERR_BUS_FAIL in case of failure
 */
sint8 nm_bus_init(void *pvinit)
{
	sint8 result = M2M_SUCCESS;
#ifdef CONF_WINC_USE_I2C
	twihs_options_t opt;

	/* Enable the peripheral clock for TWI */
	pmc_enable_periph_clk(CONF_WINC_I2C_ID);

	/* Configure the options of TWI driver */
	opt.master_clk = sysclk_get_peripheral_hz();
	opt.speed      = CONF_WINC_TWIHS_CLOCK;

	if (twihs_master_init(CONF_WINC_I2C, &opt) != TWIHS_SUCCESS) {
		M2M_ERR("-E-\tTWI master initialization failed.\r");
		while (1) {
			/* Capture error */
		}
	}

#elif CONF_WINC_USE_SPI
	/* Configure SPI pins. */
	ioport_set_pin_mode(CONF_WINC_SPI_MISO_GPIO, CONF_WINC_SPI_MISO_FLAGS);
	ioport_set_pin_mode(CONF_WINC_SPI_MOSI_GPIO, CONF_WINC_SPI_MOSI_FLAGS);
	ioport_set_pin_mode(CONF_WINC_SPI_CLK_GPIO, CONF_WINC_SPI_CLK_FLAGS);
	ioport_set_pin_mode(CONF_WINC_SPI_CS_GPIO, CONF_WINC_SPI_CS_FLAGS);
	ioport_disable_pin(CONF_WINC_SPI_MISO_GPIO);
	ioport_disable_pin(CONF_WINC_SPI_MOSI_GPIO);
	ioport_disable_pin(CONF_WINC_SPI_CLK_GPIO);
	ioport_disable_pin(CONF_WINC_SPI_CS_GPIO);

	spi_enable_clock(CONF_WINC_SPI);
	spi_disable(CONF_WINC_SPI);
	spi_reset(CONF_WINC_SPI);
	spi_set_master_mode(CONF_WINC_SPI);
	spi_disable_mode_fault_detect(CONF_WINC_SPI);
	spi_set_peripheral_chip_select_value(CONF_WINC_SPI, CONF_WINC_SPI_NPCS);
	spi_set_clock_polarity(CONF_WINC_SPI,
			CONF_WINC_SPI_NPCS, CONF_WINC_SPI_POL);
	spi_set_clock_phase(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_PHA);
	spi_set_bits_per_transfer(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(CONF_WINC_SPI, CONF_WINC_SPI_NPCS,
			(sysclk_get_cpu_hz() / CONF_WINC_SPI_CLOCK));
	spi_set_transfer_delay(CONF_WINC_SPI, CONF_WINC_SPI_NPCS, CONF_WINC_SPI_DLYBS,
			CONF_WINC_SPI_DLYBCT);
	spi_enable(CONF_WINC_SPI);

	nm_bsp_reset();
#endif
	return result;
}
Beispiel #5
0
spi_p spi_new_instance(Spi * spi_base, uint8_t spi_chip_sel, uint32_t spi_freq, uint8_t spi_mode, uint8_t buffer_size, void(*handler_call_back )(spi_p, uint8_t))
{
	_spi_base = spi_base;
	
	if (!spi_is_enabled(_spi_base)) {
		_spi_init_base(spi_base);
	}
	
	spi_p _spi = malloc(sizeof *_spi);
	
	_spi->_call_back = handler_call_back;
	_spi->_cs_pin = spi_chip_sel;
	_spi->_spi_rx_fifo_desc = (fifo_desc_t *)malloc(sizeof(fifo_desc_t));
	_spi->_spi_tx_fifo_desc = (fifo_desc_t *)malloc(sizeof(fifo_desc_t));
	
	union spi_buffer_element *spi_tx_fifo_buffer = (union spi_buffer_element *)(malloc(sizeof(union spi_buffer_element) * buffer_size));
	union spi_buffer_element *spi_rx_fifo_buffer = (union spi_buffer_element *)(malloc(sizeof(union spi_buffer_element) * buffer_size));
	fifo_init(_spi->_spi_rx_fifo_desc, spi_rx_fifo_buffer, buffer_size);
	fifo_init(_spi->_spi_tx_fifo_desc, spi_tx_fifo_buffer, buffer_size);
		
	spi_set_peripheral_chip_select_value(spi_base, spi_get_pcs(spi_chip_sel));
	switch (spi_mode)
	{
		case 0:
			spi_set_clock_polarity(spi_base, spi_chip_sel,0);
			spi_set_clock_phase(spi_base, spi_chip_sel, 1);
		break;
		case 1:
			spi_set_clock_polarity(spi_base, spi_chip_sel, 0);
			spi_set_clock_phase(spi_base, spi_chip_sel, 0);
		break;
		case 2:
			spi_set_clock_polarity(spi_base, spi_chip_sel, 1);
			spi_set_clock_phase(spi_base, spi_chip_sel, 1);
		break;
		case 3:
			spi_set_clock_polarity(spi_base, spi_chip_sel, 1);
			spi_set_clock_phase(spi_base, spi_chip_sel, 0);
		break;
	}

	spi_set_bits_per_transfer(spi_base, spi_chip_sel, SPI_CSR_BITS_8_BIT);
	spi_configure_cs_behavior(spi_base, spi_chip_sel, SPI_CS_KEEP_LOW);
	spi_set_baudrate_div(spi_base, spi_chip_sel, (sysclk_get_peripheral_hz() / spi_freq));
	spi_set_delay_between_chip_select(spi_base, 0x10);
	spi_set_transfer_delay(spi_base, spi_chip_sel, 0x01, 0x10);
	spi_enable(spi_base);
	
	return _spi;
}
Beispiel #6
0
/**
 * \brief Set up an SPI device.
 *
 * The returned device descriptor structure must be passed to the driver
 * whenever that device should be used as current slave device.
 *
 * \param p_spi     Base address of the SPI instance.
 * \param device    Pointer to SPI device struct that should be initialized.
 * \param flags     SPI configuration flags. Common flags for all
 *                  implementations are the SPI modes SPI_MODE_0 ...
 *                  SPI_MODE_3.
 * \param baud_rate Baud rate for communication with slave device in Hz.
 * \param sel_id    Board specific select id.
 */
void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
                             spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
{
    sel_id = sel_id;

    spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
                           CONFIG_SPI_MASTER_DELAY_BCT);
    spi_set_bits_per_transfer(p_spi, device->id,
                              CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
    spi_set_baudrate_div(p_spi, device->id,
                         spi_calc_baudrate_div(baud_rate, sysclk_get_cpu_hz()));
    spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
    spi_set_clock_polarity(p_spi, device->id, flags >> 1);
    spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
}
void cph_deca_spi_init(void)
{

	freertos_spi_if spi_if;

	const freertos_peripheral_options_t driver_options = {
	/* No receive buffer pointer needed for SPI */
	NULL,

	/* No receive buffer size needed for SPI */
	0,

	/* Cortex-M4 priority */
	configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY,

	/* Operation mode - MASTER */
	SPI_MASTER,

	/* Blocking (not async) */
	(USE_TX_ACCESS_MUTEX | USE_RX_ACCESS_MUTEX | WAIT_TX_COMPLETE | WAIT_RX_COMPLETE) };

	spi_if = freertos_spi_master_init(DW_SPI, &driver_options);

	if (spi_if != NULL) {
		pio_configure_pin(DW_MISO_PIO_IDX, DW_MISO_PERIPH);	// MISO
		pio_configure_pin(DW_MOSI_PIO_IDX, DW_MOSI_PERIPH);	// MOSI
		pio_configure_pin(DW_SPCK_PIO_IDX, DW_SPCK_PERIPH);	// SPCK
		pio_configure_pin(DW_CSn_PIO_IDX, DW_CSn_PIO_PERIPH);
		pmc_enable_periph_clk(ID_SPI);

		spi_disable(DW_SPI);
		spi_set_clock_polarity(DW_SPI, DW_CHIP_SELECT, DW_CLOCK_POLARITY);
		spi_set_clock_phase(DW_SPI, DW_CHIP_SELECT, DW_CLOCK_PHASE);
		spi_set_baudrate_div(DW_SPI, DW_CHIP_SELECT, (sysclk_get_cpu_hz() / DW_SPI_BAUD_SLOW));
		spi_set_transfer_delay(DW_SPI, DW_CHIP_SELECT, DW_DELAY_BEFORE,		DW_DELAY_BETWEEN);
//		spi_configure_cs_behavior(DW_SPI, DW_CHIP_SELECT, SPI_CS_KEEP_LOW);
		spi_configure_cs_behavior(DW_SPI, DW_CHIP_SELECT, SPI_CS_RISE_NO_TX);
		spi_set_peripheral_chip_select_value(DW_SPI, DW_CHIP_SELECT_VALUE);

		spi_enable(DW_SPI);
	}

//	return spi_if;


}
Beispiel #8
0
/**
 * \brief Set up an SPI device.
 *
 * The returned device descriptor structure must be passed to the driver
 * whenever that device should be used as current slave device.
 *
 * \param p_spi     Base address of the SPI instance.
 * \param device    Pointer to SPI device struct that should be initialized.
 * \param flags     SPI configuration flags. Common flags for all
 *                  implementations are the SPI modes SPI_MODE_0 ...
 *                  SPI_MODE_3.
 * \param baud_rate Baud rate for communication with slave device in Hz.
 * \param sel_id    Board specific select id.
 */
void spi_master_setup_device(Spi *p_spi, struct spi_device *device,
                             spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
{
    int16_t baud_div = spi_calc_baudrate_div(baud_rate, sysclk_get_cpu_hz());
    /* avoid Cppcheck Warning */
    UNUSED(sel_id);
    if (-1 == baud_div) {
        Assert(0 == "Failed to find baudrate divider");
    }
    spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
                           CONFIG_SPI_MASTER_DELAY_BCT);
    spi_set_bits_per_transfer(p_spi, device->id,
                              CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
    spi_set_baudrate_div(p_spi, device->id, baud_div);
    spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
    spi_set_clock_polarity(p_spi, device->id, flags >> 1);
    spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
}
Beispiel #9
0
/**
 * \brief Set up an SPI device.
 *
 * The returned device descriptor structure must be passed to the driver
 * whenever that device should be used as current slave device.
 *
 * \param p_spi     Base address of the SPI instance.
 * \param device    Pointer to SPI device struct that should be initialized.
 * \param flags     SPI configuration flags. Common flags for all
 *                  implementations are the SPI modes SPI_MODE_0 ...
 *                  SPI_MODE_3.
 * \param baud_rate Baud rate for communication with slave device in Hz.
 * \param sel_id    Board specific select id.
 */
void spi_master_setup_device(Spi *p_spi, const struct spi_device *device,
		spi_flags_t flags, uint32_t baud_rate, board_spi_select_id_t sel_id)
{
	/* avoid Cppcheck Warning */
	UNUSED(sel_id);
	UNUSED(flags);

	spi_reset(p_spi);
	spi_set_transfer_delay(p_spi, device->id, CONFIG_SPI_MASTER_DELAY_BS,
			CONFIG_SPI_MASTER_DELAY_BCT);
	spi_set_bits_per_transfer(p_spi, device->id,
			CONFIG_SPI_MASTER_BITS_PER_TRANSFER);
	int16_t baud_div = spi_calc_baudrate_div(baud_rate, SystemCoreClock);
	spi_set_baudrate_div(p_spi, device->id, baud_div);
	spi_configure_cs_behavior(p_spi, device->id, SPI_CS_KEEP_LOW);
	spi_set_clock_polarity(p_spi, device->id, flags >> 1);
	spi_set_clock_phase(p_spi, device->id, ((flags & 0x1) ^ 0x1));
}
Beispiel #10
0
/**
 * \brief Initialize SPI as master.
 */
static void radioSpiInit(void)
{
    /* Configure an SPI peripheral. */
    spi_enable_clock(SPI_MASTER_BASE);
    spi_disable(SPI_MASTER_BASE);
    spi_reset(SPI_MASTER_BASE);
    spi_set_lastxfer(SPI_MASTER_BASE);
    spi_set_master_mode(SPI_MASTER_BASE);
    spi_disable_mode_fault_detect(SPI_MASTER_BASE);
    spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_SEL);
    spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
    spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
    spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
    spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL,
                         (sysclk_get_cpu_hz() / gs_ul_spi_clock));
    spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS,
                           SPI_DLYBCT);
    spi_enable(SPI_MASTER_BASE);
}
Beispiel #11
0
platform_result_t platform_spi_init( const platform_spi_t* spi, const platform_spi_config_t* config )
{
    UNUSED_PARAMETER(spi);
    UNUSED_PARAMETER(config);

    platform_mcu_powersave_disable( );

    Pdc* spi_pdc = spi_get_pdc_base( spi->peripheral );

    /* Setup chip select pin */
    platform_gpio_init( config->chip_select, OUTPUT_PUSH_PULL );
    platform_gpio_output_high( config->chip_select );

    /* Setup other pins */
    platform_gpio_peripheral_pin_init( spi->mosi_pin, ( IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP ) );
    platform_gpio_peripheral_pin_init( spi->miso_pin, ( IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP ) );
    platform_gpio_peripheral_pin_init( spi->clk_pin,  ( IOPORT_MODE_MUX_A | IOPORT_MODE_PULLUP )  );

    /* Configure an SPI peripheral. */
    pmc_enable_periph_clk( spi->peripheral_id );
    spi_disable( spi->peripheral );
    spi_reset( spi->peripheral );
    spi_set_lastxfer( spi->peripheral );
    spi_set_master_mode( spi->peripheral );
    spi_disable_mode_fault_detect( spi->peripheral );
    spi_set_peripheral_chip_select_value( spi->peripheral, 0 );

    spi_set_clock_polarity( spi->peripheral, 0, ( ( config->mode && SPI_CLOCK_IDLE_HIGH )   ? (1) : (0) ) );
    spi_set_clock_phase( spi->peripheral, 0,    ( ( config->mode && SPI_CLOCK_RISING_EDGE ) ? (1) : (0) ) );

    spi_set_bits_per_transfer( spi->peripheral, 0, SPI_CSR_BITS_8_BIT );
    spi_set_baudrate_div( spi->peripheral, 0, (uint8_t)( CPU_CLOCK_HZ / config->speed ) );
    spi_set_transfer_delay( spi->peripheral, 0, 0, 0 );
    spi_enable( spi->peripheral );
    pdc_disable_transfer( spi_pdc, PERIPH_PTCR_RXTDIS | PERIPH_PTCR_TXTDIS );

    platform_mcu_powersave_enable( );

    return PLATFORM_SUCCESS;
}
Beispiel #12
0
/**
 * \brief Initialize SPI as master.
 */
static void spi_master_initialize(void)
{
	uint32_t i;
	
	puts("-I- Initialize SPI as master\r");
	
	for (i = 0; i < COMM_BUFFER_SIZE; i++) {
		gs_uc_spi_m_tbuffer[i] = i;
	}
	
	/* Get pointer to SPI master PDC register base */
	g_p_spim_pdc = spi_get_pdc_base(SPI_MASTER_BASE);

#if (SAMG55)
	/* Enable the peripheral and set SPI mode. */
	flexcom_enable(BOARD_FLEXCOM_SPI);
	flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
#else
	/* Configure an SPI peripheral. */
	pmc_enable_periph_clk(SPI_ID);
#endif
	spi_disable(SPI_MASTER_BASE);
	spi_reset(SPI_MASTER_BASE);
	spi_set_lastxfer(SPI_MASTER_BASE);
	spi_set_master_mode(SPI_MASTER_BASE);
	spi_disable_mode_fault_detect(SPI_MASTER_BASE);
	spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_SEL);
	spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
	spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL,
			SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL,
			(sysclk_get_cpu_hz() / gs_ul_spi_clock));
	spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS,
			SPI_DLYBCT);
	spi_enable(SPI_MASTER_BASE);
	
	pdc_disable_transfer(g_p_spim_pdc, PERIPH_PTCR_RXTDIS |
			PERIPH_PTCR_TXTDIS);
}
Beispiel #13
0
/*
*	Initialise the SPI interface as a MASTER
*
*/
void spi_master_initialize(void)
{
	/* Configure an SPI peripheral. */
	spi_enable_clock(SPI_MASTER_BASE);
	spi_disable(SPI_MASTER_BASE);
	spi_reset(SPI_MASTER_BASE);
	spi_set_master_mode(SPI_MASTER_BASE);
	spi_disable_mode_fault_detect(SPI_MASTER_BASE);
	spi_disable_loopback(SPI_MASTER_BASE);
	spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS);
	spi_set_fixed_peripheral_select(SPI_MASTER_BASE);
	spi_disable_peripheral_select_decode(SPI_MASTER_BASE);

	spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
	spi_configure_cs_behavior(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CS_KEEP_LOW);
	spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
	spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);

	spi_enable(SPI_MASTER_BASE);
}
Beispiel #14
0
/**
 * \brief Initialize SPI as master.
 */
static void spi_master_initialize(void)
{
	g_uc_role = MASTER_MODE;
	puts("-I- Initialize SPI as master\r");

	/* Configure an SPI peripheral. */
	spi_enable_clock(SPI_MASTER_BASE);
	spi_disable(SPI_MASTER_BASE);
	spi_reset(SPI_MASTER_BASE);
	spi_set_lastxfer(SPI_MASTER_BASE);
	spi_set_master_mode(SPI_MASTER_BASE);
	spi_disable_mode_fault_detect(SPI_MASTER_BASE);
	spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS);
	spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
	spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL,
			SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL,
			(sysclk_get_cpu_hz() / gs_ul_spi_clock));
	spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS,
			SPI_DLYBCT);
	spi_enable(SPI_MASTER_BASE);
}
Beispiel #15
0
OSStatus host_platform_bus_init( void )
{
#ifndef USE_OWN_SPI_DRV 
	struct spi_master_vec_config spi; 
#else
	pdc_packet_t pdc_spi_packet;
#endif
    OSStatus result;

    MCU_CLOCKS_NEEDED();

	spi_disable_interrupt(SPI_MASTER_BASE, 0xffffffff);
    //Disable_global_interrupt();//TBD!

    result = mico_rtos_init_semaphore( &spi_transfer_finished_semaphore, 1 );
    if ( result != kNoErr )
    {
        return result;
    }
    
    mico_gpio_initialize( (mico_gpio_t)MICO_GPIO_9, INPUT_PULL_UP );
    //ioport_port_mask_t ul_mask = ioport_pin_to_mask(CREATE_IOPORT_PIN(PORTA,24));
    //pio_set_input(PIOA,ul_mask, PIO_PULLUP|PIO_DEBOUNCE);
    mico_gpio_enable_IRQ( (mico_gpio_t)MICO_GPIO_9, IRQ_TRIGGER_RISING_EDGE, spi_irq_handler, NULL );
#ifndef HARD_CS_NSS0	
    mico_gpio_initialize( MICO_GPIO_15, OUTPUT_PUSH_PULL);//spi ss/cs 
	mico_gpio_output_high( MICO_GPIO_15 );//MICO_GPIO_15 TBD!
#else
	ioport_set_pin_peripheral_mode(SPI_NPCS0_GPIO, SPI_NPCS0_FLAGS);//TBD!
#endif
    /* set PORTB 01 to high to put WLAN module into g_SPI mode */
    mico_gpio_initialize( (mico_gpio_t)WL_GPIO0, OUTPUT_PUSH_PULL );
    mico_gpio_output_high( (mico_gpio_t)WL_GPIO0 );
#ifdef USE_OWN_SPI_DRV 
#if (SAMG55)
	/* Enable the peripheral and set SPI mode. */
	flexcom_enable(BOARD_FLEXCOM_SPI);
	flexcom_set_opmode(BOARD_FLEXCOM_SPI, FLEXCOM_SPI);
#else
	/* Configure an SPI peripheral. */
	pmc_enable_periph_clk(SPI_ID);
#endif
    //Init pdc, and clear RX TX.
    spi_m_pdc = spi_get_pdc_base(SPI_MASTER_BASE);

	pdc_spi_packet.ul_addr = NULL;
	pdc_spi_packet.ul_size = 3;
	pdc_tx_init(spi_m_pdc, &pdc_spi_packet, NULL);
	pdc_rx_init(spi_m_pdc, &pdc_spi_packet, NULL);

	spi_disable(SPI_MASTER_BASE);
	spi_reset(SPI_MASTER_BASE);
	spi_set_lastxfer(SPI_MASTER_BASE);
	spi_set_master_mode(SPI_MASTER_BASE);
	spi_disable_mode_fault_detect(SPI_MASTER_BASE);
#ifdef HARD_CS_NSS0
	//spi_enable_peripheral_select_decode(SPI_MASTER_BASE);
	//spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_SEL);
	spi_set_peripheral_chip_select_value(SPI_MASTER_BASE, SPI_CHIP_PCS); //use soft nss comment here
#endif
	spi_set_clock_polarity(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_POLARITY);
	spi_set_clock_phase(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CLK_PHASE);
	spi_set_bits_per_transfer(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(SPI_MASTER_BASE, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / SPI_BAUD_RATE));
	spi_set_transfer_delay(SPI_MASTER_BASE, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);

    /* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */
    /* otherwise FreeRTOS will not be able to mask the interrupt */
    /* keep in mind that ARMCM3 interrupt priority logic is inverted, the highest value */
    /* is the lowest priority */
	/* Configure SPI interrupts . */
    spi_enable_interrupt(SPI_MASTER_BASE, SPI_IER_RXBUFF);
    //spi_enable_interrupt(SPI_MASTER_BASE, SPI_IER_NSSR | SPI_IER_RXBUFF);
	
	NVIC_DisableIRQ(SPI_IRQn);
    //irq_register_handler(SPI_IRQn, 3);
	NVIC_ClearPendingIRQ(SPI_IRQn);
	NVIC_SetPriority(SPI_IRQn, 3);
	NVIC_EnableIRQ(SPI_IRQn);

    spi_enable(SPI_MASTER_BASE);
#else
    spi.baudrate = SPI_BAUD_RATE;
	if (STATUS_OK != spi_master_vec_init(&spi_master, SPI_MASTER_BASE, &spi)) {
		return -1;
	}

	spi_master_vec_enable(&spi_master);
#endif
    //if (!Is_global_interrupt_enabled())
    //    Enable_global_interrupt();
    MCU_CLOCKS_NOT_NEEDED();

    return kNoErr;
}
Beispiel #16
0
OSStatus host_platform_bus_init( void )
{
  pdc_packet_t  pdc_spi_packet;
  Pdc*          spi_pdc  = spi_get_pdc_base( wifi_spi.port );
  
  platform_mcu_powersave_disable( );
  
  mico_rtos_init_semaphore( &spi_transfer_finished_semaphore, 1 );
  
  /* Setup the SPI lines */
  platform_gpio_peripheral_pin_init(  wifi_spi.mosi_pin,  ( wifi_spi.mosi_pin_mux_mode | IOPORT_MODE_PULLUP ) );
  platform_gpio_peripheral_pin_init(  wifi_spi.miso_pin,  ( wifi_spi.miso_pin_mux_mode | IOPORT_MODE_PULLUP ) );
  platform_gpio_peripheral_pin_init(  wifi_spi.clock_pin, ( wifi_spi.clock_pin_mux_mode | IOPORT_MODE_PULLUP ) );
  
  /* Setup the interrupt input for WLAN_IRQ */
  platform_gpio_init( &wifi_spi_pins[WIFI_PIN_SPI_IRQ], INPUT_HIGH_IMPEDANCE );
  platform_gpio_irq_enable( &wifi_spi_pins[WIFI_PIN_SPI_IRQ], IRQ_TRIGGER_RISING_EDGE, spi_irq_handler, 0 );
  
  /* Setup SPI slave select GPIOs */
  platform_gpio_init( &wifi_spi_pins[WIFI_PIN_SPI_CS], OUTPUT_PUSH_PULL );
  platform_gpio_output_high( &wifi_spi_pins[WIFI_PIN_SPI_CS] );
  
#if defined ( MICO_WIFI_USE_GPIO_FOR_BOOTSTRAP )
  /* Set GPIO_B[1:0] to 01 to put WLAN module into gSPI mode */
  platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0], OUTPUT_PUSH_PULL );
  platform_gpio_output_high( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_0] );
  platform_gpio_init( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1], OUTPUT_PUSH_PULL );
  platform_gpio_output_low( &wifi_control_pins[WIFI_PIN_BOOTSTRAP_1] );
#endif
  
  /* Enable the peripheral and set SPI mode. */
  flexcom_enable( flexcom_base[ wifi_spi.spi_id ] );
  flexcom_set_opmode( flexcom_base[ wifi_spi.spi_id ], FLEXCOM_SPI );
  
  /* Init pdc, and clear RX TX. */
  pdc_spi_packet.ul_addr = 0;
  pdc_spi_packet.ul_size = 1;
  pdc_tx_init( spi_pdc, &pdc_spi_packet, NULL );
  pdc_rx_init( spi_pdc, &pdc_spi_packet, NULL );
  
  spi_disable_interrupt(wifi_spi.port, 0xffffffff );
  spi_disable( wifi_spi.port );
  spi_reset( wifi_spi.port );
  spi_set_lastxfer( wifi_spi.port );
  spi_set_master_mode( wifi_spi.port );
  spi_disable_mode_fault_detect( wifi_spi.port );
  
  spi_set_clock_polarity( wifi_spi.port, 0, SPI_CLK_POLARITY );
  spi_set_clock_phase( wifi_spi.port, 0, SPI_CLK_PHASE );
  spi_set_bits_per_transfer( wifi_spi.port, 0, SPI_CSR_BITS_8_BIT );
  spi_set_baudrate_div( wifi_spi.port, 0, (sysclk_get_cpu_hz() / SPI_BAUD_RATE) );
  spi_set_transfer_delay( wifi_spi.port, 0, 0, 0 );
  
  /* Must be lower priority than the value of configMAX_SYSCALL_INTERRUPT_PRIORITY */
  /* otherwise FreeRTOS will not be able to mask the interrupt */
  /* keep in mind that ARMCM4 interrupt priority logic is inverted, the highest value */
  /* is the lowest priority */
  /* Configure SPI interrupts . */
  
  NVIC_EnableIRQ( platform_flexcom_irq_numbers[wifi_spi.spi_id] );
  
  spi_enable(wifi_spi.port);
  
  platform_mcu_powersave_enable( );
  
  return kNoErr;
}
Beispiel #17
0
/**
 * \brief KSZ8851SNL initialization function.
 *
 * \return 0 on success, 1 on communication error.
 */
uint32_t ksz8851snl_init(void)
{
    uint32_t count = 0;
    uint16_t dev_id = 0;

    /* Configure the SPI peripheral. */
    spi_enable_clock(KSZ8851SNL_SPI);
    spi_disable(KSZ8851SNL_SPI);
    spi_reset(KSZ8851SNL_SPI);
    spi_set_master_mode(KSZ8851SNL_SPI);
    spi_disable_mode_fault_detect(KSZ8851SNL_SPI);
    spi_set_peripheral_chip_select_value(KSZ8851SNL_SPI, ~(uint32_t)(1 << KSZ8851SNL_CS_PIN));
    spi_set_clock_polarity(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_POLARITY);
    spi_set_clock_phase(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_PHASE);
    spi_set_bits_per_transfer(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN,
                              SPI_CSR_BITS_8_BIT);
    spi_set_baudrate_div(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, (sysclk_get_cpu_hz() / KSZ8851SNL_CLOCK_SPEED));
    spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, CONFIG_SPI_MASTER_DELAY_BS,
                           CONFIG_SPI_MASTER_DELAY_BCT);
    spi_enable(KSZ8851SNL_SPI);

    /* Get pointer to UART PDC register base. */
    g_p_spi_pdc = spi_get_pdc_base(KSZ8851SNL_SPI);
    pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);

    /* Control RSTN and CSN pin from the driver. */
    gpio_configure_pin(KSZ8851SNL_CSN_GPIO, KSZ8851SNL_CSN_FLAGS);
    gpio_set_pin_high(KSZ8851SNL_CSN_GPIO);
    gpio_configure_pin(KSZ8851SNL_RSTN_GPIO, KSZ8851SNL_RSTN_FLAGS);

    /* Reset the Micrel in a proper state. */
    do {
        /* Perform hardware reset with respect to the reset timing from the datasheet. */
        gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO);
        delay_ms(100);
        gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO);
        delay_ms(100);

        /* Init step1: read chip ID. */
        dev_id = ksz8851_reg_read(REG_CHIP_ID);
        if (++count > 10)
            return 1;
    } while ((dev_id & 0xFFF0) != CHIP_ID_8851_16);

    /* Init step2-4: write QMU MAC address (low, middle then high). */
    ksz8851_reg_write(REG_MAC_ADDR_0, (ETHERNET_CONF_ETHADDR4 << 8) | ETHERNET_CONF_ETHADDR5);
    ksz8851_reg_write(REG_MAC_ADDR_2, (ETHERNET_CONF_ETHADDR2 << 8) | ETHERNET_CONF_ETHADDR3);
    ksz8851_reg_write(REG_MAC_ADDR_4, (ETHERNET_CONF_ETHADDR0 << 8) | ETHERNET_CONF_ETHADDR1);

    /* Init step5: enable QMU Transmit Frame Data Pointer Auto Increment. */
    ksz8851_reg_write(REG_TX_ADDR_PTR, ADDR_PTR_AUTO_INC);

    /* Init step6: configure QMU transmit control register. */
    ksz8851_reg_write(REG_TX_CTRL,
                      TX_CTRL_ICMP_CHECKSUM |
                      TX_CTRL_UDP_CHECKSUM |
                      TX_CTRL_TCP_CHECKSUM |
                      TX_CTRL_IP_CHECKSUM |
                      TX_CTRL_FLOW_ENABLE |
                      TX_CTRL_PAD_ENABLE |
                      TX_CTRL_CRC_ENABLE
                     );

    /* Init step7: enable QMU Receive Frame Data Pointer Auto Increment. */
    ksz8851_reg_write(REG_RX_ADDR_PTR, ADDR_PTR_AUTO_INC);

    /* Init step8: configure QMU Receive Frame Threshold for one frame. */
    ksz8851_reg_write(REG_RX_FRAME_CNT_THRES, 1);

    /* Init step9: configure QMU receive control register1. */
    ksz8851_reg_write(REG_RX_CTRL1,
                      RX_CTRL_UDP_CHECKSUM |
                      RX_CTRL_TCP_CHECKSUM |
                      RX_CTRL_IP_CHECKSUM |
                      RX_CTRL_MAC_FILTER |
                      RX_CTRL_FLOW_ENABLE |
                      RX_CTRL_BROADCAST |
                      RX_CTRL_ALL_MULTICAST|
                      RX_CTRL_UNICAST);

    /* Init step10: configure QMU receive control register2. */
    ksz8851_reg_write(REG_RX_CTRL2,
                      RX_CTRL_IPV6_UDP_NOCHECKSUM |
                      RX_CTRL_UDP_LITE_CHECKSUM |
                      RX_CTRL_ICMP_CHECKSUM |
                      RX_CTRL_BURST_LEN_FRAME);

    /* Init step11: configure QMU receive queue: trigger INT and auto-dequeue frame. */
    ksz8851_reg_write(REG_RXQ_CMD, RXQ_CMD_CNTL);

    /* Init step12: adjust SPI data output delay. */
    ksz8851_reg_write(REG_BUS_CLOCK_CTRL, BUS_CLOCK_166 | BUS_CLOCK_DIVIDEDBY_1);

    /* Init step13: restart auto-negotiation. */
    ksz8851_reg_setbits(REG_PORT_CTRL, PORT_AUTO_NEG_RESTART);

    /* Init step13.1: force link in half duplex if auto-negotiation failed. */
    if ((ksz8851_reg_read(REG_PORT_CTRL) & PORT_AUTO_NEG_RESTART) != PORT_AUTO_NEG_RESTART)
    {
        ksz8851_reg_clrbits(REG_PORT_CTRL, PORT_FORCE_FULL_DUPLEX);
    }

    /* Init step14: clear interrupt status. */
    ksz8851_reg_write(REG_INT_STATUS, 0xFFFF);

    /* Init step15: set interrupt mask. */
    ksz8851_reg_write(REG_INT_MASK, INT_RX);

    /* Init step16: enable QMU Transmit. */
    ksz8851_reg_setbits(REG_TX_CTRL, TX_CTRL_ENABLE);

    /* Init step17: enable QMU Receive. */
    ksz8851_reg_setbits(REG_RX_CTRL1, RX_CTRL_ENABLE);

    return 0;
}
Beispiel #18
0
/**
 * \brief KSZ8851SNL initialization function.
 *
 * \return 0 on success, 1 on communication error.
 */
uint32_t ksz8851snl_init(void)
{
uint32_t count = 10;
uint16_t dev_id = 0;
uint8_t id_ok = 0;

	/* Configure the SPI peripheral. */
	spi_enable_clock(KSZ8851SNL_SPI);
	spi_disable(KSZ8851SNL_SPI);
	spi_reset(KSZ8851SNL_SPI);
	spi_set_master_mode(KSZ8851SNL_SPI);
	spi_disable_mode_fault_detect(KSZ8851SNL_SPI);
	spi_set_peripheral_chip_select_value(KSZ8851SNL_SPI, ~(uint32_t)(1UL << KSZ8851SNL_CS_PIN));
spi_set_fixed_peripheral_select(KSZ8851SNL_SPI);
//spi_disable_peripheral_select_decode(KSZ8851SNL_SPI);

	spi_set_clock_polarity(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_POLARITY);
	spi_set_clock_phase(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, SPI_CLK_PHASE);
	spi_set_bits_per_transfer(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN,
			SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, (sysclk_get_cpu_hz() / KSZ8851SNL_CLOCK_SPEED));
//	spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, CONFIG_SPI_MASTER_DELAY_BS,
//			CONFIG_SPI_MASTER_DELAY_BCT);


	spi_set_transfer_delay(KSZ8851SNL_SPI, KSZ8851SNL_CS_PIN, 0, 0);

	spi_enable(KSZ8851SNL_SPI);

	/* Get pointer to UART PDC register base. */
	g_p_spi_pdc = spi_get_pdc_base(KSZ8851SNL_SPI);
	pdc_enable_transfer(g_p_spi_pdc, PERIPH_PTCR_RXTEN | PERIPH_PTCR_TXTEN);

	/* Control RSTN and CSN pin from the driver. */
	gpio_configure_pin(KSZ8851SNL_CSN_GPIO, KSZ8851SNL_CSN_FLAGS);
	gpio_set_pin_high(KSZ8851SNL_CSN_GPIO);
	gpio_configure_pin(KSZ8851SNL_RSTN_GPIO, KSZ8851SNL_RSTN_FLAGS);

	/* Reset the Micrel in a proper state. */
	while( count-- )
	{
		/* Perform hardware reset with respect to the reset timing from the datasheet. */
		gpio_set_pin_low(KSZ8851SNL_RSTN_GPIO);
		vTaskDelay(2);
		gpio_set_pin_high(KSZ8851SNL_RSTN_GPIO);
		vTaskDelay(2);

		/* Init step1: read chip ID. */
		dev_id = ksz8851_reg_read(REG_CHIP_ID);
		if( ( dev_id & 0xFFF0 ) == CHIP_ID_8851_16 )
		{
			id_ok = 1;
			break;
		}
	}
	if( id_ok != 0 )
	{
		ksz8851snl_set_registers();
	}

	return id_ok ? 1 : -1;
}
Beispiel #19
0
/**
 * \brief Test SPI transfer.
 *
 * This test tests SPI read/write.
 *
 * \param test Current test case.
 */
static void run_spi_trans_test(const struct test_case *test)
{
	spi_status_t rc;
	uint16_t     spi_data;
	uint8_t      spi_pcs;

	spi_reset(CONF_TEST_SPI);
	spi_set_lastxfer(CONF_TEST_SPI);
	spi_set_master_mode(CONF_TEST_SPI);
	spi_disable_mode_fault_detect(CONF_TEST_SPI);
	spi_set_peripheral_chip_select_value(CONF_TEST_SPI, CONF_TEST_SPI_NPCS);
	spi_set_clock_polarity(CONF_TEST_SPI,
		CONF_TEST_SPI_NPCS, SPI_CLK_POLARITY);
	spi_set_clock_phase(CONF_TEST_SPI, CONF_TEST_SPI_NPCS, SPI_CLK_PHASE);
	spi_set_bits_per_transfer(CONF_TEST_SPI,
		CONF_TEST_SPI_NPCS, SPI_CSR_BITS_8_BIT);
	spi_set_baudrate_div(CONF_TEST_SPI,
		CONF_TEST_SPI_NPCS,
		(sysclk_get_cpu_hz() / TEST_CLOCK));
	spi_set_transfer_delay(CONF_TEST_SPI,
		CONF_TEST_SPI_NPCS, SPI_DLYBS, SPI_DLYBCT);
	spi_set_variable_peripheral_select(CONF_TEST_SPI);
	spi_enable_loopback(CONF_TEST_SPI);

	/* Test read/write timeout: should return SPI_ERROR_TIMEOUT. */
	rc = spi_write(CONF_TEST_SPI, TEST_PATTERN, TEST_PCS, 1);
	test_assert_true(test, rc == SPI_ERROR_TIMEOUT,
		"Test SPI Write timeout: return code should not be %d", rc);

	rc = spi_read(CONF_TEST_SPI, &spi_data, &spi_pcs);
	test_assert_true(test, rc == SPI_ERROR_TIMEOUT,
		"Test SPI Read timeout: return code should not be %d", rc);

	spi_enable(CONF_TEST_SPI);
	spi_enable_interrupt(CONF_TEST_SPI, SPI_IER_TDRE|SPI_IER_RDRF);
	NVIC_EnableIRQ((IRQn_Type)CONF_TEST_SPI_ID);

	/* Test write: should return OK. */
	rc = spi_write(CONF_TEST_SPI, TEST_PATTERN, TEST_PCS, 1);
	test_assert_true(test, rc == SPI_OK,
		"Test SPI Write: return code should not be %d", rc);

	/* Test read: should return OK with what is sent. */
	rc = spi_read(CONF_TEST_SPI, &spi_data, &spi_pcs);
	test_assert_true(test, rc == SPI_OK,
		"Test SPI Read: return code should not be %d", rc);
	test_assert_true(test, spi_data == TEST_PATTERN,
		"Unexpected SPI data: %x, should be %x",
		spi_data, TEST_PATTERN);
	test_assert_true(test, spi_pcs == TEST_PCS,
		"Unexpected SPI PCS: %x, should be %x",
		spi_pcs, TEST_PCS);

	/* Check interrupts. */
	test_assert_true(test, g_b_spi_interrupt_tx_ready,
		"Test SPI TX interrupt not detected");
	test_assert_true(test, g_b_spi_interrupt_rx_ready,
		"Test SPI RX interrupt not detected");

	/* Done, disable SPI and all interrupts. */
	spi_disable_loopback(CONF_TEST_SPI);
	spi_disable(CONF_TEST_SPI);
	spi_disable_interrupt(CONF_TEST_SPI, 0xFFFFFFFF);
	NVIC_DisableIRQ((IRQn_Type)CONF_TEST_SPI_ID);
}
Beispiel #20
0
// Here should be all the initialization functions for the module before 12v power
void init_module_peripherals_bp(void)
{
	/* LEDs IO */
	pmc_enable_periph_clk(IN_CLK_LED1_PIO_ID);
	ioport_set_pin_dir(IN_CLK_LED1_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(IN_CLK_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
	pmc_enable_periph_clk(IN_CLK_LED2_PIO_ID);
	ioport_set_pin_dir(IN_CLK_LED2_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(IN_CLK_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
	pmc_enable_periph_clk(IN_CLK_LED3_PIO_ID);
	ioport_set_pin_dir(IN_CLK_LED3_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(IN_CLK_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);	
	pmc_enable_periph_clk(IN_DAT_LED1_PIO_ID);
	ioport_set_pin_dir(IN_DAT_LED1_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(IN_DAT_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
	pmc_enable_periph_clk(IN_DAT_LED2_PIO_ID);
	ioport_set_pin_dir(IN_DAT_LED2_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(IN_DAT_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
	pmc_enable_periph_clk(IN_DAT_LED3_PIO_ID);
	ioport_set_pin_dir(IN_DAT_LED3_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(IN_DAT_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);	
	pmc_enable_periph_clk(OUT_CH1_CH2_LED1_PIO_ID);
	ioport_set_pin_dir(OUT_CH1_CH2_LED1_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(OUT_CH1_CH2_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
	pmc_enable_periph_clk(OUT_CH1_CH2_LED2_PIO_ID);
	ioport_set_pin_dir(OUT_CH1_CH2_LED2_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(OUT_CH1_CH2_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
	pmc_enable_periph_clk(OUT_CH1_CH2_LED3_PIO_ID);
	ioport_set_pin_dir(OUT_CH1_CH2_LED3_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(OUT_CH1_CH2_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);	
	pmc_enable_periph_clk(OUT_CH3_LED1_PIO_ID);
	ioport_set_pin_dir(OUT_CH3_LED1_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(OUT_CH3_LED1_GPIO, IOPORT_PIN_LEVEL_HIGH);
	pmc_enable_periph_clk(OUT_CH3_LED2_PIO_ID);
	ioport_set_pin_dir(OUT_CH3_LED2_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(OUT_CH3_LED2_GPIO, IOPORT_PIN_LEVEL_HIGH);
	pmc_enable_periph_clk(OUT_CH3_LED3_PIO_ID);
	ioport_set_pin_dir(OUT_CH3_LED3_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(OUT_CH3_LED3_GPIO, IOPORT_PIN_LEVEL_HIGH);
	
	/* Pulse inputs/state & d reset output */
	pmc_enable_periph_clk(OUT_PULSE_DET_PIO_ID);
	ioport_set_pin_dir(OUT_PULSE_DET_GPIO, IOPORT_DIR_INPUT);
	pmc_enable_periph_clk(DATA_IN_DET_PIO_ID);
	ioport_set_pin_dir(DATA_IN_DET_GPIO, IOPORT_DIR_INPUT);
	pmc_enable_periph_clk(CLK_IN_DET_PIO_ID);
	ioport_set_pin_dir(CLK_IN_DET_GPIO, IOPORT_DIR_INPUT);	
	pmc_enable_periph_clk(OUT_PULSE_STATE_PIO_ID);
	ioport_set_pin_dir(OUT_PULSE_STATE_GPIO, IOPORT_DIR_INPUT);
	pmc_enable_periph_clk(DATA_IN_STATE_PIO_ID);
	ioport_set_pin_dir(DATA_IN_STATE_GPIO, IOPORT_DIR_INPUT);
	pmc_enable_periph_clk(CLK_IN_STATE_PIO_ID);
	ioport_set_pin_dir(CLK_IN_STATE_GPIO, IOPORT_DIR_INPUT);	
	pmc_enable_periph_clk(OUT_PULSE_RST_PIO_ID);
	ioport_set_pin_dir(OUT_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(OUT_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);	
	pmc_enable_periph_clk(DATA_PULSE_RST_PIO_ID);
	ioport_set_pin_dir(DATA_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(DATA_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);	
	pmc_enable_periph_clk(CLK_PULSE_RST_PIO_ID);
	ioport_set_pin_dir(CLK_PULSE_RST_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(CLK_PULSE_RST_GPIO, IOPORT_PIN_LEVEL_LOW);
	
	/* Sload */
	pmc_enable_periph_clk(DATA_DELAY_SLOAD_PIO_ID);
	ioport_set_pin_dir(DATA_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(DATA_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
	pmc_enable_periph_clk(CLOCK_DELAY_SLOAD_PIO_ID);
	ioport_set_pin_dir(CLOCK_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(CLOCK_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
	pmc_enable_periph_clk(RESET_DELAY_SLOAD_PIO_ID);
	ioport_set_pin_dir(RESET_DELAY_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(RESET_DELAY_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);
	pmc_enable_periph_clk(RF_ATTEN_SLOAD_PIO_ID);
	ioport_set_pin_dir(RF_ATTEN_SLOAD_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(RF_ATTEN_SLOAD_GPIO, IOPORT_PIN_LEVEL_LOW);

	/* Delay enables */
	pmc_enable_periph_clk(DATA_DELAY_EN_PIO_ID);
	ioport_set_pin_dir(DATA_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(DATA_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH);	// default state is HIGH (OG 10.04.2014)
	pmc_enable_periph_clk(CLOCK_DELAY_EN_PIO_ID);
	ioport_set_pin_dir(CLOCK_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(CLOCK_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH);	// default state is HIGH (OG 10.04.2014)
	pmc_enable_periph_clk(RESET_DELAY_EN_PIO_ID);
	ioport_set_pin_dir(RESET_DELAY_EN_GPIO, IOPORT_DIR_OUTPUT);
	ioport_set_pin_level(RESET_DELAY_EN_GPIO, IOPORT_PIN_LEVEL_HIGH);	// default state is HIGH (OG 10.04.2014)
	
		
	// Init LED interrupt,
	uint32_t ul_div;
	uint32_t ul_tcclks;
	/* Get system clock. */
	uint32_t ul_sysclk = sysclk_get_cpu_hz();
	/* Configure PMC. */
	pmc_enable_periph_clk(ID_TC1);
	/* Configure TC for a TC_FREQ frequency and trigger on RC compare. */
	tc_find_mck_divisor(20, ul_sysclk, &ul_div, &ul_tcclks, ul_sysclk);
	tc_init(TC0, 1, ul_tcclks | TC_CMR_CPCTRG);
	tc_write_rc(TC0, 1, (ul_sysclk / ul_div) / 20);
	/* Configure and enable interrupt on RC compare. */
	tc_start(TC0, 1);
	NVIC_DisableIRQ(TC1_IRQn);
	NVIC_ClearPendingIRQ(TC1_IRQn);
	//NVIC_SetPriority(TC1_IRQn, 0);
	NVIC_EnableIRQ((IRQn_Type)ID_TC1);
	tc_enable_interrupt(TC0, 1, TC_IER_CPCS);

	/* SPI interface */
	gpio_configure_pin(SPI0_MISO_GPIO, SPI0_MISO_FLAGS);
	gpio_configure_pin(SPI0_MOSI_GPIO, SPI0_MOSI_FLAGS);
	gpio_configure_pin(SPI0_SPCK_GPIO, SPI0_SPCK_FLAGS);
	//gpio_configure_pin(SPI0_NPCS0_GPIO, SPI0_NPCS0_FLAGS); // Controled by software
	
	/* Configure an SPI peripheral. */
	spi_enable_clock(SPI0);
	spi_disable(SPI0);
	spi_reset(SPI0);
	spi_set_lastxfer(SPI0);
	spi_set_master_mode(SPI0);
	spi_disable_mode_fault_detect(SPI0);
	
	/* Set variable chip select */
	spi_set_variable_peripheral_select(SPI0);
	
	/* Configure delay SPI channel */
	spi_set_clock_polarity(SPI0, SPI_CHIP_SEL, SPI_CLK_POLARITY);
	spi_set_clock_phase(SPI0, SPI_CHIP_SEL, SPI_CLK_PHASE);
	spi_set_bits_per_transfer(SPI0, SPI_CHIP_SEL, SPI_CSR_BITS_11_BIT);
	spi_configure_cs_behavior(SPI0, SPI_CHIP_SEL, SPI_CS_RISE_FORCED);
	spi_set_baudrate_div(SPI0, SPI_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
	spi_set_transfer_delay(SPI0, SPI_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
	
	/* Configure RF atten SPI channel */
	spi_set_clock_polarity(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_POLARITY);
	spi_set_clock_phase(SPI0, SPI_ALT_CHIP_SEL, SPI_CLK_PHASE);
	spi_set_bits_per_transfer(SPI0, SPI_ALT_CHIP_SEL, SPI_CSR_BITS_16_BIT);
	spi_configure_cs_behavior(SPI0, SPI_ALT_CHIP_SEL, SPI_CS_RISE_FORCED);
	spi_set_baudrate_div(SPI0, SPI_ALT_CHIP_SEL, (sysclk_get_cpu_hz() / gs_ul_spi_clock));
	spi_set_transfer_delay(SPI0, SPI_ALT_CHIP_SEL, SPI_DLYBS, SPI_DLYBCT);
	
	/* Enable SPI */
	spi_enable(SPI0);
}
Beispiel #21
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/*
 * Configure the SPI hardware, including SPI clock speed, mode, delays, chip select pins
 * It uses values listed in
 */
void AJ_WSL_SPI_InitializeSPIController(void)
{
    uint32_t config;

    /* Initialize and enable DMA controller. */
    pmc_enable_periph_clk(ID_DMAC);
    dmac_init(DMAC);
    dmac_set_priority_mode(DMAC, DMAC_PRIORITY_ROUND_ROBIN);
    dmac_enable(DMAC);

    /* Configure DMA TX channel. */
    config = 0;
    config |= DMAC_CFG_DST_PER(AJ_SPI_TX_INDEX) |
              DMAC_CFG_DST_H2SEL |
              DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
    dmac_channel_set_configuration(DMAC, AJ_DMA_TX_CHANNEL, config);

    /* Configure DMA RX channel. */
    config = 0;
    config |= DMAC_CFG_SRC_PER(AJ_SPI_RX_INDEX) |
              DMAC_CFG_SRC_H2SEL |
              DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
    dmac_channel_set_configuration(DMAC, AJ_DMA_RX_CHANNEL, config);

    /* Enable receive channel interrupt for DMAC. */
    uint8_t* interruptEnableAddress = AJ_SPI_ISER1_IEN_ADDR;
    *interruptEnableAddress = AJ_SPI_DMAC_IEN_BIT;

    dmac_enable_interrupt(DMAC, (1 << AJ_DMA_RX_CHANNEL));
    dmac_enable_interrupt(DMAC, (1 << AJ_DMA_TX_CHANNEL));
    //AJ_WSL_DMA_Setup();
    dmac_channel_disable(DMAC, AJ_DMA_TX_CHANNEL);
    dmac_channel_disable(DMAC, AJ_DMA_RX_CHANNEL);

    /*
     * Configure the hardware to enable SPI and some output pins
     */
    {
        pmc_enable_periph_clk(ID_PIOA);
        pmc_enable_periph_clk(ID_PIOB);
        pmc_enable_periph_clk(ID_PIOC);
        pmc_enable_periph_clk(ID_PIOD);


        // make all of these pins controlled by the right I/O controller
        pio_configure_pin_group(PIOA, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_A);
        pio_configure_pin_group(PIOB, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_B);
        pio_configure_pin_group(PIOC, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_C);
        pio_configure_pin_group(PIOD, 0xFFFFFFFF, PIO_TYPE_PIO_PERIPH_D);


        /*
         * Reset the device by toggling the CHIP_POWER
         */
        ioport_set_pin_dir(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_DIR_OUTPUT);
        ioport_set_pin_level(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_PIN_LEVEL_LOW);
        AJ_Sleep(10);
        ioport_set_pin_level(AJ_WSL_SPI_CHIP_POWER_PIN, IOPORT_PIN_LEVEL_HIGH);


        /*
         * Reset the device by toggling the CHIP_PWD# signal
         */
        ioport_set_pin_dir(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_DIR_OUTPUT);
        ioport_set_pin_level(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_PIN_LEVEL_LOW);
        AJ_Sleep(10);
        ioport_set_pin_level(AJ_WSL_SPI_CHIP_PWD_PIN, IOPORT_PIN_LEVEL_HIGH);

        /* configure the pin that detects SPI data ready from the target chip */
        ioport_set_pin_dir(AJ_WSL_SPI_CHIP_SPI_INT_PIN, IOPORT_DIR_INPUT);
        ioport_set_pin_sense_mode(AJ_WSL_SPI_CHIP_SPI_INT_PIN, IOPORT_SENSE_LEVEL_LOW);

        pio_handler_set(PIOC, ID_PIOC, AJ_WSL_SPI_CHIP_SPI_INT_BIT, (PIO_PULLUP | PIO_IT_FALL_EDGE), &AJ_WSL_SPI_CHIP_SPI_ISR);
        pio_handler_set_priority(PIOD, (IRQn_Type) ID_PIOC, 0xB);
        pio_enable_interrupt(PIOC, AJ_WSL_SPI_CHIP_SPI_INT_BIT);
    }

    spi_enable_clock(AJ_WSL_SPI_DEVICE);
    spi_reset(AJ_WSL_SPI_DEVICE);
    spi_set_lastxfer(AJ_WSL_SPI_DEVICE);
    spi_set_master_mode(AJ_WSL_SPI_DEVICE);
    spi_disable_mode_fault_detect(AJ_WSL_SPI_DEVICE);
    spi_set_peripheral_chip_select_value(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS);
    spi_set_clock_polarity(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_CLOCK_POLARITY);
    spi_set_clock_phase(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_CLOCK_PHASE);
    spi_set_bits_per_transfer(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, SPI_CSR_BITS_8_BIT);
    spi_set_baudrate_div(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, (sysclk_get_cpu_hz() / AJ_WSL_SPI_CLOCK_RATE));
    spi_set_transfer_delay(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, AJ_WSL_SPI_DELAY_BEFORE_CLOCK, AJ_WSL_SPI_DELAY_BETWEEN_TRANSFERS);
    spi_set_fixed_peripheral_select(AJ_WSL_SPI_DEVICE);
    spi_configure_cs_behavior(AJ_WSL_SPI_DEVICE, AJ_WSL_SPI_DEVICE_NPCS, SPI_CS_RISE_FORCED);

    spi_enable_interrupt(AJ_WSL_SPI_DEVICE, SPI_IER_TDRE | SPI_IER_RDRF);
    spi_enable(AJ_WSL_SPI_DEVICE);
}