void skl_ipc_op_int_disable(struct sst_dsp *ctx) { /* disable IPC DONE interrupt */ sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL, SKL_ADSP_REG_HIPCCTL_DONE, 0); /* Disable IPC BUSY interrupt */ sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_HIPCCTL, SKL_ADSP_REG_HIPCCTL_BUSY, 0); }
static void skl_cldma_stream_run(struct sst_dsp *ctx, bool enable) { unsigned char val; int timeout; sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_CL_SD_CTL, CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable)); udelay(3); timeout = 300; do { /* waiting for hardware to report that the stream Run bit set */ val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) & CL_SD_CTL_RUN_MASK; if (enable && val) break; else if (!enable && !val) break; udelay(3); } while (--timeout); if (timeout == 0) dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable); }
static int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx) { int ret; dev_dbg(ctx->dev, "In %s\n", __func__); /* update bits */ sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CRST_MASK, 0); /* poll with timeout to check if operation successful */ ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CRST_MASK, 0, SKL_DSP_RESET_TO, "Unset reset"); if ((sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) & SKL_ADSPCS_CRST(SKL_DSP_CORES_MASK)) != 0) { dev_err(ctx->dev, "Unset reset state failed\n"); ret = -EIO; } return ret; }
static int skl_dsp_core_set_reset_state(struct sst_dsp *ctx, unsigned int core_mask) { int ret; /* update bits */ sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CRST_MASK(core_mask), SKL_ADSPCS_CRST_MASK(core_mask)); /* poll with timeout to check if operation successful */ ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CRST_MASK(core_mask), SKL_ADSPCS_CRST_MASK(core_mask), SKL_DSP_RESET_TO, "Set reset"); if ((sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) & SKL_ADSPCS_CRST_MASK(core_mask)) != SKL_ADSPCS_CRST_MASK(core_mask)) { dev_err(ctx->dev, "Set reset state failed: core_mask %x\n", core_mask); ret = -EIO; } return ret; }
int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask) { int ret; /* update bits */ sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_SPA_MASK(core_mask), SKL_ADSPCS_SPA_MASK(core_mask)); /* poll with timeout to check if operation successful */ ret = sst_dsp_register_poll(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CPA_MASK(core_mask), SKL_ADSPCS_CPA_MASK(core_mask), SKL_DSP_PU_TO, "Power up"); if ((sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_ADSPCS) & SKL_ADSPCS_CPA_MASK(core_mask)) != SKL_ADSPCS_CPA_MASK(core_mask)) { dev_err(ctx->dev, "DSP core power up failed: core_mask %x\n", core_mask); ret = -EIO; } return ret; }
static void skl_cldma_cleanup_spb(struct sst_dsp *ctx) { sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL, CL_SPBFIFO_SPBFCCTL_SPIBE_MASK, CL_SPBFIFO_SPBFCCTL_SPIBE(0)); sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0); }
static int skl_dsp_reset_core(struct sst_dsp *ctx, unsigned int core_mask) { /* stall core */ sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CSTALL_MASK(core_mask), SKL_ADSPCS_CSTALL_MASK(core_mask)); /* set reset state */ return skl_dsp_core_set_reset_state(ctx, core_mask); }
static void skl_cldma_setup_spb(struct sst_dsp *ctx, unsigned int size, bool enable) { if (enable) sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL, CL_SPBFIFO_SPBFCCTL_SPIBE_MASK, CL_SPBFIFO_SPBFCCTL_SPIBE(1)); sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size); }
int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask) { /* update bits */ sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_SPA_MASK(core_mask), 0); /* poll with timeout to check if operation successful */ return sst_dsp_register_poll(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CPA_MASK(core_mask), 0, SKL_DSP_PD_TO, "Power down"); }
static int cnl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask) { /* update bits */ sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS, CNL_ADSPCS_SPA(core_mask), CNL_ADSPCS_SPA(core_mask)); /* poll with timeout to check if operation successful */ return sst_dsp_register_poll(ctx, CNL_ADSP_REG_ADSPCS, CNL_ADSPCS_CPA(core_mask), CNL_ADSPCS_CPA(core_mask), CNL_DSP_PU_TO, "Power up"); }
static int cnl_dsp_core_unset_reset_state(struct sst_dsp *ctx, unsigned int core_mask) { /* update bits */ sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS, CNL_ADSPCS_CRST(core_mask), 0); /* poll with timeout to check if operation successful */ return sst_dsp_register_poll(ctx, CNL_ADSP_REG_ADSPCS, CNL_ADSPCS_CRST(core_mask), 0, CNL_DSP_RESET_TO, "Unset reset"); }
static int cnl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask) { int ret; /* unset reset state */ ret = cnl_dsp_core_unset_reset_state(ctx, core_mask); if (ret < 0) return ret; /* run core */ sst_dsp_shim_update_bits_unlocked(ctx, CNL_ADSP_REG_ADSPCS, CNL_ADSPCS_CSTALL(core_mask), 0); if (!is_cnl_dsp_core_enable(ctx, core_mask)) { cnl_dsp_reset_core(ctx, core_mask); dev_err(ctx->dev, "DSP core mask %#x enable failed\n", core_mask); ret = -EIO; } return ret; }
int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask) { int ret; /* unset reset state */ ret = skl_dsp_core_unset_reset_state(ctx, core_mask); if (ret < 0) return ret; /* run core */ dev_dbg(ctx->dev, "unstall/run core: core_mask = %x\n", core_mask); sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPCS, SKL_ADSPCS_CSTALL_MASK(core_mask), 0); if (!is_skl_dsp_core_enable(ctx, core_mask)) { skl_dsp_reset_core(ctx, core_mask); dev_err(ctx->dev, "DSP start core failed: core_mask %x\n", core_mask); ret = -EIO; } return ret; }
void skl_cldma_int_disable(struct sst_dsp *ctx) { sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0); }
void skl_ipc_int_disable(struct sst_dsp *ctx) { sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_IPC, 0); }